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| REJ09B0103-0600 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 H8S/2639, H8S/2638,H8S/2636, H8S/2630, H8S/2635 Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series Rev. 6.00 Revision Date: Feb 22, 2005 Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 6.00 Feb 22, 2005 page ii of lx Preface This LSI has the internal 32-bit H8S/2600 CPU and includes a variety of peripheral functions necessary for a system configuration. It serves as a high-performance microcomputer. The on-chip peripheral devices include a 16-bit timer pulse unit (TPU), a programmable pulse generator (PPG), a watchdog timer unit (WDT), a serial communication interface (SCI), an A/D converter, a motor control PWM timer (PWM), a PC brake controller and I/O ports. It also has an internal data transfer controller (DTC), which performs high-speed data transfer without using the CPU, thus enabling the use of the LSI as an embedded microcomputer in various advanced control systems. Two types of internal ROM are available: flash memory (F-ZTATTM*) and mask ROM. The LSI can be used flexibly in a wide range of applications from applied equipment with varied specifications and early production models to full-scale mass-produced products. Notes: The H8S/2635 and H8S/2634 are not equipped with a PPG, a PC brake controller, or a DTC. * F-ZTAT is a trademark of Renesas Technology Corp. Target users: This manual was written for users who will be using the H8S/2636, H8S/2638, H8S/2639, H8S/2630, H8S/2635, and H8S/2634 in the design of application systems. Members of this audience are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8S/2636, H8S/2638, H8S/2639, H8S/2630, H8S/2635, and H8S/2634 to the above audience. Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description of the instruction set. Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Programming Manual. * In order to understand the details of a register when its name is known The addresses, bits, and initial values of the registers are summarized in Appendix B, Internal I/O Registers. Example: Bit order: The MSB is on the left and the LSB is on the right. Rev. 6.00 Feb 22, 2005 page iii of lx Related manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ H8S/2636, H8S/2638, H8S/2639, H8S/2630, H8S/2635 Group manuals: Document Title H8S/2636, H8S/2638, H8S/2639, H8S/2630, H8S/2635 Hardware Manual H8S/2600 Series, H8S/2000 Series Programming Manual Document No. This manual REJ09B0139 User's manuals for development tools: Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual H8S, H8/300 Series Simulator/Debugger (for Windows) User's Manual H8S, H8/300 Series High-performance Embedded Workshop User's Manual Document No. REJ10B0058 ADE-702-037 ADE-702-201 Application Notes: Document Title H8S Family Technical Q & A Document No. REJ05B0397 Rev. 6.00 Feb 22, 2005 page iv of lx Main Revisions in This Edition Item All Preface iii Page Revision (See Manual for Details) H8S/2635 and H8S/2634 added Note amended Notes: The H8S/2635 and H8S/2634 are not equipped with a PPG, a PC brake controller, or a DTC. * F-ZTAT is a trademark of Renesas Technology Corp. Target users: This manual was written for users who will be using the H8S/2636, H8S/2638, H8S/2639, H8S/2630, H8S/2635, and H8S/2634 in the design of application systems. ... 1.1 Overview 1 Description amended The H8S/2636, H8S/2638, H8S/2639, H8S/2630, H8S/2635, and H8S/2634 are microcomputers (MCUs: microcomputer units), built around ... On-chip ROM is available as 128-kbyte, 192-kbyte, 256-kbyte, and 384-kbyte flash memory (F-ZTATTM* version), and as 128-kbyte, 192-kbyte, 256-kbyte, and 384kbyte mask ROM. ... The features of the H8S/2636, H8S/2638, H8S/2639, H8S/2630, H8S/2635, and H8S/2634 are shown in table 1-1. Notes: The H8S/2635 and H8S/2634 are not equipped with a DTC, a PPG, or a D/A converter. * F-ZTAT is a trademark of Renesas Technology Corp. Table 1-1 Overview 2 Item in table 1-1 amended PC break controller (This function is not implemented in the H8S/2635 Group) Data transfer controller (DTC) (This function is not implemented in the H8S/2635 Group) 3 Programmable pulse generator (PPG) (This function is not implemented in the H8S/2635 Group) Controller area network (HCAN) 2 channels (The H8S/2635 Group has one HCAN channels) D/A converter (This function is not implemented in the H8S/2635 Group) 4 Memory Product Name H8S/2630* H8S/2635 H8S/2634 ROM 384 kbytes 192 kbytes 128 kbytes RAM 16 kbytes 6 kbytes Rev. 6.00 Feb 22, 2005 page v of lx Item 1.1 Overview Table 1-1 Overview Page 4 Revision (See Manual for Details) Item in table 1-1 amended Interrupt controller * 49 interrupt sources (45 sources in H8S/2635) 5 Clock pulse generator * Input clock frequency H8S/2636, H8S/2638, H8S/2630: 4 to 20 MHz H8S/2639, H8S/2635, H8S/2634: 4 to 5 MHz Product lineup Model Name Mask ROM Version HD6432630F HD6432630UF (U-Mask Version) HD6432630WF (W-Mask Version) HD6432635F HD6432634F F-ZTAT Version HD64F2630F HD64F2630UF (U-Mask Version) HD64F2630WF (W-Mask Version) HD64F2635F -- Subclock Functions No Yes Yes Yes Yes I C bus interface No No Yes No No 192 k/ 6k 128 k/ 6k 2 ROM/ RAM (Bytes) Packages 384 k/ 16 k Note * amended Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available only in the U-mask and W-mask versions, and H8S/2635 Group, but are not in the other versions. 1.2 Internal Block Diagram Figure 1-1 (c) Internal Block Diagram of H8S/2635 Group 1.3.1 Pin Arrangement 9 Figure 1-2 Pin Arrangement of H8S/2636 Group (FP-128B: Top View) Figure 1-3 Pin Arrangement of H8S/2638 Group and H8S/2630 Group (FP-128B: Top View) 10 Note added Notes: PPG and D/A converter pin functions not implemented. 1. Connect a 0.1 F capacitor between VCL and VSS (close to the pins). ... Notes: The PPG and D/A converter pin functions not implemented. 1. Connect a 0.1 F capacitor between VCL and VSS (close to the pins). ... 8 Figure added Rev. 6.00 Feb 22, 2005 page vi of lx Item Page Revision (See Manual for Details) Figure 1-5 added 1.3.1 Pin Arrangement 12 Figure 1-5 Pin Arrangement of H8S/2635 Group (FP-128B: Top View) 1.3.2 Pin Functions in 14 Each Operating Mode Table 1-2 Pin Functions in Each Operating Mode Table amended, note *4 added Pin No. FP-128B 27 28 29 30 31 32 33 34 42 Mode 4 PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 LWR/ADTRG/ IRQ3 Mode 5 PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 PF3/LWR/ADTRG/ IRQ3 Pin Name Mode 6 PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 PF3/LWR/ADTRG/ IRQ3 Mode 7 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF3/ADTRG/ IRQ3 16 Pin No. FP-128B 89 90 91 92 93 94 95 96 109 110 Mode 4 Mode 5 Pin Name Mode 6 Mode 7 4 4 4 4 P10/PO8* /TIOCA0/A20 P10/PO8* /TIOCA0/A20 P10/PO8* /TIOCA0/A20 P10/PO8* /TIOCA0 4 4 4 4 P11/PO9* /TIOCB0/A21 P11/PO9* /TIOCB0/A21 P11/PO9* /TIOCB0/A21 P11/PO9* /TIOCB0 P12/PO10* /TIOCC0/ TCLKA/A22 4 4 P12/PO10* /TIOCC0/ TCLKA/A22 4 P13/PO11* /TIOCD0/ TCLKB/A23 4 P12/PO10* /TIOCC0/ TCLKA/A22 4 P13/PO11* /TIOCD0/ TCLKB/A23 P12/PO10* /TIOCC0/ TCLKA 4 P13/PO11* /TIOCD0/ TCLKB/A23 4 P13/PO11* /TIOCD0/ TCLKB 4 P14/PO12* /TIOCA1/ IRQ0 4 P14/PO12* /TIOCA1/ IRQ0 4 4 P15/PO13* /TIOCB1/ TCLKC 4 P16/PO14* /TIOCA2/ IRQ1 4 P17/PO15* /TIOCB2/ TCLKD 4 P46/AN6/DA0* 4 P47/AN7/DA1* P14/PO12* /TIOCA1/ IRQ0 4 4 P15/PO13* /TIOCB1/ TCLKC P14/PO12* /TIOCA1/ IRQ0 4 P15/PO13* /TIOCB1/ TCLKC 4 4 P16/PO14* /TIOCA2/ IRQ1 P15/PO13* /TIOCB1/ TCLKC 4 P16/PO14* /TIOCA2/ IRQ1 4 4 P17/PO15* /TIOCB2/ TCLKD 4 P46/AN6/DA0* 4 P47/AN7/DA1* P16/PO14* /TIOCA2/ IRQ1 4 P17/PO15* /TIOCB2/ TCLKD 4 4 P46/AN6/DA0* 4 P47/AN7/DA1* P17/PO15* /TIOCB2/ TCLKD 4 4 P46/AN6/DA0* 4 P47/AN7/DA1* 17 Notes amended Notes: 1. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group. ... The H8S/2639 and H8S/2635 Groups have no OSC1 and OSC2 pins. 4. The PPG output, DA0, and DA1 are not supported in H8S/2635 Group. Rev. 6.00 Feb 22, 2005 page vii of lx Item 1.3.3 Pin Functions Table 1-3 Pin Functions Page 18 Revision (See Manual for Details) Name and function amended XTAL Crystal: Connects to a crystal oscillator. ... EXTAL External clock: Connects to a crystal oscillator. ... 21 AVCC Analog power supply: A/D converter and D/A converter power supply pin. ... AVSS Analog ground: Ground pin for A/D converter and D/A converter. ... Vref Analog reference power supply: A/D converter and D/A converter reference voltage input pin. ... 18, 20, 21 22 Table 1-3 amended HTxD1*3 HRxD1*3 PO15 to PO8*4 DA1, DA0*5 Notes amended Notes: 1. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group. ... The H8S/2639 and H8S/2635 Groups have no OSC1 and OSC2 pins. 3. The HTxD1 and HRxD1 pins are not supported in the H8S/2635 Group. 4. The PO15 to 8 output are not supported in the H8S/2635 Group. 5. The DA1 and DA0 output are not supported in the H8S/2635 Group. 1.4 Differences between H8S/2636, H8S/2638, H8S/2639, H8S/2630, H8S/2635, and H8S/2634 23 1.4 title amended Rev. 6.00 Feb 22, 2005 page viii of lx Item 1.4 Differences between H8S/2636, H8S/2638, H8S/2639, H8S/2630, H8S/2635, and H8S/2634 Table 1-4 Comparison of Product Specifications Page 23 Revision (See Manual for Details) Table 1-4 amended Product Specifications Product Type Model ROM RAM Subclock I2C Bus Function Interface No No DTC, PBC, Power-Down PPG, Modes DAC See section 23A, PowerDown Modes See section 23B, PowerDown Modes No See section 23A, PowerDown Modes See section 23B, PowerDown Modes No See section 23A, PowerDown Modes See section 23B, PowerDown Modes See section 23A, PowerDown Modes See section 23B, PowerDown Modes HCAN H8S/2636 HD64F2636F HD64F2636UF 128-kbyte on-chip flash memory 4-kbyte SRAM Yes 2 channels Yes HD6432636F 128-kbyte mask ROM No HD6432636UF Yes H8S/2638 HD64F2638F 256-kbyte on-chip flash HD64F2638UF memory HD64F2638WF HD6432638F 256-kbyte mask ROM 16-kbyte No SRAM Yes Yes No No HD6432638UF HD6432638WF Yes Yes 24 Product Type Model ROM RAM Product Specifications Subclock I2C Bus Function Interface No Yes DTC, PBC, Power-Down PPG, Modes DAC See section 23B, PowerDown Modes HCAN H8S/2639*1 HD64F2639UF 256-kbyte HD64F2639WF on-chip flash memory HD6432639UF 256-kbyte HD6432639WF mask ROM H8S/2630 HD64F2630F 384-kbyte on-chip flash HD64F2630UF memory HD64F2630WF HD6432630F 384-kbyte mask ROM 16-kbyte Yes SRAM 2 Yes channels No Yes 16-kbyte No SRAM Yes Yes No No No See section 23A, PowerDown Modes See section 23B, PowerDown Modes See section 23A, PowerDown Modes See section 23B, PowerDown Modes 1 channel No HD6432630UF HD6432630WF H8S/2635*1 HD64F2635F 192-kbyte on-chip flash memory 6-kbyte SRAM Yes Yes Yes No HD6432635F*2 192-kbyte mask ROM H8S/2634*1 HD6432634F*2 128-kbyte mask ROM Rev. 6.00 Feb 22, 2005 page ix of lx Item 3.3.1 Mode 4 Page 85 Revision (See Manual for Details) Description amended Ports 1, A, B, and C function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. 3.3.2 Mode 5 85 Description amended Ports 1, A, B, and C function as an address bus, port D function as a data bus, and part of port F carries bus control signals. 3.3.3 Mode 6 85 Description amended Ports 1, A, B, and C function as input port pins immediately after a reset. Address output can be performed by setting the corresponding DDR (data direction register) bits to 1. 3.5 Address Map in Each Operating Mode Figure 3-4 Memory Map in Each Operating Mode in the H8S/2635 91 Figure 3-4 added Figure 3-5 Memory 92 Map in Each Operating Mode in the H8S/2634 4.1.1 Exception Handling Types and Priority Table 4-1 Exception Types and Priority 93 Figure 3-5 added Note * amended Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. ... 93 Note 4 amended Note: 4. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. ... Note 3 amended Note: 3. ... Subclock functions are available in the U-mask and W-mask versions, and H8S/2635 Group only. Note added Note: The DTC, PBC, and IIC are not implemented in the H8S/2635 Group. 4.1.3 Exception Vector 95 Table Table 4-2 Exception Vector Table 4.4 Interrupts 100 Figure 4-4 Interrupts 100 Sources and Number of Interrupts Note *3 added 3 HCAN (4)* Note: 3. 2 Sources in the H8S/2635 Group. Rev. 6.00 Feb 22, 2005 page x of lx Item 5.1.1 Features Page 105 Revision (See Manual for Details) Note * added * DTC control* ... Note: * The H8S/2635 Group is not equipped with a DTC. 5.2 Register Descriptions 108 Note added Note: The H8S/2635 Group is not equipped with a DTC, a PC brake controller, or an HCAN1. Note *3 added 3 DTC* PC break*3 HCAN channel 1*3 Note: 3. The PC break, DTC, and HCAN channel 1 are reserved in the H8S/2635 Group. 5.2.2 Interrupt Priority 109 Registers A to H, J to M (IPRA to IPRH, IPRJ to IPRM) Table 5-3 Correspondence between Interrupt Sources and IPR Setting 5.3 Interrupt Sources 114 Notes added Notes: The H8S/2635 Group is not equipped with a DTC, a PC break controller, or an HCAN1. The H8S/2635 has 45 sources of internal interrupt. 5.3.3 Interrupt Exception Handling Vector Table Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities 117 Note *3 added DTC*3 PC break controller*3 HCAN*3 Note: 3. The DTC, PC break, and HCAN1 interrupts are reserved in the H8S/2635 Group. Note added Note: The DTC is not implemented in the H8S/2635 Group. Note added Note: The H8S/2635 Group is not equipped with a PBC. Note added Note: The DTC is not implemented in the H8S/2635 Group. Note added Note: The H8S/2635 Group is not equipped with a DTC. Note added Note: The H8S/2635 Group is not equipped with a DTC. 120 5.6 DTC Activation by 133 Interrupt Section 6 PC Break Controller (PBC) 7.1 Overview 7.8 Bus Arbitration Section 8 Data Transfer Controller (DTC) 137 149 187 189 Rev. 6.00 Feb 22, 2005 page xi of lx Item Table 9-1 Port Functions Page 224 Revision (See Manual for Details) Notes *2, *3 added Port Description Pins 1 Mode 4 Mode 5 Mode 6 Mode 7 Port 3 * 6-bit I/O port P35/SCK1/SCL0* / IRQ5 1 * Open-drain P34/RxD1/SDA0* 1 output P33/TxD1/SCL1* capability 1 P32/SCK0/SDA1* / * SchmittIRQ4 triggered P31/RxD0 input (P35, P30/TxD0 P32) 6-bit I/O port also functioning as SCI (channel 0, 1) I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1), interrupt input pins ( IRQ4, IRQ5), IIC (channel 0, 1) I/O pins (SCL0, SDA0, SCL1, 1 SDA1)* Port (Before) Port 1 (After) Port 1 * (Before) Port 4 (After) Port 4 *3 2 226 Note added 2 Notes: 1. I C bus interface ... and H8S/2630. 2. The PPG output is not implemented in the H8S/2635 Group. 3. The DA output is not implemented in the H8S/2635 Group. 9.2 Port 1 227 Note added Note: The PPG output is not implemented in the H8S/2635 Group. 9.2.3 Pin Functions 229 Note added Note: The PPG output is not implemented in the H8S/2635 Group. 9.4 Port 4 248 Note added Note: The DA output is not implemented in the H8S/2635 Group. Section 10 16-Bit 295 Timer Pulse Unit (TPU) 10.5.2 DTC Activation 369 Note added Note: The H8S/2635 Group is not equipped with a DTC or PPG. Note added Note: The DTC is not implemented in the H8S/2635 and H8S/2634. 10.6.2 Interrupt Signal 377 Timing Status Flag Clearing Timing Note * added DTC* Note: * The DTC is not implemented in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page xii of lx Item 10.7 Usage Notes Figure 10-56 Contention between Overflow and Counter Clearing Page 386 Revision (See Manual for Details) Figure 10-56 amended TCNT input clock TCNT Counter clear signal TGF Prohibited TCFV H'FFFF H'0000 Figure 10-57 Contention between TCNT Write and Overflow 387 Figure 10-57 amended Prohibited TCFV flag 387 Interrupts and Module Stop Mode Note * added DTC* Note: *The DTC is not implemented in the H8S/2635 and H8S/2634. Section 11 Programmable Pulse Generator (PPG) 12.1.1 Features 389 Note added Note: The H8S/2635 Group is not equipped with a PPG. 415 Notes amended Notes: 1. Other than the U-mask and W-mask versions, and H8S/2635 Group have eight types of counter input clock as well as WDT0. 2. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. ... The H8S/2639, H8S/2635 Groups have no OSC1 and OSC2 pins. 12.1.2 Block Diagram 416 Figure 12-1 (a) Block Diagram of WDT0 Note 2 amended Note: 2. In the U-mask and W-mask versions, and H8S/2635 Group, in subactive and subsleep modes operates as SUB. Rev. 6.00 Feb 22, 2005 page xiii of lx Item Page Revision (See Manual for Details) Note 2 amended Note: 2. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. TSCR1 Note 2 amended Note: 2. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. Bits 2 to 0Clock Select 2 to 0 (CKS2 to CKS0) Note * amended Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. ... 12.1.2 Block Diagram 417 Figure 12-1 (b) Block Diagram of WDT1 12.2.2 Timer 420 Control/Status Register (TCSR) 423 424 WDT0 Input Clock Select Note 2 amended Note: 2. In the U-mask and W-mask versions, and H8S/2635 Group, in subactive and subsleep modes operates as SUB. 425 WDT1 Input Clock Select Note 2 amended Note: 2. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. ... 12.3.1 Watchdog Timer Operation 12.5.2 Changing Value of PSS* and CKS2 to CKS0 Section 13 Serial Communication Interface (SCI) 13.2.2 Receive Data Register (RDR) 429 434 Note * amended Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. ... Note added Note: The H8S/2635 Group is not equipped with a DTC. 435 440 Note * amended Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. ... Rev. 6.00 Feb 22, 2005 page xiv of lx Item 13.2.4 Transmit Data Register (TDR) Page 441 Revision (See Manual for Details) Note * amended Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. ... 13.2.7 Serial Status Register (SSR) 449 Note * amended Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. ... 13.5 Usage Notes 497 Note * added Restrictions on Use of DTC* Note: * The DTC is not implemented in the H8S/2635 and H8S/2634. Operation in Case of Mode Transition * Transmission ... Operation should also be stopped ... before making a transition from transmission by DTC* transfer to module stop mode, ... . To perform transmission with the DTC* after the relevant mode is cleared, ... and start DTC* transmission. Note: * The DTC is not implemented in the H8S/2635 and H8S/2634. Section 14 Smart Card 503 Interface 14.1.1 Features 503 Note added Note: The H8S/2635 Group is not equipped with a DTC. * Three interrupt sources Note * added The transmit data empty interrupt and receive data full interrupt can activate the data transfer controller (DTC)* to execute data transfer Note: * The DTC is not implemented in the H8S/2635 and H8S/2634. 14.3.6 Data Transfer Operations 523 Serial Data Transmission (Except Block Transfer Mode) Note * added ... If the DTC* is activated by a TXI request, the number of bytes set in the DTC can be transmitted automatically, including automatic retransmission. ... Note: * The DTC is not implemented in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page xv of lx Item 14.3.6 Data Transfer Operations Page 527 Revision (See Manual for Details) Serial Data Reception (Except Block Transfer Mode) Note * added DTC* Note: * The DTC is not implemented in the H8S/2635 and H8S/2634. 528, 529 Data Transfer Operation by DTC* Note * added Note: * The DTC is not implemented in the H8S/2635 and H8S/2634. 14.4 Usage Notes 533 Retransfer operations (Except Block Transfer Mode) * Retransfer operation when SCI is in receive mode Note * added [4] ... If DTC* data transfer by an RXI source is enabled, ... When the RDR data is read by the DTC*, the RDRF flag is automatically cleared to 0. Note: * The DTC is not implemented in the H8S/2635 and H8S/2634. 534 * Retransfer operation when SCI is in transmit mode Note * added [9] ... If data transfer by the DTC* by means of the TXI source is enabled, ... When data is written to TDR by the DTC*, the TDRE bit is automatically cleared to 0. Note: * The DTC is not implemented in the H8S/2635 and H8S/2634. 15.4 Usage Notes 599, 600 * Notes on Arbitration Lost in Master Mode Description added * Notes on loss of arbitration Description deleted Note added Notes: The H8S/2635 Group is not equipped with a DTC. Only a single HCAN channel, HCAN0, is implemented in the H8S/2635 Group. Section 16 Controller Area Network (HCAN) 601 Rev. 6.00 Feb 22, 2005 page xvi of lx Item 16.1.3 Pin Configuration Table 16-1 HCAN Pins 16.1.4 Register Configuration Table 16-2 HCAN Registers Page 604 Revision (See Manual for Details) Note * added Channel 1* Notes: * The HCAN1 is not supported by the H8S/2635 and H8S/2634. 605 to 608 Note *2 added 1 Address* Channel 1*2 Notes: 1. Lower 16 bits of the address. 2. The HCAN1 is not supported by the H8S/2635 and H8S/2634. 16.2.20 Module Stop Control Register C (MSTPCRC) 640 Note * added MSTPC2* Note: * The MSTPC2 is not available and is reserved in the H8S/2635 and H8S/2634. 640 Bit 2Module Stop (MSTPC2)* Note: * The MSTPC2 is not available and is reserved in the H8S/2635 and H8S/2634. 16.3.8 DTC Interface* 665 Note * added Note: * The DTC is not implemented in the H8S/2635 and H8S/2634. Section 17 A/D Converter Section 18 D/A Converter 671 695 Note added Note: The H8S/2635 Group is not equipped with a DTC. Note added Note: The H8S/2635 Group is not equipped with a D/A converter. Rev. 6.00 Feb 22, 2005 page xvii of lx Item Section 19 Motor Control PWM Timer Page 703 Revision (See Manual for Details) Note added Note: The H8S/2635 Group is not equipped with a DTC. Note * amended Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. ... 19.2.2 PWM Output 710 Control Registers 1 and 2 (PWOCR1, PWOCR2) 19.2.3 PWM Polarity Registers 1 and 2 (PWPR1, PWPR2) 711 19.2.4 PWM Counters 712 1 and 2 (PWCNT1, PWCNT2) 19.2.5 PWM Cycle Registers 1 and 2 (PWCYR1, PWCYR2) 19.2.6 PWM Duty Registers 1A, 1C, 1E, 1G (PWDTR1A, 1C, 1E, 1G) 713 714 19.2.7 PWM Buffer 716 Registers 1A, 1C, 1E, 1G (PWBFR1A, 1C, 1E, 1G) 19.2.8 PWM Duty Registers 2A to 2H (PWDTR2A to PWDTR2H) 19.2.9 PWM Buffer Registers 2A to 2D (PWBFR2A to PWBFR2D) 19.5 Usage Note 717 719 725 Note * added Buffer register rewriting must be completed before automatic transfer by the DTC* (data transfer controller), ... Note: * The DTC is not implemented in the H8S/2635 and H8S/2634. Section 20 RAM 727 Note added Note: The H8S/2635 Group is not equipped with a DTC. Rev. 6.00 Feb 22, 2005 page xviii of lx Item 20.1 Overview Page 727 Revision (See Manual for Details) Description amended The H8S/2636 has 4 kbytes, and H8S/2638, H8S/2639, and H8S/2630 have 16 kbytes of on-chip high-speed static RAM. The H8S/2635 Group has 6 kbytes of on-chip RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. This makes it possible to perform fast word data transfer. 20.1.1 Block Diagram 729 Figure 20-1 (c) Block Diagram of RAM (H8S/2635 Group) 20.3 Operation 730 Figure 20-1 (c) added Description amended When the RAME bit is set to 1, accesses to addresses H'FFE000 to H'FFEFBF (for the H8S/2636), H'FFB000 to H'FFEFBF (for the H8S/2638, H8S/2639, and H8S/2630), H'FFD800 to H'FFEFBF (for the H8S/2635 Group), or H'FFFFC0 to H'FFFFFF in the chip are directed to the on-chip RAM. ... 20.4 Usage Notes 731 Reserved Areas Description amended Addresses H'FFB000 to H'FFDFFF in the H8S/2636 and H'FFB000 to H'FFD7FF in the H8S/2635 Group are reserved areas that cannot be read or written to. ... 21A.8.1 Boot Mode Figure 21A-9 RAM Area in Boot Mode 758 Figure amended H'FFE000 Boot program area (2 kbytes) H'FFE7FF H'FFE800 Programming control program area (1.9 kbytes) H'FFEFBF 759 Note on Use of Boot Mode Description amended * Before branching to the programming control program (RAM area H'FFE800), the chip terminates ... Rev. 6.00 Feb 22, 2005 page xix of lx Item Page Revision (See Manual for Details) Table 21A-27 amended Register Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 Abbreviation FLMCR1 FLMCR2 EBR1 EBR2 Address H'FFA8 H'FFA9 H'FFAA H'FFAB 21A.16 Note on 796 Switching from F-ZTAT Version to Mask ROM Version Table 21A-27 Registers Present in FZTAT Version but Absent in Mask ROM Version 21B.1 Overview 797 Description amended The H8S/2638 and H8S/2639 have 256 kbytes of on-chip flash memory, or 256 kbytes or 384 kbytes of on-chip mask ROM. 21B.16 Note on 862 Switching from F-ZTAT Version to Mask ROM Version Table 21B-27 Registers Present in FZTAT Version but Absent in Mask ROM Version Section 21C ROM (H8S/2635 Group) Section 22B Clock Pulse Generator (H8S/2639 Group, H8S/2635 Group) 22B.3.2 External Clock Input Figure 22B-6 External Clock Input (Examples) 863 to 928 941 Table 21B-27 amended Register Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 Abbreviation FLMCR1 FLMCR2 EBR1 EBR2 Address H'FFA8 H'FFA9 H'FFAA H'FFAB Section 21C added Section 22B title amended 947 Note * added (b) Complementary clock input at XTAL pin* Note: * In the case of the H8S/2635 Group, do not input a complementary clock to the XTAL pin. Rev. 6.00 Feb 22, 2005 page xx of lx Item Section 23A PowerDown Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] Section 23B PowerDown Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF, HD6432635F, HD64F2635F, HD6432634F] Page 951 Revision (See Manual for Details) Section 23A title amended 973 Note added Note: The DTC, PBC, PPB, and D/A converter are not implemented in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page xxi of lx Item 23B.1 Overview Page 973 Revision (See Manual for Details) Description amended ... The chip operating modes are as follows: (3) Subactive mode* (U-mask, W-mask version, H8S/2635 Group only) ... (5) Subsleep mode* (U-mask, W-mask version, H8S/2635 Group only) ... (6) Watch mode* (U-mask, W-mask version, H8S/2635 Group only) ... 974 Note * amended Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. ... Table 23B-2 LSI Internal States in Each Mode (H8S/2639 Group, H8S/2635 Group) 23.2.3 Low-Power Control Register (LPWRCR) 976 Note *3 added DTC*3 PBC*3 PPG*3 D/A0, 1*3 Note: 3. The DTC, PBC, PPB, DA0, and DA1 are not implemented in the H8S/2635 and H8S/2634. 983 Note * amended Note: * Bits 7 to 3 in LPWRCR are valid in the U-mask and Wmask versions, and H8S/2635 Group; they are reserved bits in all other versions. ... Note * amended Note: 2. Bit 4 (PSS) in TCSR of WDT1 is valid in the U-mask and W-mask versions, and H8S/2635 Group. In versions other than the U-mask and W-mask versions, and H8S/2635 Group, however, the PSS bit ... Bit 4Prescaler Select (PSS) Note 2 amended Note: 2. Bit 4 (PSS) in TCSR of WDT1 is valid in the U-mask and W-mask versions, and H8S/2635 Group. In versions other than the U-mask and W-mask versions, and H8S/2635 Group, however, the PSS bit ... 23.2.4 Timer 985 Control/Status Register (TCSR) 986 Rev. 6.00 Feb 22, 2005 page xxii of lx Item 23B.5.1 Module Stop Mode Table 23B-5 MSTP Bits and Corresponding On-Chip Supporting Modules Page 991 Revision (See Manual for Details) Note *3 added Register MSTPCRA Bit MSTPA6 MSTPA5 MSTPA3 MSTPA2 MSTPCRC MSTPC4 MSTPC3 MSTPC2 Module 3 Data transfer controller (DTC)* 16-bit timer pulse unit (TPU) Programmable pulse generator (PPG)* D/A converter (channel 0, 1)* 3 PC break controller (PBC)* HCAN0 3 HCAN1* 3 3 Note: 3. The DTC, PPG, D/A converter, PBC, and HCAN1 are not implemented in the H8S/2635 and H8S/2634. MSTPA6, MSTPA3, MSTPA2, MSTPC4, and MSTPC2 are readable/writable bits, but only 1 should be written to them. 23B.5.2 Usage Notes 992 Note added Note: The DTC is not implemented in the H8S/2635 Group. 23B.6.3 Setting 993 Oscillation Stabilization Time after Clearing Software Standby Mode Using a Crystal Oscillator Description added 1. Setting for H8S/2636, H8S/2638, H8S/2639, H8S/2630 Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time). Table 23B-6 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 23B-6 994 Oscillation Stabilization Time Settings Table 23B-6 Oscillation Stabilization Time Settings STS2 0 STS1 0 STS0 0 1 1 0 1 1 0 0 1 1 0 1 Standby Time 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved 16 states (Setting prohibited) 20 MHz 0.41 0.82 1.6 3.3 6.6 16 MHz 0.51 1.0 2.0 4.1 8.2 12 MHz 0.68 1.3 2.7 5.5 10.9 21.8 -- 1.3 10 MHz 0.8 1.6 3.3 6.6 8 MHz 1.0 2.0 4.1 8.2 6 MHz 1.3 2.7 5.5 10.9 21.8 43.6 -- 2.6 5 MHz 1.6 3.2 6.5 4 MHz 2.0 4.1 8.2 Unit ms 13.1 16.4 26.2 52.4 -- 3.2 32.8 65.6 -- 4.0 s 13.1 16.4 26.2 -- 1.6 32.8 -- 2.0 13.1 16.4 -- 0.8 -- 1.0 : Recommended time setting Rev. 6.00 Feb 22, 2005 page xxiii of lx Item Page Revision (See Manual for Details) 2. Setting for H8S/2635, H8S/2634 Set bits STS2 to STS0 so that the standby time is at least 12 ms (the oscillation stabilization time). Table 23B-7 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 23B-7 Oscillation Stabilization Time Settings STS2 0 STS1 0 STS0 0 1 1 0 1 1 0 0 1 1 0 1 Standby Time 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved 16 states (Setting prohibited) 20 MHz 16 MHz 10 MHz 8 MHz 0.41 0.82 1.6 3.3 6.6 13.1 -- 0.8 0.51 1.0 2.0 4.1 8.2 16.4 -- 1.0 0.8 1.6 3.3 6.6 13.1 26.2 -- 1.6 1.0 2.0 4.1 8.2 16.4 32.8 -- 2.0 5 MHz 1.6 3.2 6.5 13.1 26.2 52.4 -- 3.2 4 MHz 2.0 4.1 8.2 16.4 32.8 65.6 -- 4.0 s Unit ms 23B.6.3 Setting 994 Oscillation Stabilization Time after Clearing Software Standby Mode Table 23B-7 Oscillation Stabilization Time Settings : Recommended time setting 23B.8 Watch Mode (U-mask, W-mask Version, H8S/2635 Group Only) 997 23B.8 title amended 23B.9 Subsleep Mode 999 (U-mask, W-mask Version, H8S/2635 Group Only) 23B.10 Subactive 1000 Mode (U-mask, Wmask Version, H8S/2635 Group Only) 23B.11 Direct 1001 Transitions (U-mask, W-mask Version, H8S/2635 Group Only) 23B.12 Clock Output 1002 Disabling Function Table 23B-8 Pin State in Each Processing State 23B.9 title amended 23B.10 title amended 23B.11 title amended Note * amended Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. ... Rev. 6.00 Feb 22, 2005 page xxiv of lx Item 23B.13 Usage Notes Page 1003 Revision (See Manual for Details) Description amended 5. (H8S/2639 Group, H8S/2635 Group only) The subclock (SUB) is ... (Before) f SUB (After) t SUB Table 24-4 Clock Timing 24.2.4 AC Characteristics Table 24-15 Clock Timing 24.3 H8S/2639 Group, 1038 H8S/2635 Group Electrical Characteristics 24.3.3 DC Characteristics Table 24-24 DC Characteristics 1040 Note * added 1029 Symbol of subclock (SUB) cycle time amended (Before) f SUB (After) t SUB Input voltage (XTAL*, EXTAL) Note: * In the case of the H8S/2635 Group, do not input a signal to the XTAL pin. Table 24-24 amended, notes *7, *8 added HRxD1*7 HTxD1*7 During A/D and D/A*7 conversion Item Output high voltage PWM1A to PWM1H, PWM2A to PWM2H Ports 1, 3, A to F, H, J HTxD0, HTxD1*7 ITSI Symbol Min. Typ. Max. -- Unit Test Conditions IOH = -15 mA PWMVCC - -- 0.5 Three-state leakage current (off state) 0000 0000 24.1.4 AC Characteristics 1012 Symbol of subclock (SUB) cycle time amended -- -- 1.0 A Vin =0.5 V to VCC - 0.5 V Rev. 6.00 Feb 22, 2005 page xxv of lx Item 24.3.3 DC Characteristics Table 24-24 DC Characteristics Page 1042 Revision (See Manual for Details) Table 24-24 amended, notes *7, *8 added Item Ports A to E MOS input pull-up current Current 2 dissipation* (H8S/2639 Group) Normal operation Sleep mode All modules stopped Mediumspeed mode (/32) Subactive mode Subsleep mode Watch mode Standby mode*3 Current 2 dissipation* (H8S/2635 Group) Normal operation Sleep mode All modules stopped Mediumspeed mode (/32) Subactive mode Subsleep mode Watch mode Standby mode ICC* 8 Symbol -IP 4 ICC* Min. 50 -- -- -- -- Typ. -- 75 65 57 49 Max. 300 90 80 -- -- Unit A mA Test Conditions Vin = 0 V f = 20 MHz mA f = 20 MHz (reference value) -- -- -- -- -- -- -- -- -- 0.7 0.7 0.6 2.0 -- 60 50 40 45 1.0 1.0 1.0 5.0 20 65 55 -- -- mA Subclock (using 4.19 MHz crystal oscillator) A mA Ta 50C 50C < Ta f = 20 MHz mA f = 20 MHz (reference value) -- -- -- -- -- 0.35 0.3 0.25 2.0 -- 0.4 0.35 0.3 5.0 20 mA Subclock (using 5.0 MHz crystal oscillator) A Ta 50C 50C < Ta 1043 Notes 7, 8 added Note: 7. The HDxD1, HRxD1 pins, and D/A converter are not available in the H8S/2635 Group. 8. ICC depends on VCC and f as follows: ICC (max.) = 17 (mA) + 0.43 (mA/(MHz x V)) x VCC x f (normal operation) ICC (max.) = 17 (mA) + 0.34 (mA/(MHz x V)) x VCC x f (sleep mode) Rev. 6.00 Feb 22, 2005 page xxvi of lx Item 24.3.4 AC Characteristics Table 24-27 Clock Timing Page 1047 Revision (See Manual for Details) Table 24-27 amended Condition 20MHz Item Clock oscillator settling time in software standby (crystal) (H8S/2639 Group) Clock oscillator settling time in software standby (crystal) (H8S/2635 Group) External clock output stabilization delay time Subclock oscillator frequency Subclock (SUB) cycle time tDEXT fSUB tSUB Symbol tOSC2 Min. 8 Max. -- Unit ms Test Conditions Figure 23A-3 Figure 23B-3 12 -- 2 31.25 25.6 -- 39.6 32.0 ms kHz s Figure 24-10 Table 24-30 Timing of 1050, On-Chip Supporting 1051 Modules Note *1 added PPG*1 HCAN*2 Notes: 1. The PPG output is not available in the H8S/2635 Group. 2. The HCAN input signal is asynchronous. ... 24.3.6 D/A Conversion 1053 Characteristics* 24.4 H8S/2630 Group 1056 to Electrical 1073 Characteristics 24.4.3 DC Characteristics Table 24-36 DC Characteristics 1059 Note * added Note: * The D/A conversion is not implemented in the H8S/2635 and H8S/2634. "Preliminary" deleted Table 24-36 amended Item Output high voltage PWM1A to PWM1H, PWM2A to PWM2H Ports 1, 3, A to F, H, J HTxD0, HTxD1 Symbol VOH Min. Typ. Max. -- Unit V Test Conditions IOH = -15 mA PWMVCC - -- 0.5 Three-state leakage current (off state) ITSI -- -- 1.0 A Vin = 0.5 V to VCC - 0.5 V 1060 Item Ports A to E MOS input pull-up current Symbol -IP Min. 50 Typ. -- Max. 300 Unit A Test Conditions Vin = 0 V (Before) f SUB (After) t SUB Table 24-39 Clock Timing Rev. 6.00 Feb 22, 2005 page xxvii of lx 0000 24.4.4 AC Characteristics 1065 Symbol of subclock (SUB) cycle time amended Item 24.5.4 On-Chip Supporting Module Timing Figure 24-20 PPG Output Timing* A.1 Instruction List Table A-1 Instruction Set Page 1081 Revision (See Manual for Details) Note * added Note: * The PPG output is not implemented in the H8S/2635 and H8S/2634. 1089 1108 Note *4 added LDM*4 STM*4 Note: 4. Only register ER0 to ER6 should be used when using the STM/ LDM instruction. Note *3 added 3 3 LDM* STM* Note: 3. Only register ER0 to ER6 should be used when using the STM/ LDM instruction. Note *9 added LDM.L (ERn-ERn+1)*9 LDM.L (ERn-ERn+2)*9 LDM.L (ERnERn+3)*9 @SP*9 Note: 9. Only register ER0 to ER6 should be used when using the STM/ LDM instruction. Note *7 added DTC*7 HCAN1*7 PBC*7 PPG*7 IIC0*4 IIC1*4 Address H'FEC0 H'FEC1 H'FEC2 H'FEC3 H'FEC4 Register Name IPRA IPRB IPRC IPRD IPRE Bit 7 -- -- -- -- -- Bit 6 IPR6 IPR6 -- IPR6 IPR6* 7 A.2 Instruction Codes 1117, Table A-2 Instruction 1122 Codes 1123 A.5 Bus States during 1149, Instruction Execution 1154 Table A-6 Instruction Execution Cycles 1155 1162, 1169 to 1180, 1182, 1183 B.1 Address Bit 5 IPR5 IPR5 -- IPR5 IPR5* 7 Bit 4 IPR4 IPR4 -- IPR4 IPR4* 7 Bit 3 -- -- -- -- -- Bit 2 IPR2 IPR2 IPR2* -- IPR2 7 Bit 1 IPR1 IPR1 IPR1* -- IPR1 7 Bit 0 IPR0 IPR0 IPR0* -- IPR0 7 Module Name INT Data Bus Width 8 Address H'FFA8 H'FFA9 H'FFAA H'FFAB H'FFAC Register Name FLMCR1 FLMCR2 EBR1 EBR2 FLPWCR Bit 7 FWE FLER EB7 -- PDWND* 2 Bit 6 SWE -- EB6 -- -- Bit 5 ESU -- EB5 EB13* -- 8 Bit 4 PSU -- EB4 EB12* -- 8 Bit 3 EV -- EB3 EB11* -- 6 Bit 2 PV -- EB2 EB10* -- 5 Bit 1 E -- EB1 EB9 -- Bit 0 P -- EB0 EB8 -- Module Name FLASH Data Bus Width 8 Rev. 6.00 Feb 22, 2005 page xxviii of lx Item B.1 Address Page 1183 Revision (See Manual for Details) Notes amended Notes: 1. Bit 4 (PSS) in TCSR of WDT1 is valid in the U-mask and W-mask versions, and H8S/2635 Group. In versions other than the U-mask and W-mask versions, and H8S/2635 Group, however, the PSS bit ... 2. Subclock functions (subactive mode, subsleep mode, and watch mode) are not available in versions other than the Umask and W-mask versions, and H8S/2635 Group. Subclock functions may be used with the U-mask and W-mask versions, and H8S/2635 Group. 3. Bits DTON, LSON, NESEL, and SUBSTP in LPWRCR are valid in the U-mask and W-mask versions, and H8S/2635 Group. In versions other than the U-mask and W-mask versions, and H8S/2635 Group, however, ... 5. This bit is reserved in the H8S/2636. 6. This bit is reserved in the H8S/2636 and H8S/2635. 7. These bits are not available in the H8S/2635 and H8S/2634. 8. These bits are reserved in the H8S/2636, H8S/2638, H8S/2639, and H8S/2635. These bits are valid in the H8S/2630 only. MRA H'EBC0 DTC* to LAFMH1 H'FA1E HCAN1* Note * added DTC * HCAN1* Note: * This register is not available in the H8S/2635 and H8S/2634. UMSR0 H'F81A HCAN0, UMSR1 H'FA1A HCAN1*1 Note *2 added Bit Initial value Read/Write Bit Initial value Read/Write 15 UMSR7 0 R/(W)*2 7 14 13 12 11 10 9 8 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 B.2 Functions 1185 to 1201 1200 0 0 0 0 0 0 0 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 6 5 4 3 2 1 0 UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8 0 0 0 0 0 0 0 0 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 Notes: 1. This register is not availabel in the H8S/2635 and H8S/2634 2. Only 1 can be written, to clear the flag to 0. Rev. 6.00 Feb 22, 2005 page xxix of lx 00000 Item B.2 Functions Page 1266 to 1329 Revision (See Manual for Details) MC0[1] H'FA20 HCAN1 to MD15[8] H'FB2F HCAN1 Note added Note: These registers are not available in the H8S/2635 and H8S/2634. 1341 SCKCR H'FDE6 System Note * amended Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. ... 1344 LPWRCR H'FDEC System Note * amended Note: * Bits in 7 to 3 in LPWRCR are valid in the U-mask and W-mask versions, and H8S/2635 Group; they are reserved bits in all other versions. ... 1345 BARA H'FE00 PBC, Note 2 added BARB H'FE04 PBC Notes: 1. The bit configuration ob BARB is the same as for BARA. 2. These registers are not available in the H8S/2635 and H8S/2634. 1346 BCRA H'FE08 PBC, Note 2 added Notes: 1. The bit configuration of BCRB is the same as for BCRA. 2. These registers are not available in the H8S/2635 and H8S/2634. 1349 to 1356 DTCERA H'FE16 DTC to DTVECR H'FE1F DTC, PCR H'FE26 PPG to NDRL H'FE2F PPG Note added Note: This register is not available in the H8S/2635 and H8S/2634. BCRB H'FE09 PBC Rev. 6.00 Feb 22, 2005 page xxx of lx Item B.2 Functions Page 1360 Revision (See Manual for Details) P3ODR H'FE46 Port Figure amended Bit Initial value Read/Write 7 6 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR Undefined Undefined PAODR H'FE47 Port Figure amended Bit Initial value Read/Write 7 6 5 4 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PA3ODR PA2ODR PA1ODR PA0ODR Undefined Undefined Undefined Undefined 1361 PBODR H'FE48 Port Figure amended Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR PCODR H'FE49 Port Figure amended Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR 1382 IPRA H'FEC0 INT to IPRM H'FECC INT Note *3 added DTC*3 PC break*3 HCAN channel 1*3 Note: 3. The DTC, PC break, and HCAN are not implemented in the H8S/2635 and H8S/2634. 1387 BCRL H'FED5 Bus Controller Figure amended 2 0 R/W 1 WDBE 0 R/W 0 0 R/W Rev. 6.00 Feb 22, 2005 page xxxi of lx Item B.2 Functions Page 1388 Revision (See Manual for Details) RAMER H'FEDB Flash Memory Figure amended Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R/W 4 0 R/W 3 RAMS 0 R/W 2 RAM2 0 R/W 1 RAM1 0 R/W 0 RAM0 0 R/W Flash Memory Area Selection * H8S/2636 Addresses H'FFE000-H'FFE3FF H'000000-H'0003FF H'000400-H'0007FF H'000800-H'000BFF H'000C00-H'000FFF Block Name RAMS RAM2 RAM1 RAM0 * 0 * * RAM area 1 kB 1 0 0 EB0 (1 kB) 1 EB1 (1 kB) 1 0 EB2 (1 kB) 1 EB3 (1 kB) *: Don't care * H8S/2638, H8S/2639, H8S/2630 Addresses H'FFD000-H'FFDFFF H'000000-H'000FFF H'001000-H'001FFF H'002000-H'002FFF H'003000-H'003FFF H'004000-H'004FFF H'005000-H'005FFF H'006000-H'006FFF H'007000-H'007FFF * H8S/2635 Addresses H'FFD800-H'FFE7FF H'000000-H'000FFF H'001000-H'001FFF H'002000-H'002FFF H'003000-H'003FFF H'004000-H'004FFF H'005000-H'005FFF H'006000-H'006FFF H'007000-H'007FFF RAM Select 0 1 Emulation not selected Program/erase-protection of all flash memory blocks is disabled Emulation selected Program/erase-protection of all flash memory blocks is enabled Block Name RAM area 4 kB EB0 (4 kB) EB1 (4 kB) EB2 (4 kB) EB3 (4 kB) EB4 (4 kB) EB5 (4 kB) EB6 (4 kB) EB7 (4 kB) RAMS RAM2 RAM1 RAM0 0 * * * 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 *: Don't care Block Name RAM area 4 kB EB0 (4 kB) EB1 (4 kB) EB2 (4 kB) EB3 (4 kB) EB4 (4 kB) EB5 (4 kB) EB6 (4 kB) EB7 (4 kB) RAMS RAM2 RAM1 RAM0 0 * * * 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 *: Don't care Rev. 6.00 Feb 22, 2005 page xxxii of lx Item B.2 Functions Page 1438 Revision (See Manual for Details) TCSR1 H'FFA2(W), H'FFA2(R) WDT1 Figure amended Bit Initial value Read/Write 7 OVF 0 R/(W)*1 6 WT/IT 0 R/W 5 TME 0 R/W 4 0 R/W 3 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W PSS*2 RST/NMI Clock Select 2 to 0 PSS CKS2 CKS1 CKS0 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock /2 /64 /128 /512 /2048 /8192 /32768 /131072 SUB/2*2 SUB/4*2 SUB/8*2 SUB/16*2 SUB/32*2 SUB/64*2 SUB/128*2 SUB/256*2 Overflow Period*1 (where = 20 MHz) (where SUB*2 = 32.768 kHz) 25.6 s 819.2 s 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s 15.6 ms 31.3 ms 62.5 ms 125 ms 250 ms 500 ms 1s 2s 0 1 1 0 Notes: 1. An overflow period is the time interval between the start of counting up from H'00 on the TCNT and the occurrence of a TCNT overflow. 2. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask, W-mask versions, and H8S/2635 Group only, but are not available in the other versions. Reset or NMI 0 1 NMI request Internal reset request Prescaler Select 0 1 The TCNT counts frequency-division clock pulses of the based prescaler (PSM) The TCNT counts frequency-division clock pulses of the SUB*-based prescaler (PSS) Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask, W-mask versions, and H8S/2635 Group only. These functions cannot be used with the other versions, and in them the PSS bit is reserved. Only 0 should be written to this bit. Timer Enable 0 1 TCNT is initialized to H'00 and halted TCNT counts Timer Mode Select 0 1 Overflow Flag 0 [Clearing conditions] * Write 0 in the TME bit (Only applies to WDT1) * Read TCSR* when OVF = 1, then write 0 in OVF [Setting condition] * When TCNT overflows (changes from H'FF to H'00) (When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset) Interval timer mode: WDT1 requests an interval timer interrupt (WOVI) from the CPU when the TCNT overflows Watchdog timer mode: WDT1 requests a reset or an NMI interrupt from the CPU when the TCNT overflows 1 Note: * When interval timer interrupts are disabled and OVF is polled, read the OVF = 1 state at least twice. Notes: TCSR1 register differs from other registers in being more difficult to write to. For details see section 12.2.4, Notes on Register Access. 1. Only 0 can be written, to clear the flag. 2. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask, W-mask versions, and H8S/2635 Group only. 1439 DADR0 H'FFA4 D/A0, 1, DADR1 H'FFA5 D/A0, 1 Note added Note: These registers are not available in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page xxxiii of lx Item B.2 Functions Page 1440 Revision (See Manual for Details) DACR01 H'FFA6 D/A0, 1 Note added Note: This register is not available in the H8S/2635 and H8S/2634. 1443 EBR1 H'FFAA Flash Memory, EBR2 H'FFAB Flash Memory Figure amended EBR1 Bit Initial value Read/Write EBR2 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 EB13*3 0 R/W 4 EB12*3 0 R/W 3 EB11*2 0 R/W 2 EB10*1 0 R/W 1 EB9 0 R/W 0 EB8 0 R/W 15 EB7 0 R/W 14 EB6 0 R/W 13 EB5 0 R/W 12 EB4 0 R/W 11 EB3 0 R/W 10 EB2 0 R/W 9 EB1 0 R/W 8 EB0 0 R/W Specify the flash memory erase area * H8S/2636 Block (Size) EB0 (1 kbyte) EB1 (1 kbyte) EB2 (1 kbyte) EB3 (1 kbyte) EB4 (28 kbytes) EB5 (16 kbytes) EB6 (8 kbytes) EB7 (8 kbytes) EB8 (32 kbytes) EB9 (32 kbytes) Addresses H'000000 to H'0003FF H'000400 to H'0007FF H'000800 to H'000BFF H'000C00 to H'000FFF H'001000 to H'007FFF H'008000 to H'00BFFF H'00C000 to H'00DFFF H'00E000 to H'00FFFF H'010000 to H'017FFF H'018000 to H'01FFFF * H8S/2638, H8S/2639 Block (Size) Addresses EB0 (4 kbytes) H'000000 to H'000FFF EB1 (4 kbytes) H'001000 to H'001FFF EB2 (4 kbytes) H'002000 to H'002FFF EB3 (4 kbytes) H'003000 to H'003FFF EB4 (4 kbytes) H'004000 to H'004FFF EB5 (4 kbytes) H'005000 to H'005FFF EB6 (4 kbytes) H'006000 to H'006FFF EB7 (4 kbytes) H'007000 to H'007FFF EB8 (32 kbytes) H'008000 to H'00FFFF EB9 (64 kbytes) H'010000 to H'01FFFF EB10 (64 kbytes) H'020000 to H'02FFFF EB11 (64 kbytes) H'030000 to H'03FFFF * H8S/2630 Block (Size) EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) EB8 (32 kbytes) EB9 (64 kbytes) EB10 (64 kbytes) EB11 (64 kbytes) EB12 (64 kbytes) EB13 (64 kbytes) * H8S/2635 Block (Size) EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) EB8 (32 kbytes) EB9 (64 kbytes) EB10 (64 kbytes) Addresses H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF H'008000 to H'00FFFF H'010000 to H'01FFFF H'020000 to H'02FFFF Addresses H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF H'008000 to H'00FFFF H'010000 to H'01FFFF H'020000 to H'02FFFF H'030000 to H'03FFFF H'040000 to H'04FFFF H'050000 to H'05FFFF Notes: 1. On the H8S/2636, these bits are reserved. 2. Reserved in the H8S/2636 and H8S/2635. 3. Reserved in the H8S/2638, H8S/2639, and H8S/2635. Rev. 6.00 Feb 22, 2005 page xxxiv of lx Item C.1 Port 1 Block Diagrams Figure C-1 (a) Port 1 Block Diagram (Pins P10 and P11) to Figure C-1 (f) Port 1 Block Diagram (Pin P17) C.3 Port 4 Block Diagram Figure C-3 (b) Port 4 Block Diagram (Pins P46, P47) D.1 Port States in Each Mode Table D-1 I/O Port States in Each Processing State Page 1448 to 1453 Revision (See Manual for Details) Note *2 added PPG module*2 Notes: 1. Priority order: ... 2. The PPG module is not implemented in the H8S/2635 and H8S/2634. 1460 Note * added D/A converter module* Notes: The D/A converter is not implemented in the H8S/2635 and H8S/2634. n = 6, 7 1479, 1480 Table D-1 amended Port Name Pin Name PF6/AS PF5/RD PF4/ HWR Port Name Pin Name PF3/LWR Rev. 6.00 Feb 22, 2005 page xxxv of lx Item F. Product Code Lineup Table F-1 H8S/2636, H8S/2638, H8S/2639, and H8S/2630 Product Code Lineup Page 1483 Revision (See Manual for Details) Table F-1 amended Product Type H8S/2630 F-ZTAT version Product Code HD64F2630 Mark Code HD64F2630F HD64F2630UF Functions No subclock function 2 or I C bus interface Subclock function, 2 no I C bus interface Packages 128-pin QFP (FP-128B) 128-pin QFP (FP-128B) HD64F2630WF Subclock function and 128-pin QFP 2 I C bus interface (FP-128B) Mask ROM HD6432630 version HD6432630F HD6432630UF No subclock function or I2C bus interface Subclock function, 2 no I C bus interface 128-pin QFP (FP-128B) 128-pin QFP (FP-128B) HD6432630WF Subclock function and 128-pin QFP I2C bus interface (FP-128B) H8S/2635 F-ZTAT version HD64F2635 HD64F2635F HD6432635F HD6432634F Subclock function, no I2C bus interface Subclock function, 2 no I C bus interface Subclock function, no I2C bus interface 128-pin QFP (FP-128B) 128-pin QFP (FP-128B) 128-pin QFP (FP-128B) Mask ROM HD6432635* version HD6432634* Note: * Under development G Package Dimensions Figure G-1 FP-128B Package Dimensions 1484 Figure G-1 replaced Rev. 6.00 Feb 22, 2005 page xxxvi of lx Contents Section 1 Overview............................................................................................................. 1.1 1.2 1.3 1 1 6 9 9 13 18 1.4 Overview........................................................................................................................... Internal Block Diagram..................................................................................................... Pin Description ................................................................................................................. 1.3.1 Pin Arrangement.................................................................................................. 1.3.2 Pin Functions in Each Operating Mode ............................................................... 1.3.3 Pin Functions ....................................................................................................... Differences between H8S/2636, H8S/2638, H8S/2639, H8S/2630, H8S/2635, and H8S/2634 .......................................................................................................................... 23 Section 2 CPU ...................................................................................................................... 25 2.1 Overview........................................................................................................................... 2.1.1 Features................................................................................................................ 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 2.1.3 Differences from H8/300 CPU ............................................................................ 2.1.4 Differences from H8/300H CPU ......................................................................... CPU Operating Modes...................................................................................................... Address Space................................................................................................................... Register Configuration...................................................................................................... 2.4.1 Overview.............................................................................................................. 2.4.2 General Registers................................................................................................. 2.4.3 Control Registers ................................................................................................. 2.4.4 Initial Register Values ......................................................................................... Data Formats..................................................................................................................... 2.5.1 General Register Data Formats............................................................................ 2.5.2 Memory Data Formats......................................................................................... Instruction Set................................................................................................................... 2.6.1 Overview.............................................................................................................. 2.6.2 Instructions and Addressing Modes..................................................................... 2.6.3 Table of Instructions Classified by Function ...................................................... 2.6.4 Basic Instruction Formats .................................................................................... Addressing Modes and Effective Address Calculation..................................................... 2.7.1 Addressing Mode................................................................................................. 2.7.2 Effective Address Calculation ............................................................................. Processing States .............................................................................................................. 2.8.1 Overview.............................................................................................................. 2.8.2 Reset State ........................................................................................................... 25 25 26 27 28 28 33 34 34 35 36 38 39 39 41 42 42 43 45 54 56 56 59 63 63 64 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Rev. 6.00 Feb 22, 2005 page xxxvii of lx 2.8.3 Exception-Handling State .................................................................................... 2.8.4 Program Execution State ..................................................................................... 2.8.5 Bus-Released State .............................................................................................. 2.8.6 Power-Down State ............................................................................................... 2.9 Basic Timing..................................................................................................................... 2.9.1 Overview.............................................................................................................. 2.9.2 On-Chip Memory (ROM, RAM)......................................................................... 2.9.3 On-Chip Supporting Module Access Timing ...................................................... 2.9.4 On-Chip HCAN Module Access Timing............................................................. 2.9.5 Port H and J Register Access Timing .................................................................. 2.9.6 External Address Space Access Timing .............................................................. 2.10 Usage Note ....................................................................................................................... 2.10.1 TAS Instruction ................................................................................................... 2.10.2 STM/LDM Instructions ....................................................................................... 2.10.3 Caution to Observe when Using Bit Manipulation Instructions .......................... 65 68 68 68 69 69 69 71 73 75 76 77 77 77 77 Section 3 MCU Operating Modes .................................................................................. 79 3.1 Overview........................................................................................................................... 3.1.1 Operating Mode Selection ................................................................................... 3.1.2 Register Configuration......................................................................................... Register Descriptions........................................................................................................ 3.2.1 Mode Control Register (MDCR) ......................................................................... 3.2.2 System Control Register (SYSCR)...................................................................... 3.2.3 Pin Function Control Register (PFCR) ................................................................ Operating Mode Descriptions ........................................................................................... 3.3.1 Mode 4................................................................................................................. 3.3.2 Mode 5................................................................................................................. 3.3.3 Mode 6................................................................................................................. 3.3.4 Mode 7................................................................................................................. Pin Functions in Each Operating Mode ............................................................................ Address Map in Each Operating Mode............................................................................. 79 79 80 80 80 81 83 85 85 85 85 86 86 87 3.2 3.3 3.4 3.5 Section 4 Exception Handling ......................................................................................... 93 4.1 Overview........................................................................................................................... 4.1.1 Exception Handling Types and Priority............................................................... 4.1.2 Exception Handling Operation ............................................................................ 4.1.3 Exception Vector Table ....................................................................................... Reset ................................................................................................................................. 4.2.1 Overview.............................................................................................................. 4.2.2 Reset Sequence .................................................................................................... 93 93 94 94 96 96 96 4.2 Rev. 6.00 Feb 22, 2005 page xxxviii of lx 4.3 4.4 4.5 4.6 4.7 4.2.3 Interrupts after Reset............................................................................................ 4.2.4 State of On-Chip Supporting Modules after Reset Release ................................. Traces................................................................................................................................ Interrupts........................................................................................................................... Trap Instruction ................................................................................................................ Stack Status after Exception Handling.............................................................................. Notes on Use of the Stack................................................................................................. 98 99 99 100 101 102 103 Section 5 Interrupt Controller .......................................................................................... 105 5.1 Overview........................................................................................................................... 5.1.1 Features................................................................................................................ 5.1.2 Block Diagram..................................................................................................... 5.1.3 Pin Configuration ................................................................................................ 5.1.4 Register Configuration......................................................................................... Register Descriptions........................................................................................................ 5.2.1 System Control Register (SYSCR)...................................................................... 5.2.2 Interrupt Priority Registers A to H, J to M (IPRA to IPRH, IPRJ to IPRM) ....... 5.2.3 IRQ Enable Register (IER) .................................................................................. 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 5.2.5 IRQ Status Register (ISR).................................................................................... Interrupt Sources............................................................................................................... 5.3.1 External Interrupts ............................................................................................... 5.3.2 Internal Interrupts ................................................................................................ 5.3.3 Interrupt Exception Handling Vector Table......................................................... Interrupt Operation ........................................................................................................... 5.4.1 Interrupt Control Modes and Interrupt Operation................................................ 5.4.2 Interrupt Control Mode 0..................................................................................... 5.4.3 Interrupt Control Mode 2..................................................................................... 5.4.4 Interrupt Exception Handling Sequence .............................................................. 5.4.5 Interrupt Response Times .................................................................................... Usage Notes ...................................................................................................................... 5.5.1 Contention between Interrupt Generation and Disabling..................................... 5.5.2 Instructions that Disable Interrupts...................................................................... 5.5.3 Times when Interrupts Are Disabled ................................................................... 5.5.4 Interrupts during Execution of EEPMOV Instruction ......................................... 5.5.5 IRQ Interrupts...................................................................................................... 5.5.6 Notes on Use of NMI Interrupt............................................................................ DTC Activation by Interrupt............................................................................................. 5.6.1 Overview.............................................................................................................. 5.6.2 Block Diagram..................................................................................................... 105 105 106 107 107 108 108 109 110 111 112 114 114 116 116 120 120 124 126 128 129 130 130 131 131 132 132 132 133 133 133 5.2 5.3 5.4 5.5 5.6 Rev. 6.00 Feb 22, 2005 page xxxix of lx 5.6.3 Operation ............................................................................................................. 134 Section 6 PC Break Controller (PBC)........................................................................... 137 6.1 Overview........................................................................................................................... 6.1.1 Features................................................................................................................ 6.1.2 Block Diagram..................................................................................................... 6.1.3 Register Configuration......................................................................................... Register Descriptions........................................................................................................ 6.2.1 Break Address Register A (BARA) ..................................................................... 6.2.2 Break Address Register B (BARB) ..................................................................... 6.2.3 Break Control Register A (BCRA) ...................................................................... 6.2.4 Break Control Register B (BCRB) ...................................................................... 6.2.5 Module Stop Control Register C (MSTPCRC) ................................................... Operation .......................................................................................................................... 6.3.1 PC Break Interrupt Due to Instruction Fetch ....................................................... 6.3.2 PC Break Interrupt Due to Data Access .............................................................. 6.3.3 Notes on PC Break Interrupt Handling................................................................ 6.3.4 Operation in Transitions to Power-Down Modes ................................................ 6.3.5 PC Break Operation in Continuous Data Transfer............................................... 6.3.6 When Instruction Execution Is Delayed by One State......................................... 6.3.7 Additional Notes.................................................................................................. 137 137 138 139 139 139 140 140 142 142 143 143 144 144 145 146 147 148 6.2 6.3 Section 7 Bus Controller ................................................................................................... 149 7.1 Overview........................................................................................................................... 7.1.1 Features................................................................................................................ 7.1.2 Block Diagram..................................................................................................... 7.1.3 Pin Configuration ................................................................................................ 7.1.4 Register Configuration......................................................................................... Register Descriptions........................................................................................................ 7.2.1 Bus Width Control Register (ABWCR)............................................................... 7.2.2 Access State Control Register (ASTCR) ............................................................. 7.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 7.2.4 Bus Control Register H (BCRH) ......................................................................... 7.2.5 Bus Control Register L (BCRL) .......................................................................... 7.2.6 Pin Function Control Register (PFCR) ................................................................ Overview of Bus Control.................................................................................................. 7.3.1 Area Partitioning.................................................................................................. 7.3.2 Bus Specifications ............................................................................................... 7.3.3 Memory Interfaces............................................................................................... 7.3.4 Interface Specifications for Each Area ................................................................ 149 149 150 151 151 152 152 153 154 158 160 161 163 163 164 165 166 7.2 7.3 Rev. 6.00 Feb 22, 2005 page xl of lx 7.4 7.5 7.6 7.7 7.8 7.9 Basic Bus Interface ........................................................................................................... 7.4.1 Overview.............................................................................................................. 7.4.2 Data Size and Data Alignment............................................................................. 7.4.3 Valid Strobes ....................................................................................................... 7.4.4 Basic Timing........................................................................................................ 7.4.5 Wait Control ........................................................................................................ Burst ROM Interface ........................................................................................................ 7.5.1 Overview.............................................................................................................. 7.5.2 Basic Timing........................................................................................................ 7.5.3 Wait Control ........................................................................................................ Idle Cycle.......................................................................................................................... 7.6.1 Operation ............................................................................................................. 7.6.2 Pin States During Idle Cycles .............................................................................. Write Data Buffer Function .............................................................................................. Bus Arbitration ................................................................................................................. 7.8.1 Overview.............................................................................................................. 7.8.2 Operation ............................................................................................................. 7.8.3 Bus Transfer Timing............................................................................................ Resets and the Bus Controller........................................................................................... 167 167 167 169 170 178 179 179 179 181 181 181 185 186 187 187 187 187 188 Section 8 Data Transfer Controller (DTC)................................................................... 189 8.1 Overview........................................................................................................................... 8.1.1 Features................................................................................................................ 8.1.2 Block Diagram..................................................................................................... 8.1.3 Register Configuration......................................................................................... Register Descriptions........................................................................................................ 8.2.1 DTC Mode Register A (MRA) ............................................................................ 8.2.2 DTC Mode Register B (MRB)............................................................................. 8.2.3 DTC Source Address Register (SAR).................................................................. 8.2.4 DTC Destination Address Register (DAR).......................................................... 8.2.5 DTC Transfer Count Register A (CRA) .............................................................. 8.2.6 DTC Transfer Count Register B (CRB)............................................................... 8.2.7 DTC Enable Registers (DTCER)......................................................................... 8.2.8 DTC Vector Register (DTVECR)........................................................................ 8.2.9 Module Stop Control Register A (MSTPCRA) ................................................... Operation .......................................................................................................................... 8.3.1 Overview.............................................................................................................. 8.3.2 Activation Sources............................................................................................... 8.3.3 DTC Vector Table ............................................................................................... 8.3.4 Location of Register Information in Address Space ............................................ 189 189 190 191 192 192 194 195 195 195 196 196 197 199 200 200 202 204 208 8.2 8.3 Rev. 6.00 Feb 22, 2005 page xli of lx 8.4 8.5 8.3.5 Normal Mode....................................................................................................... 8.3.6 Repeat Mode........................................................................................................ 8.3.7 Block Transfer Mode........................................................................................... 8.3.8 Chain Transfer ..................................................................................................... 8.3.9 Operation Timing................................................................................................. 8.3.10 Number of DTC Execution States ....................................................................... 8.3.11 Procedures for Using DTC .................................................................................. 8.3.12 Examples of Use of the DTC............................................................................... Interrupts........................................................................................................................... Usage Notes ...................................................................................................................... 209 210 211 213 214 215 217 218 221 221 Section 9 I/O Ports .............................................................................................................. 223 9.1 9.2 Overview........................................................................................................................... Port 1................................................................................................................................. 9.2.1 Overview.............................................................................................................. 9.2.2 Register Configuration......................................................................................... 9.2.3 Pin Functions ....................................................................................................... Port 3................................................................................................................................. 9.3.1 Overview.............................................................................................................. 9.3.2 Register Configuration......................................................................................... 9.3.3 Pin Functions ....................................................................................................... Port 4................................................................................................................................. 9.4.1 Overview.............................................................................................................. 9.4.2 Register Configuration......................................................................................... 9.4.3 Pin Functions ....................................................................................................... Port 9................................................................................................................................. 9.5.1 Overview.............................................................................................................. 9.5.2 Register Configuration......................................................................................... 9.5.3 Pin Functions ....................................................................................................... Port A................................................................................................................................ 9.6.1 Overview.............................................................................................................. 9.6.2 Register Configuration......................................................................................... 9.6.3 Pin Functions ....................................................................................................... 9.6.4 Pin Functions ....................................................................................................... 9.6.5 MOS Input Pull-Up Function .............................................................................. Port B................................................................................................................................ 9.7.1 Overview.............................................................................................................. 9.7.2 Register Configuration......................................................................................... 9.7.3 Pin Functions ....................................................................................................... 9.7.4 MOS Input Pull-Up Function .............................................................................. 223 227 227 228 229 242 242 243 245 248 248 249 249 250 250 251 251 252 252 253 256 258 259 260 260 261 264 265 9.3 9.4 9.5 9.6 9.7 Rev. 6.00 Feb 22, 2005 page xlii of lx 9.8 9.9 9.10 9.11 9.12 9.13 Port C................................................................................................................................ 9.8.1 Overview.............................................................................................................. 9.8.2 Register Configuration......................................................................................... 9.8.3 Pin Functions for Each Mode .............................................................................. 9.8.4 MOS Input Pull-Up Function .............................................................................. Port D................................................................................................................................ 9.9.1 Overview.............................................................................................................. 9.9.2 Register Configuration......................................................................................... 9.9.3 Pin Functions ....................................................................................................... 9.9.4 MOS Input Pull-Up Function .............................................................................. Port E ................................................................................................................................ 9.10.1 Overview.............................................................................................................. 9.10.2 Register Configuration......................................................................................... 9.10.3 Pin Functions ....................................................................................................... 9.10.4 MOS Input Pull-Up Function .............................................................................. Port F ................................................................................................................................ 9.11.1 Overview.............................................................................................................. 9.11.2 Register Configuration......................................................................................... 9.11.3 Pin Functions ....................................................................................................... Port H................................................................................................................................ 9.12.1 Overview.............................................................................................................. 9.12.2 Register Configuration......................................................................................... 9.12.3 Pin Functions ....................................................................................................... Port J ................................................................................................................................. 9.13.1 Overview.............................................................................................................. 9.13.2 Register Configuration......................................................................................... 9.13.3 Pin Functions ....................................................................................................... 266 266 267 270 272 273 273 274 276 277 278 278 279 281 283 284 284 285 287 289 289 290 291 292 292 293 294 Section 10 16-Bit Timer Pulse Unit (TPU).................................................................. 295 10.1 Overview........................................................................................................................... 10.1.1 Features................................................................................................................ 10.1.2 Block Diagram..................................................................................................... 10.1.3 Pin Configuration ................................................................................................ 10.1.4 Register Configuration......................................................................................... 10.2 Register Descriptions........................................................................................................ 10.2.1 Timer Control Register (TCR)............................................................................. 10.2.2 Timer Mode Register (TMDR)............................................................................ 10.2.3 Timer I/O Control Register (TIOR)..................................................................... 10.2.4 Timer Interrupt Enable Register (TIER).............................................................. 10.2.5 Timer Status Register (TSR)................................................................................ 295 295 299 300 302 304 304 309 311 325 328 Rev. 6.00 Feb 22, 2005 page xliii of lx 10.3 10.4 10.5 10.6 10.7 10.2.6 Timer Counter (TCNT)........................................................................................ 10.2.7 Timer General Register (TGR) ............................................................................ 10.2.8 Timer Start Register (TSTR) ............................................................................... 10.2.9 Timer Synchro Register (TSYR) ......................................................................... 10.2.10 Module Stop Control Register A (MSTPCRA) ................................................... Interface to Bus Master..................................................................................................... 10.3.1 16-Bit Registers ................................................................................................... 10.3.2 8-Bit Registers ..................................................................................................... Operation .......................................................................................................................... 10.4.1 Overview.............................................................................................................. 10.4.2 Basic Functions.................................................................................................... 10.4.3 Synchronous Operation ....................................................................................... 10.4.4 Buffer Operation.................................................................................................. 10.4.5 Cascaded Operation ............................................................................................. 10.4.6 PWM Modes........................................................................................................ 10.4.7 Phase Counting Mode.......................................................................................... Interrupts........................................................................................................................... 10.5.1 Interrupt Sources and Priorities ........................................................................... 10.5.2 DTC Activation ................................................................................................... 10.5.3 A/D Converter Activation.................................................................................... Operation Timing.............................................................................................................. 10.6.1 Input/Output Timing............................................................................................ 10.6.2 Interrupt Signal Timing ....................................................................................... Usage Notes ...................................................................................................................... 332 333 334 335 336 337 337 337 339 339 340 346 348 352 354 360 367 367 369 369 370 370 374 378 389 389 389 390 391 392 393 393 394 395 395 397 399 402 402 Section 11 Programmable Pulse Generator (PPG) .................................................... 11.1 Overview........................................................................................................................... 11.1.1 Features................................................................................................................ 11.1.2 Block Diagram..................................................................................................... 11.1.3 Pin Configuration ................................................................................................ 11.1.4 Registers .............................................................................................................. 11.2 Register Descriptions........................................................................................................ 11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................................... 11.2.2 Output Data Registers H and L (PODRH, PODRL)............................................ 11.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 11.2.4 Notes on NDR Access ......................................................................................... 11.2.5 PPG Output Control Register (PCR) ................................................................... 11.2.6 PPG Output Mode Register (PMR) ..................................................................... 11.2.7 Port 1 Data Direction Register (P1DDR)............................................................. 11.2.8 Module Stop Control Register A (MSTPCRA) ................................................... Rev. 6.00 Feb 22, 2005 page xliv of lx 11.3 Operation .......................................................................................................................... 11.3.1 Overview.............................................................................................................. 11.3.2 Output Timing ..................................................................................................... 11.3.3 Normal Pulse Output ........................................................................................... 11.3.4 Non-Overlapping Pulse Output ........................................................................... 11.3.5 Inverted Pulse Output .......................................................................................... 11.3.6 Pulse Output Triggered by Input Capture............................................................ 11.4 Usage Notes ...................................................................................................................... 403 403 404 405 407 410 411 412 Section 12 Watchdog Timer............................................................................................. 415 12.1 Overview........................................................................................................................... 12.1.1 Features................................................................................................................ 12.1.2 Block Diagram..................................................................................................... 12.1.3 Pin Configuration ................................................................................................ 12.1.4 Register Configuration......................................................................................... 12.2 Register Descriptions........................................................................................................ 12.2.1 Timer Counter (TCNT)........................................................................................ 12.2.2 Timer Control/Status Register (TCSR)................................................................ 12.2.3 Reset Control/Status Register (RSTCSR)............................................................ 12.2.4 Notes on Register Access .................................................................................... 12.3 Operation .......................................................................................................................... 12.3.1 Watchdog Timer Operation ................................................................................. 12.3.2 Interval Timer Operation ..................................................................................... 12.3.3 Timing of Setting Overflow Flag (OVF) ............................................................. 12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) ......................... 12.4 Interrupts........................................................................................................................... 12.5 Usage Notes ...................................................................................................................... 12.5.1 Contention between Timer Counter (TCNT) Write and Increment..................... 12.5.2 Changing Value of PSS and CKS2 to CKS0 ....................................................... 12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 12.5.4 Internal Reset in Watchdog Timer Mode............................................................. 12.5.5 OVF Flag Clearing in Interval Timer Mode ........................................................ 415 415 416 418 418 419 419 420 426 427 429 429 431 431 432 433 433 433 434 434 434 434 435 435 435 437 438 439 440 Section 13 Serial Communication Interface (SCI) .................................................... 13.1 Overview........................................................................................................................... 13.1.1 Features................................................................................................................ 13.1.2 Block Diagram..................................................................................................... 13.1.3 Pin Configuration ................................................................................................ 13.1.4 Register Configuration......................................................................................... 13.2 Register Descriptions........................................................................................................ Rev. 6.00 Feb 22, 2005 page xlv of lx 13.2.1 Receive Shift Register (RSR) .............................................................................. 13.2.2 Receive Data Register (RDR).............................................................................. 13.2.3 Transmit Shift Register (TSR)............................................................................. 13.2.4 Transmit Data Register (TDR) ............................................................................ 13.2.5 Serial Mode Register (SMR) ............................................................................... 13.2.6 Serial Control Register (SCR) ............................................................................. 13.2.7 Serial Status Register (SSR) ................................................................................ 13.2.8 Bit Rate Register (BRR) ...................................................................................... 13.2.9 Smart Card Mode Register (SCMR).................................................................... 13.2.10 Module Stop Control Register B (MSTPCRB) ................................................... 13.3 Operation .......................................................................................................................... 13.3.1 Overview.............................................................................................................. 13.3.2 Operation in Asynchronous Mode ....................................................................... 13.3.3 Multiprocessor Communication Function ........................................................... 13.3.4 Operation in Clocked Synchronous Mode........................................................... 13.4 SCI Interrupts.................................................................................................................... 13.5 Usage Notes ...................................................................................................................... 440 440 441 441 442 445 449 453 460 461 463 463 465 476 484 493 494 503 503 503 504 505 506 507 507 509 511 513 514 514 514 516 518 520 522 529 530 531 Section 14 Smart Card Interface ..................................................................................... 14.1 Overview........................................................................................................................... 14.1.1 Features................................................................................................................ 14.1.2 Block Diagram..................................................................................................... 14.1.3 Pin Configuration ................................................................................................ 14.1.4 Register Configuration......................................................................................... 14.2 Register Descriptions........................................................................................................ 14.2.1 Smart Card Mode Register (SCMR).................................................................... 14.2.2 Serial Status Register (SSR) ................................................................................ 14.2.3 Serial Mode Register (SMR) ............................................................................... 14.2.4 Serial Control Register (SCR) ............................................................................. 14.3 Operation .......................................................................................................................... 14.3.1 Overview.............................................................................................................. 14.3.2 Pin Connections................................................................................................... 14.3.3 Data Format ......................................................................................................... 14.3.4 Register Settings .................................................................................................. 14.3.5 Clock.................................................................................................................... 14.3.6 Data Transfer Operations..................................................................................... 14.3.7 Operation in GSM Mode ..................................................................................... 14.3.8 Operation in Block Transfer Mode ...................................................................... 14.4 Usage Notes ...................................................................................................................... Rev. 6.00 Feb 22, 2005 page xlvi of lx Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630)........................... 535 15.1 Overview........................................................................................................................... 15.1.1 Features................................................................................................................ 15.1.2 Block Diagram..................................................................................................... 15.1.3 Input/Output Pins................................................................................................. 15.1.4 Register Configuration......................................................................................... 15.2 Register Descriptions........................................................................................................ 15.2.1 I2C Bus Data Register (ICDR)............................................................................. 15.2.2 Slave Address Register (SAR)............................................................................. 15.2.3 Second Slave Address Register (SARX) ............................................................. 15.2.4 I2C Bus Mode Register (ICMR) .......................................................................... 15.2.5 I2C Bus Control Register (ICCR) ........................................................................ 15.2.6 I2C Bus Status Register (ICSR) ........................................................................... 15.2.7 Serial Control Register X (SCRX)....................................................................... 15.2.8 DDC Switch Register (DDCSWR)...................................................................... 15.2.9 Module Stop Control Register B (MSTPCRB) ................................................... 15.3 Operation .......................................................................................................................... 15.3.1 I2C Bus Data Format............................................................................................ 15.3.2 Initial Setting ....................................................................................................... 15.3.3 Master Transmit Operation.................................................................................. 15.3.4 Master Receive Operation ................................................................................... 15.3.5 Slave Receive Operation...................................................................................... 15.3.6 Slave Transmit Operation .................................................................................... 15.3.7 IRIC Setting Timing and SCL Control ................................................................ 15.3.8 Operation Using the DTC .................................................................................... 15.3.9 Noise Canceler..................................................................................................... 15.3.10 Initialization of Internal State .............................................................................. 15.4 Usage Notes ...................................................................................................................... 535 535 536 538 539 540 540 543 544 545 549 557 563 564 565 566 566 568 568 572 577 582 585 586 587 587 589 601 601 601 603 604 605 609 609 610 612 Section 16 Controller Area Network (HCAN) ........................................................... 16.1 Overview........................................................................................................................... 16.1.1 Features................................................................................................................ 16.1.2 Block Diagram..................................................................................................... 16.1.3 Pin Configuration ................................................................................................ 16.1.4 Register Configuration......................................................................................... 16.2 Register Descriptions........................................................................................................ 16.2.1 Master Control Register (MCR) .......................................................................... 16.2.2 General Status Register (GSR) ............................................................................ 16.2.3 Bit Configuration Register (BCR) ....................................................................... Rev. 6.00 Feb 22, 2005 page xlvii of lx 16.2.4 Mailbox Configuration Register (MBCR) ........................................................... 16.2.5 Transmit Wait Register (TXPR) .......................................................................... 16.2.6 Transmit Wait Cancel Register (TXCR).............................................................. 16.2.7 Transmit Acknowledge Register (TXACK) ........................................................ 16.2.8 Abort Acknowledge Register (ABACK) ............................................................. 16.2.9 Receive Complete Register (RXPR).................................................................... 16.2.10 Remote Request Register (RFPR) ....................................................................... 16.2.11 Interrupt Register (IRR)....................................................................................... 16.2.12 Mailbox Interrupt Mask Register (MBIMR) ....................................................... 16.2.13 Interrupt Mask Register (IMR) ............................................................................ 16.2.14 Receive Error Counter (REC).............................................................................. 16.2.15 Transmit Error Counter (TEC) ............................................................................ 16.2.16 Unread Message Status Register (UMSR)........................................................... 16.2.17 Local Acceptance Filter Masks (LAFML, LAFMH)........................................... 16.2.18 Message Control (MC0 to MC15) ....................................................................... 16.2.19 Message Data (MD0 to MD15) ........................................................................... 16.2.20 Module Stop Control Register C (MSTPCRC) ................................................... 16.3 Operation .......................................................................................................................... 16.3.1 Hardware and Software Resets ............................................................................ 16.3.2 Initialization after Hardware Reset ...................................................................... 16.3.3 Transmit Mode .................................................................................................... 16.3.4 Receive Mode ...................................................................................................... 16.3.5 HCAN Sleep Mode.............................................................................................. 16.3.6 HCAN Halt Mode................................................................................................ 16.3.7 Interrupt Interface ................................................................................................ 16.3.8 DTC Interface ...................................................................................................... 16.4 CAN Bus Interface ........................................................................................................... 16.5 Usage Notes ...................................................................................................................... 614 615 616 617 618 619 620 621 626 627 630 630 631 632 634 638 640 641 641 644 649 655 661 663 663 665 666 667 Section 17 A/D Converter................................................................................................. 671 17.1 Overview........................................................................................................................... 17.1.1 Features................................................................................................................ 17.1.2 Block Diagram..................................................................................................... 17.1.3 Pin Configuration ................................................................................................ 17.1.4 Register Configuration......................................................................................... 17.2 Register Descriptions........................................................................................................ 17.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 17.2.2 A/D Control/Status Register (ADCSR) ............................................................... 17.2.3 A/D Control Register (ADCR) ............................................................................ 17.2.4 Module Stop Control Register A (MSTPCRA) ................................................... Rev. 6.00 Feb 22, 2005 page xlviii of lx 671 671 672 673 674 675 675 676 679 680 17.3 Interface to Bus Master..................................................................................................... 17.4 Operation .......................................................................................................................... 17.4.1 Single Mode (SCAN = 0) .................................................................................... 17.4.2 Scan Mode (SCAN = 1)....................................................................................... 17.4.3 Input Sampling and A/D Conversion Time ......................................................... 17.4.4 External Trigger Input Timing............................................................................. 17.5 Interrupts........................................................................................................................... 17.6 Usage Notes ...................................................................................................................... 681 682 682 684 686 687 688 689 Section 18 D/A Converter................................................................................................. 695 18.1 Overview........................................................................................................................... 18.1.1 Features................................................................................................................ 18.1.2 Block Diagram..................................................................................................... 18.1.3 Input and Output Pins .......................................................................................... 18.1.4 Register Configuration......................................................................................... 18.2 Register Descriptions........................................................................................................ 18.2.1 D/A Data Registers 0, 1 (DADR0, DADR1) ....................................................... 18.2.2 D/A Control Register 01 (DACR01) ................................................................... 18.2.3 Module Stop Control Register A (MSTPCRA) ................................................... 18.3 Operation .......................................................................................................................... 695 695 696 697 697 698 698 698 700 701 703 703 703 704 706 707 708 708 710 711 712 713 714 716 717 719 720 721 721 Section 19 Motor Control PWM Timer ........................................................................ 19.1 Overview........................................................................................................................... 19.1.1 Features................................................................................................................ 19.1.2 Block Diagram..................................................................................................... 19.1.3 Pin Configuration ................................................................................................ 19.1.4 Register Configuration......................................................................................... 19.2 Register Descriptions........................................................................................................ 19.2.1 PWM Control Registers 1 and 2 (PWCR1, PWCR2) .......................................... 19.2.2 PWM Output Control Registers 1 and 2 (PWOCR1, PWOCR2) ........................ 19.2.3 PWM Polarity Registers 1 and 2 (PWPR1, PWPR2) .......................................... 19.2.4 PWM Counters 1 and 2 (PWCNT1, PWCNT2) .................................................. 19.2.5 PWM Cycle Registers 1 and 2 (PWCYR1, PWCYR2) ....................................... 19.2.6 PWM Duty Registers 1A, 1C, 1E, 1G (PWDTR1A, 1C, 1E, 1G) ....................... 19.2.7 PWM Buffer Registers 1A, 1C, 1E, 1G (PWBFR1A, 1C, 1E, 1G) ..................... 19.2.8 PWM Duty Registers 2A to 2H (PWDTR2A to PWDTR2H) ............................. 19.2.9 PWM Buffer Registers 2A to 2D (PWBFR2A to PWBFR2D) ........................... 19.2.10 Module Stop Control Register D (MSTPCRD) ................................................... 19.3 Bus Master Interface......................................................................................................... 19.3.1 16-Bit Data Registers........................................................................................... Rev. 6.00 Feb 22, 2005 page xlix of lx 19.3.2 8-Bit Data Registers............................................................................................. 19.4 Operation .......................................................................................................................... 19.4.1 PWM Channel 1 Operation.................................................................................. 19.4.2 PWM Channel 2 Operation.................................................................................. 19.5 Usage Note ....................................................................................................................... 721 722 722 723 725 727 727 727 729 730 730 730 731 Section 20 RAM .................................................................................................................. 20.1 Overview........................................................................................................................... 20.1.1 Block Diagram..................................................................................................... 20.1.2 Register Configuration......................................................................................... 20.2 Register Descriptions........................................................................................................ 20.2.1 System Control Register (SYSCR)...................................................................... 20.3 Operation .......................................................................................................................... 20.4 Usage Notes ...................................................................................................................... 21A.1 Overview....................................................................................................................... 21A.1.1 Block Diagram.............................................................................................. 21A.1.2 Register Configuration ................................................................................. Register Descriptions .................................................................................................... 21A.2.1 Mode Control Register (MDCR) .................................................................. Operation....................................................................................................................... Flash Memory Overview............................................................................................... 21A.4.1 Features ........................................................................................................ 21A.4.2 Block Diagram.............................................................................................. 21A.4.3 Mode Transitions.......................................................................................... 21A.4.4 On-Board Programming Modes ................................................................... 21A.4.5 Flash Memory Emulation in RAM ............................................................... 21A.4.6 Differences between Boot Mode and User Program Mode .......................... 21A.4.7 Block Configuration ..................................................................................... Pin Configuration .......................................................................................................... Register Configuration .................................................................................................. Register Descriptions .................................................................................................... 21A.7.1 Flash Memory Control Register 1 (FLMCR1) ............................................. 21A.7.2 Flash Memory Control Register 2 (FLMCR2) ............................................. 21A.7.3 Erase Block Register 1 (EBR1) .................................................................... 21A.7.4 Erase Block Register 2 (EBR2) .................................................................... 21A.7.5 RAM Emulation Register (RAMER) ........................................................... 21A.7.6 Flash Memory Power Control Register (FLPWCR)..................................... On-Board Programming Modes .................................................................................... Section 21A ROM (H8S/2636 Group).......................................................................... 733 733 733 733 734 734 734 737 737 738 739 740 742 743 744 745 746 747 747 750 751 751 752 753 754 21A.2 21A.3 21A.4 21A.5 21A.6 21A.7 21A.8 Rev. 6.00 Feb 22, 2005 page l of lx 21A.9 21A.10 21A.11 21A.12 21A.13 21A.14 21A.15 21A.16 21A.8.1 Boot Mode.................................................................................................... 21A.8.2 User Program Mode ..................................................................................... Flash Memory Programming/Erasing ........................................................................... 21A.9.1 Program Mode .............................................................................................. 21A.9.2 Program-Verify Mode .................................................................................. 21A.9.3 Erase Mode................................................................................................... 21A.9.4 Erase-Verify Mode ....................................................................................... Protection ...................................................................................................................... 21A.10.1 Hardware Protection ..................................................................................... 21A.10.2 Software Protection ...................................................................................... 21A.10.3 Error Protection ............................................................................................ Flash Memory Emulation in RAM................................................................................ Interrupt Handling when Programming/Erasing Flash Memory ................................... Flash Memory Programmer Mode ................................................................................ 21A.13.1 Socket Adapter and Memory Map................................................................ 21A.13.2 Programmer Mode Operation ....................................................................... 21A.13.3 Memory Read Mode..................................................................................... 21A.13.4 Auto-Program Mode..................................................................................... 21A.13.5 Auto-Erase Mode.......................................................................................... 21A.13.6 Status Read Mode......................................................................................... 21A.13.7 Status Polling................................................................................................ 21A.13.8 Programmer Mode Transition Time ............................................................. 21A.13.9 Notes on Memory Programming .................................................................. Flash Memory and Power-Down States ........................................................................ 21A.14.1 Notes on Power-Down States ....................................................................... Flash Memory Programming and Erasing Precautions ................................................. Note on Switching from F-ZTAT Version to Mask ROM Version .............................. 755 759 761 763 764 768 769 771 771 772 772 774 776 777 777 778 779 783 785 787 788 788 789 790 790 791 796 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group).... 797 21B.1 Overview....................................................................................................................... 21B.1.1 Block Diagram.............................................................................................. 21B.1.2 Register Configuration ................................................................................. Register Descriptions .................................................................................................... 21B.2.1 Mode Control Register (MDCR) .................................................................. Operation....................................................................................................................... Flash Memory Overview............................................................................................... 21B.4.1 Features ........................................................................................................ 21B.4.2 Block Diagram.............................................................................................. 21B.4.3 Mode Transitions.......................................................................................... 21B.4.4 On-Board Programming Modes ................................................................... 797 797 798 798 798 798 801 801 802 803 804 21B.2 21B.3 21B.4 Rev. 6.00 Feb 22, 2005 page li of lx 21B.5 21B.6 21B.7 21B.8 21B.9 21B.10 21B.11 21B.12 21B.13 21B.14 21B.15 21B.16 21B.4.5 Flash Memory Emulation in RAM ............................................................... 21B.4.6 Differences between Boot Mode and User Program Mode .......................... 21B.4.7 Block Configuration ..................................................................................... Pin Configuration .......................................................................................................... Register Configuration .................................................................................................. Register Descriptions .................................................................................................... 21B.7.1 Flash Memory Control Register 1 (FLMCR1) ............................................. 21B.7.2 Flash Memory Control Register 2 (FLMCR2) ............................................. 21B.7.3 Erase Block Register 1 (EBR1) .................................................................... 21B.7.4 Erase Block Register 2 (EBR2) .................................................................... 21B.7.5 RAM Emulation Register (RAMER) ........................................................... 21B.7.6 Flash Memory Power Control Register (FLPWCR)..................................... On-Board Programming Modes .................................................................................... 21B.8.1 Boot Mode.................................................................................................... 21B.8.2 User Program Mode ..................................................................................... Programming/Erasing Flash Memory ........................................................................... 21B.9.1 Program Mode .............................................................................................. 21B.9.2 Program-Verify Mode .................................................................................. 21B.9.3 Erase Mode................................................................................................... 21B.9.4 Erase-Verify Mode ....................................................................................... Protection ...................................................................................................................... 21B.10.1 Hardware Protection ..................................................................................... 21B.10.2 Software Protection ...................................................................................... 21B.10.3 Error Protection ............................................................................................ Flash Memory Emulation in RAM................................................................................ Interrupt Handling when Programming/Erasing Flash Memory ................................... Flash Memory Programmer Mode ................................................................................ 21B.13.1 Socket Adapter and Memory Map................................................................ 21B.13.2 Programmer Mode Operation ....................................................................... 21B.13.3 Memory Read Mode..................................................................................... 21B.13.4 Auto-Program Mode..................................................................................... 21B.13.5 Auto-Erase Mode.......................................................................................... 21B.13.6 Status Read Mode......................................................................................... 21B.13.7 Status Polling................................................................................................ 21B.13.8 Programmer Mode Transition Time ............................................................. 21B.13.9 Notes on Memory Programming .................................................................. Flash Memory and Power-Down States ........................................................................ 21B.14.1 Notes on Power-Down States ....................................................................... Flash Memory Programming and Erasing Precautions ................................................. Note on Switching from F-ZTAT Version to Mask ROM Version .............................. 806 807 808 809 810 811 811 814 815 815 816 818 819 820 824 826 828 829 833 833 835 835 836 837 839 841 841 842 843 844 848 850 852 853 853 854 855 856 856 862 Rev. 6.00 Feb 22, 2005 page lii of lx Section 21C ROM (H8S/2635 Group) .......................................................................... 863 21C.1 Overview....................................................................................................................... 21C.1.1 Block Diagram.............................................................................................. 21C.1.2 Register Configuration ................................................................................. Register Descriptions .................................................................................................... 21C.2.1 Mode Control Register (MDCR) .................................................................. Operation....................................................................................................................... Flash Memory Overview............................................................................................... 21C.4.1 Features ........................................................................................................ 21C.4.2 Block Diagram.............................................................................................. 21C.4.3 Mode Transitions.......................................................................................... 21C.4.4 On-Board Programming Modes ................................................................... 21C.4.5 Flash Memory Emulation in RAM ............................................................... 21C.4.6 Differences between Boot Mode and User Program Mode .......................... 21C.4.7 Block Configuration ..................................................................................... Pin Configuration .......................................................................................................... Register Configuration .................................................................................................. Register Descriptions .................................................................................................... 21C.7.1 Flash Memory Control Register 1 (FLMCR1) ............................................. 21C.7.2 Flash Memory Control Register 2 (FLMCR2) ............................................. 21C.7.3 Erase Block Register 1 (EBR1) .................................................................... 21C.7.4 Erase Block Register 2 (EBR2) .................................................................... 21C.7.5 RAM Emulation Register (RAMER) ........................................................... 21C.7.6 Flash Memory Power Control Register (FLPWCR)..................................... On-Board Programming Modes .................................................................................... 21C.8.1 Boot Mode.................................................................................................... 21C.8.2 User Program Mode ..................................................................................... Programming/Erasing Flash Memory ........................................................................... 21C.9.1 Program Mode .............................................................................................. 21C.9.2 Program-Verify Mode .................................................................................. 21C.9.3 Erase Mode................................................................................................... 21C.9.4 Erase-Verify Mode ....................................................................................... Protection ...................................................................................................................... 21C.10.1 Hardware Protection ..................................................................................... 21C.10.2 Software Protection ...................................................................................... 21C.10.3 Error Protection ............................................................................................ Flash Memory Emulation in RAM................................................................................ Interrupt Handling when Programming/Erasing Flash Memory ................................... Flash Memory Programmer Mode ................................................................................ 21C.13.1 Socket Adapter and Memory Map................................................................ 863 863 864 864 864 864 867 867 868 869 870 872 873 874 875 876 877 877 880 881 881 882 884 885 886 890 892 894 895 899 899 901 901 902 903 905 907 907 908 21C.2 21C.3 21C.4 21C.5 21C.6 21C.7 21C.8 21C.9 21C.10 21C.11 21C.12 21C.13 Rev. 6.00 Feb 22, 2005 page liii of lx 21C.13.2 Programmer Mode Operation ....................................................................... 21C.13.3 Memory Read Mode..................................................................................... 21C.13.4 Auto-Program Mode..................................................................................... 21C.13.5 Auto-Erase Mode.......................................................................................... 21C.13.6 Status Read Mode......................................................................................... 21C.13.7 Status Polling................................................................................................ 21C.13.8 Programmer Mode Transition Time ............................................................. 21C.13.9 Notes on Memory Programming .................................................................. 21C.14 Flash Memory and Power-Down States ........................................................................ 21C.14.1 Notes on Power-Down States ....................................................................... 21C.15 Flash Memory Programming and Erasing Precautions ................................................. 21C.16 Note on Switching from F-ZTAT Version to Mask ROM Version .............................. 909 910 914 916 918 919 919 920 921 922 922 928 Section 22A Clock Pulse Generator (H8S/2636 Group, H8S/2638 Group, H8S/2630 Group) ....................................................................................... 929 22A.1 Overview....................................................................................................................... 22A.1.1 Block Diagram.............................................................................................. 22A.1.2 Register Configuration ................................................................................. Register Descriptions .................................................................................................... 22A.2.1 System Clock Control Register (SCKCR).................................................... 22A.2.2 Low-Power Control Register (LPWRCR).................................................... Oscillator....................................................................................................................... 22A.3.1 Connecting a Crystal Resonator ................................................................... 22A.3.2 External Clock Input..................................................................................... PLL Circuit.................................................................................................................... Medium-Speed Clock Divider....................................................................................... Bus Master Clock Selection Circuit .............................................................................. Subclock Oscillator ....................................................................................................... Subclock Waveform Generation Circuit ....................................................................... Note on Crystal Resonator ............................................................................................ 929 929 930 930 930 931 932 932 935 937 938 938 938 939 939 22A.2 22A.3 22A.4 22A.5 22A.6 22A.7 22A.8 22A.9 Section 22B Clock Pulse Generator (H8S/2639 Group, H8S/2635 Group)....... 941 22B.1 Overview....................................................................................................................... 22B.1.1 Block Diagram.............................................................................................. 22B.1.2 Register Configuration ................................................................................. Register Descriptions .................................................................................................... 22B.2.1 System Clock Control Register (SCKCR).................................................... 22B.2.2 Low-Power Control Register (LPWRCR).................................................... Oscillator....................................................................................................................... 22B.3.1 Connecting a Crystal Resonator ................................................................... 941 941 942 942 942 943 944 944 22B.2 22B.3 Rev. 6.00 Feb 22, 2005 page liv of lx 22B.4 22B.5 22B.6 22B.7 22B.8 22B.3.2 External Clock Input..................................................................................... PLL Circuit.................................................................................................................... Medium-Speed Clock Divider....................................................................................... Bus Master Clock Selection Circuit .............................................................................. Subclock Divider........................................................................................................... Note on Resonator......................................................................................................... 947 949 949 949 950 950 Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] .............................................................................................. 951 23A.1 23A.2 Overview....................................................................................................................... 23A.1.1 Register Configuration ................................................................................. Register Descriptions .................................................................................................... 23A.2.1 Standby Control Register (SBYCR) ............................................................. 23A.2.2 System Clock Control Register (SCKCR).................................................... 23A.2.3 Low-Power Control Register (LPWRCR).................................................... 23A.2.4 Timer Control/Status Register (TCSR)......................................................... 23A.2.5 Module Stop Control Register (MSTPCR)................................................... Medium-Speed Mode.................................................................................................... Sleep Mode ................................................................................................................... 23A.4.1 Sleep Mode................................................................................................... 23A.4.2 Exiting Sleep Mode ...................................................................................... Module Stop Mode........................................................................................................ 23A.5.1 Module Stop Mode ....................................................................................... 23A.5.2 Usage Notes.................................................................................................. Software Standby Mode ................................................................................................ 23A.6.1 Software Standby Mode ............................................................................... 23A.6.2 Clearing Software Standby Mode................................................................. 23A.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode............................................................................................... 23A.6.4 Software Standby Mode Application Example............................................. 23A.6.5 Usage Notes.................................................................................................. Hardware Standby Mode............................................................................................... 23A.7.1 Hardware Standby Mode .............................................................................. 23A.7.2 Hardware Standby Mode Timing ................................................................. Clock Output Disabling Function............................................................................... 951 955 956 956 957 959 959 960 962 963 963 963 964 964 965 966 966 966 967 968 969 969 969 970 971 23A.3 23A.4 23A.5 23A.6 23A.7 23A.8 Rev. 6.00 Feb 22, 2005 page lv of lx Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF, HD6432635F, HD64F2635F, HD6432634F] ............................................................................................... 973 23B.1 Overview....................................................................................................................... 973 23B.1.1 Register Configuration ................................................................................. 979 23B.2 Register Descriptions .................................................................................................... 979 23B.2.1 Standby Control Register (SBYCR) ............................................................. 979 23B.2.2 System Clock Control Register (SCKCR).................................................... 981 23B.2.3 Low-Power Control Register (LPWRCR).................................................... 983 23B.2.4 Timer Control/Status Register (TCSR)......................................................... 985 23B.2.5 Module Stop Control Register (MSTPCR)................................................... 987 23B.3 Medium-Speed Mode.................................................................................................... 988 23B.4 Sleep Mode ................................................................................................................... 989 23B.4.1 Sleep Mode................................................................................................... 989 23B.4.2 Exiting Sleep Mode ...................................................................................... 989 23B.5 Module Stop Mode........................................................................................................ 990 23B.5.1 Module Stop Mode ....................................................................................... 990 23B.5.2 Usage Notes.................................................................................................. 992 23B.6 Software Standby Mode ................................................................................................ 992 23B.6.1 Software Standby Mode ............................................................................... 992 23B.6.2 Clearing Software Standby Mode................................................................. 993 23B.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode............................................................................................... 993 23B.6.4 Software Standby Mode Application Example............................................. 995 23B.6.5 Usage Notes.................................................................................................. 996 23B.7 Hardware Standby Mode............................................................................................... 996 23B.7.1 Hardware Standby Mode .............................................................................. 996 23B.7.2 Hardware Standby Mode Timing ................................................................. 997 23B.8 Watch Mode (U-Mask, W-Mask Version, H8S/2635 Group Only).............................. 997 23B.8.1 Watch Mode ................................................................................................. 997 23B.8.2 Exiting Watch Mode..................................................................................... 998 23B.8.3 Notes............................................................................................................. 998 23B.9 Subsleep Mode (U-Mask, W-Mask Version, H8S/2635 Group Only).......................... 999 23B.9.1 Subsleep Mode ............................................................................................. 999 23B.9.2 Exiting Subsleep Mode................................................................................. 999 23B.10 Subactive Mode (U-Mask, W-Mask Version, H8S/2635 Group Only) ...................... 1000 23B.10.1 Subactive Mode .......................................................................................... 1000 Rev. 6.00 Feb 22, 2005 page lvi of lx 23B.10.2 Exiting Subactive Mode ............................................................................. 23B.11 Direct Transitions (U-Mask, W-Mask Version, H8S/2635 Group Only).................... 23B.11.1 Overview of Direct Transitions .................................................................. 23B.12 Clock Output Disabling Function............................................................................. 23B.13 Usage Notes ................................................................................................................ 1000 1001 1001 1002 1003 1005 1005 1005 1006 1007 1011 1016 1017 1018 1020 1020 1021 1022 1028 1034 1035 1036 1038 1038 1039 1040 1046 1052 1053 1054 1056 1056 1057 1058 1064 1070 1071 1072 Section 24 Electrical Characteristics ........................................................................... 24.1 H8S/2636 Group Electrical Characteristics .................................................................... 24.1.1 Absolute Maximum Ratings .............................................................................. 24.1.2 Power Supply Voltage and Operating Frequency Range................................... 24.1.3 DC Characteristics ............................................................................................. 24.1.4 AC Characteristics ............................................................................................. 24.1.5 A/D Conversion Characteristics ........................................................................ 24.1.6 D/A Conversion Characteristics ........................................................................ 24.1.7 Flash Memory Characteristics ........................................................................... 24.2 H8S/2638 Group Electrical Characteristics .................................................................... 24.2.1 Absolute Maximum Ratings .............................................................................. 24.2.2 Power Supply Voltage and Operating Frequency Range................................... 24.2.3 DC Characteristics ............................................................................................. 24.2.4 AC Characteristics ............................................................................................. 24.2.5 A/D Conversion Characteristics ........................................................................ 24.2.6 D/A Conversion Characteristics ........................................................................ 24.2.7 Flash Memory Characteristics ........................................................................... 24.3 H8S/2639 Group, H8S/2635 Group Electrical Characteristics....................................... 24.3.1 Absolute Maximum Ratings .............................................................................. 24.3.2 Power Supply Voltage and Operating Frequency Range................................... 24.3.3 DC Characteristics ............................................................................................. 24.3.4 AC Characteristics ............................................................................................. 24.3.5 A/D Conversion Characteristics ........................................................................ 24.3.6 D/A Conversion Characteristics ........................................................................ 24.3.7 Flash Memory Characteristics ........................................................................... 24.4 H8S/2630 Group Electrical Characteristics .................................................................... 24.4.1 Absolute Maximum Ratings .............................................................................. 24.4.2 Power Supply Voltage and Operating Frequency Range................................... 24.4.3 DC Characteristics ............................................................................................. 24.4.4 AC Characteristics ............................................................................................. 24.4.5 A/D Conversion Characteristics ........................................................................ 24.4.6 D/A Conversion Characteristics ........................................................................ 24.4.7 Flash Memory Characteristics ........................................................................... Rev. 6.00 Feb 22, 2005 page lvii of lx 24.5 Operation Timing............................................................................................................ 24.5.1 Clock Timing ..................................................................................................... 24.5.2 Control Signal Timing ....................................................................................... 24.5.3 Bus Timing ........................................................................................................ 24.5.4 On-Chip Supporting Module Timing................................................................. 24.6 Usage Note ..................................................................................................................... 1074 1074 1075 1076 1080 1084 Appendix A Instruction Set............................................................................................ 1085 A.1 A.2 A.3 A.4 A.5 A.6 Instruction List................................................................................................................ Instruction Codes ............................................................................................................ Operation Code Map....................................................................................................... Number of States Required for Instruction Execution.................................................... Bus States during Instruction Execution......................................................................... Condition Code Modification ......................................................................................... 1085 1109 1124 1128 1142 1156 Appendix B Internal I/O Register................................................................................. 1162 B.1 B.2 Address ........................................................................................................................... 1162 Functions ........................................................................................................................ 1184 Appendix C I/O Port Block Diagrams ........................................................................ 1448 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 C.11 C.12 Port 1 Block Diagrams.................................................................................................... Port 3 Block Diagrams.................................................................................................... Port 4 Block Diagram ..................................................................................................... Port 9 Block Diagram ..................................................................................................... Port A Block Diagram .................................................................................................... Port B Block Diagram..................................................................................................... Port C Block Diagram..................................................................................................... Port D Block Diagram .................................................................................................... Port E Block Diagram..................................................................................................... Port F Block Diagrams ................................................................................................... Port H Block Diagram .................................................................................................... Port J Block Diagram...................................................................................................... 1448 1454 1460 1461 1462 1466 1467 1468 1469 1470 1476 1477 Appendix D Pin States..................................................................................................... 1478 D.1 Port States in Each Mode................................................................................................ 1478 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode............................................................................................ 1481 Rev. 6.00 Feb 22, 2005 page lviii of lx Appendix F Product Code Lineup............................................................................... 1482 Appendix G Package Dimensions................................................................................ 1484 Rev. 6.00 Feb 22, 2005 page lix of lx Rev. 6.00 Feb 22, 2005 page lx of lx Section 1 Overview Section 1 Overview 1.1 Overview The H8S/2636, H8S/2638, H8S/2639, H8S/2630, H8S/2635, and H8S/2634 are microcomputers (MCUs: microcomputer units), built around the H8S/2600 CPU, employing Renesas Technology's proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. On-chip peripheral functions required for system configuration include data transfer controller (DTC) bus masters, ROM and RAM memory, a16-bit timer-pulse unit (TPU), programmable pulse generator (PPG), motor control PWM timer (PWM) watchdog timer (WDT), serial communication interface (SCI), A/D converter, D/A converter, controller area network (HCAN) and I/O ports. An I2C bus interface (IIC) is available as an option in the H8S/2638, H8S/2639, and H8S/2630. On-chip ROM is available as 128-kbyte, 192-kbyte, 256-kbyte, and 384-kbyte flash memory (FZTATTM* version), and as 128-kbyte, 192-kbyte, 256-kbyte, and 384-kbyte mask ROM. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching has been speeded up, and processing speed increased. Four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or external expansion mode. Subclock (32 kHz oscillation) functions are available in the U-mask and W-mask versions only. These functions cannot be used with the other versions. The features of the H8S/2636, H8S/2638, H8S/2639, H8S/2630, H8S/2635, and H8S/2634 are shown in table 1-1. Notes: The H8S/2635 and H8S/2634 are not equipped with a DTC, a PPG, or a D/A converter. * F-ZTAT is a trademark of Renesas Technology Corp. Rev. 6.00 Feb 22, 2005 page 1 of 1484 REJ09B0103-0600 Section 1 Overview Table 1-1 Item CPU Overview Specification * General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * High-speed operation suitable for realtime control Maximum clock rate: 20 MHz High-speed arithmetic operations 8/16/32-bit register-register add/subtract 16 x 16-bit register-register multiply 16 x 16 + 42-bit multiply and accumulate 32 / 16-bit register-register divide * Sixty-nine basic instructions 8/16/32-bit move/arithmetic and logic instructions Unsigned/signed multiply and divide instructions Multiply-and accumulate instruction Powerful bit-manipulation instructions * CPU operating modes Advanced mode: 16-Mbyte address space Address space divided into 8 areas, with bus specifications settable independently for each area Choice of 8-bit or 16-bit access space for each area 2-state or 3-state access space can be designated for each area Number of program wait states can be set for each area Direct connection to burst ROM supported Supports debugging functions by means of PC break interrupts Two break channels : 50 ns : 200 ns : 200 ns : 1000 ns Instruction set suitable for high-speed operation Bus controller * * * * * PC break controller * (This function is not * implemented in the H8S/2635 Group) Data transfer * controller (DTC) * (This function is not implemented in the * H8S/2635 Group) * Can be activated by internal interrupt or software Multiple transfers or multiple types of transfer possible for one activation source Transfer possible in repeat mode, block transfer mode, etc. Request can be sent to CPU for interrupt that activated DTC Rev. 6.00 Feb 22, 2005 page 2 of 1484 REJ09B0103-0600 Section 1 Overview Item 16-bit timer-pulse unit (TPU) Specification * * * Programmable pulse generator (PPG) (This function is not implemented in the H8S/2635 Group) Watchdog timer (WDT) 2 channels Motor control PWM timer (PWM) * * * * * * * * * * * Serial communication interface (SCI) 3 channels (SCI0 to SCI2) Controller area network (HCAN) 2 channels (The H8S/2635 Group has one HCAN channel) A/D converter * * * * * * 6-channel 16-bit timer on-chip Pulse I/O processing capability for up to 16 pins' Automatic 2-phase encoder count capability Maximum 8-bit pulse output possible with TPU as time base Output trigger selectable in 4-bit groups Non-overlap margin can be set Direct output or inverse output setting possible Watchdog timer or interval timer selectable Operation using sub-clock supported (WDT1 only)* Maximum of 16 10-bit PWM outputs Eight outputs with two channels each built in Duty settable between 0% and 100% Automatic transfer of buffer register data supported Settable to any one of 5 operating speeds Asynchronous mode or synchronous mode selectable Multiprocessor communication function Smart card interface function CAN: Ver. 2.0B compliant Buffer size: 15 transmit/receive messages, transmit only one message Filtering of receive messages * * * * * * Resolution: 10 bits Input: 12 channels High-speed conversion: 13.3 s minimum conversion time (at 20 MHz operation) Single or scan mode selectable Sample and hold circuit A/D conversion can be activated by external trigger or timer trigger Resolution: 8 bits Output: 2 channels D/A converter * (This function is not * implemented in the H8S/2635 Group) Rev. 6.00 Feb 22, 2005 page 3 of 1484 REJ09B0103-0600 Section 1 Overview Item I/O ports Memory Specification * * * 72 I/O pins, 12 input-only pins Flash memory or mask ROM High-speed static RAM ROM 128 kbytes 256 kbytes 384 kbytes 192 kbytes 128 kbytes 6 kbytes RAM 4 kbytes 16 kbytes Product Name H8S/2636 H8S/2638 H8S/2639 H8S/2630* H8S/2635 H8S/2634 * * * Power-down states * * * * * * Operating modes Note: * Under development 49 internal interrupt sources (45 sources in H8S/2635) Eight priority levels settable Medium-speed mode Sleep mode Module-stop mode Software standby mode Hardware standby mode Sub-clock operation* (subactive mode, subsleep mode, watch mode) External Data Bus Mode 4 5 6 7 CPU Operating Mode Advanced Description On-chip ROM disabled expansion mode On-chip ROM disabled expansion mode On-chip ROM enabled expansion mode Single-chip mode On-Chip ROM Disabled Disabled Enabled Enabled Initial Value 16 bits 8 bits 8 bits -- Maximum Value 16 bits 16 bits 16 bits -- 5QRI 0QRI Interrupt controller Seven external interrupt pins (NMI, to ) Four MCU operating modes Rev. 6.00 Feb 22, 2005 page 4 of 1484 REJ09B0103-0600 Section 1 Overview Item Clock pulse generator Specification * * On-chip PLL circuit (x1, x2, x4) Input clock frequency H8S/2636, H8S/2638, H8S/2630: 4 to 20 MHz H8S/2639, H8S/2635, H8S/2634: 4 to 5 MHz I2C bus interface (IIC) x2 channel (Option) (Only for the H8S/2638, H8S/2639, and H8S/2630) Packages Product lineup Mask ROM Version HD6432636F HD6432636UF (U-Mask Version) HD6432638F HD6432638UF (U-Mask Version) HD6432638WF (W-Mask Version) HD6432639UF (U-Mask Version) HD6432639WF (W-Mask Version) HD6432630F HD6432630UF (U-Mask Version) HD6432630WF (W-Mask Version) HD6432635F HD6432634F * * * * Conforms to the I2C bus interface type advocated by Philips Single master mode/slave mode Possible to determine arbitration lost conditions Supports two slave addresses * 128-pin plastic QFP (FP-128B) Model Name F-ZTAT Version HD64F2636F HD64F2636UF (U-Mask Version) HD64F2638F HD64F2638UF (U-Mask Version) HD64F2638WF (W-Mask Version) HD64F2639UF (U-Mask Version) HD64F2639WF (W-Mask Version) HD64F2630F HD64F2630UF (U-Mask Version) HD64F2630WF (W-Mask Version) HD64F2635F -- Subclock Functions No Yes No Yes Yes Yes Yes No Yes Yes Yes Yes I C bus interface No No Yes No Yes No No Yes No No 192 k/ 6k 128 k/ 6k 384 k/ 16 k 2 ROM/ RAM (Bytes) Packages 128 k/ 4k FP-128B 256 k/ 16 k Note: * Under development Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available only in the U-mask and W-mask versions, and H8S/2635 Group, but are not available in the other versions. Rev. 6.00 Feb 22, 2005 page 5 of 1484 REJ09B0103-0600 Section 1 Overview 1.2 Internal Block Diagram Figure 1-1 (a) shows an internal block diagram of the H8S/2636. PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Port D Port E Interrupt controller PC break controller Port F TPU D/A converter A/D converter PJ0/PWM2A PJ1/PWM2B PJ2/PWM2C PJ3/PWM2D PJ4/PWM2E PJ5/PWM2F PJ6/PWM2G PJ7/PWM2H Port J PPG HCAN x 2 channels P93/AN11 P92/AN10 P91/AN9 P90/AN8 Port 1 Port 4 HRxD0 HTxD0 HRxD1 HTxD1 Vref AVCC AVSS P47 / AN7/ DA1 P46 / AN6/ DA0 P45 / AN5 P44 / AN4 P43 / AN3 P42 / AN2 P41 / AN1 P40 / AN0 P10 / PO8/TIOCA0 /A20 P11 / PO9/TIOCB0 /A21 P12 / PO10/ TIOCC0 / TCLKA/A22 P13 / PO11/ TIOCD0 / TCLKB/A23 P14 / PO12/ TIOCA1/IRQ0 P15 / PO13/ TIOCB1 / TCLKC P16 / PO14/ TIOCA2/IRQ1 P17 / PO15/ TIOCB2 / TCLKD Notes: 1. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask version. These functions cannot be used with the other versions. See section 22A.7, Subclock Oscillator, for the method of fixing pins OSC1 and OSC2. 2. The FWE pin only applies to the flash memory version. The FWE pin is a NC pin in the mask ROM versions. In the mask ROM version, the FWE pin must be left open or be connected to Vss. Figure 1-1 (a) Internal Block Diagram of H8S/2636 Rev. 6.00 Feb 22, 2005 page 6 of 1484 REJ09B0103-0600 PWMVCC PWMVCC PWMVSS PWMVSS PWMVSS Port 9 Port 3 PH0/PWM1A PH1/PWM1B PH2/PWM1C PH3/PWM1D PH4/PWM1E PH5/PWM1F PH6/PWM1G PH7/PWM1H WDT x 2 channels Port H RAM SCI x 3 channels Motor control PWM timer Port C PF7/ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF0/IRQ2 Peripheral data bus DTC Peripheral address bus EXTAL XTAL PLLCAP STBY RES NMI FWE*2 H8S/2600 CPU Internal data bus Internal address bus Clock pulse generator VCL MD2 MD1 MD0 OSC2*1 OSC1*1 PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 Bus controller Port A PLL PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3 / A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 ROM (mask ROM, flash memory) Port B P35/SCK1/IRQ5 P34/RxD1 P33/TxD1 P32/SCK0/IRQ4 P31/RxD0 P30/TxD0 Section 1 Overview Figure 1-1 (b) shows an internal block diagram of the H8S/2638, H8S/2639, and H8S/2630. PD7 /D15 PD6 /D14 PD5 /D13 PD4 /D12 PD3 /D11 PD2 /D10 PD1 /D9 PD0 /D8 PE7 /D7 PE6 /D6 PE5/ D5 PE4/ D4 PE3/ D3 PE2/ D2 PE1/ D1 PE0/ D0 VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Port D Port E Clock pulse generator Bus controller TPU D/A converter A/D converter PJ0/PWM2A PJ1/PWM2B PJ2/PWM2C PJ3/PWM2D PJ4/PWM2E PJ5/PWM2F PJ6/PWM2G PJ7/PWM2H Port J PPG HCAN x 2 channels P93/AN11 P92/AN10 P91/AN9 P90/AN8 Port 1 Port 4 HRxD0 HTxD0 HRxD1 HTxD1 Vref AVCC AVSS P47/AN7/DA1 P46/AN6/DA0 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 Notes: 1. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions. These functions cannot be used with the other versions. See section 22A.7, Subclock Oscillator, for the method of fixing pins OSC1 and OSC2. The H8S/2639 has no OSC1 and OSC2 pins. 2. These pins are used for the I2C bus interface. The I2C bus interface is available as an option. The product equipped with the I2C bus interface is the W-mask version. 3. The FWE pin is for compatibility with the flash memory version. The FWE pin is a NC pin in the mask ROM versions. In the mask ROM version, the FWE pin must be left open or be connected to Vss. Figure 1-1 (b) Internal Block Diagram of H8S/2638, H8S/2639, and H8S/2630 P10/PO8/TIOCA0/A20 P11/PO9/TIOCB0/A21 P12/PO10/TIOCC0/TCLKA/A22 P13/PO11/TIOCD0/TCLKB/A23 P14/PO12/TIOCA1/IRQ0 P15/PO13/TIOCB1/TCLKC P16/PO14/TIOCA2/IRQ1 P17/PO15/TIOCB2/TCLKD PWMVCC PWMVCC PWMVSS PWMVSS PWMVSS Rev. 6.00 Feb 22, 2005 page 7 of 1484 REJ09B0103-0600 Port 9 Port 3 PH0/PWM1A PH1/PWM1B PH2/PWM1C PH3/PWM1D PH4/PWM1E PH5/PWM1F PH6/PWM1G PH7/PWM1H WDT x 2 channels Port H RAM I2C bus interface (option) SCI x 3 channels Motor control PWM timer Port C PF7/ PF6/ AS PF5/ RD PF4/ HWR PF3/ LWR/ADTRG/IRQ3 PF0/IRQ2 PC break controller Port F Peripheral data bus Interrupt controller DTC Peripheral address bus EXTAL XTAL PLLCAP STBY RES NMI FWE*3 H8S/2600 CPU Internal data bus Internal address bus VCL MD2 MD1 MD0 OSC2*1 OSC1*1 PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 Port A PLL PB7/ A15/TIOCB5 PB6/ A14/TIOCA5 PB5/ A13/TIOCB4 PB4/ A12/TIOCA4 PB3 / A11/TIOCD3 PB2/ A10/TIOCC3 PB1/ A9/TIOCB3 PB0/ A8/TIOCA3 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 ROM (mask ROM, flash memory) Port B P35/SCK1/SCL0*2/IRQ5 P34/RxD1/SDA0*2 P33/TxD1/SCL1*2 P32/SCK0/SDA1*2/IRQ4 P31/RxD0 P30/TxD0 Section 1 Overview Figure 1-1 (c) shows an internal block diagram of the H8S/2635 Group. PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Port D VCL MD2 MD1 MD0 NC*2 EXTAL XTAL Internal address bus Port E PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3 / A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PLLCAP PLLVSS STBY RES NMI FWE*1 Clock pulse generator PLL Internal data bus H8S/2600 CPU Bus controller HCAN x 1 channel SCI x 3 channels Port J PJ0/PWM2A PJ1/PWM2B PJ2/PWM2C PJ3/PWM2D PJ4/PWM2E PJ5/PWM2F PJ6/PWM2G PJ7/PWM2H TPU Port 9 Port 3 PH0/PWM1A PH1/PWM1B PH2/PWM1C PH3/PWM1D PH4/PWM1E PH5/PWM1F PH6/PWM1G PH7/PWM1H Motor control PWM timer Port H RAM WDT x 2 channels P35/SCK1/IRQ5 P34/RxD1 P33/TxD1 P32/SCK0/IRQ4 P31/RxD0 P30/TxD0 Port C PF7/ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF0/IRQ2 ROM (mask ROM, flash memory) Peripheral data bus Interrupt controller Port F Peripheral address bus Port B Port A A/D converter P93/AN11 P92/AN10 P91/AN9 P90/AN8 Port 1 Port 4 P47/AN7 P46/AN6 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 P10/TIOCA0/A20 P11/TIOCB0/A21 P12/TIOCC0/TCLKA/A22 P13/TIOCD0/TCLKB/A23 P14/TIOCA1/IRQ0 P15/TIOCB1/TCLKC P16/TIOCA2/IRQ1 P17/TIOCB2/TCLKD Notes: 1. The FWE pin is for compatibility with the flash memory version. The FWE pin is a NC pin in the mask ROM versions. In the mask ROM version, the FWE pin must be left open or be connected to Vss. 2. The NC pin should be left open. Figure 1-1 (c) Internal Block Diagram of H8S/2635 Group Rev. 6.00 Feb 22, 2005 page 8 of 1484 REJ09B0103-0600 PWMVCC PWMVCC PWMVSS PWMVSS PWMVSS HRxD HTxD Vref AVCC AVSS Section 1 Overview 1.3 1.3.1 Pin Description Pin Arrangement Figure 1-2 shows the pin arrangement of the H8S/2636, figure 1-3 shows the pin arrangement of the H8S/2638 and H8S/2630, figure 1-4 shows the pin arrangement of the H8S/2639, and figure 1-5 shows the pin arrangement of the H8S/2635 Group. Vref AVCC NC VSS HRxD0 HTxD0 P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2/IRQ1 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1/IRQ0 P13/PO11/TIOCD0/TCLKB/A23 P12/PO10/TIOCC0/TCLKA/A22 P11/PO9/TIOCB0/A21 P10/PO8/TIOCA0/A20 PF7/ STBY 3 FWE* 0.1 F *1 PLLVSS VSS PLLCAP NMI RES P35/SCK1/IRQ5 P34/RxD1 P33/TxD1 P32/SCK0/IRQ4 VSS 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VSS P31/RxD0 P30/TxD0 EXTAL VSS XTAL VCL VCC VCC 2 OSC1* 2 OSC2* VCC VCC NC NC PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 VCC PD0/D8 VSS PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 VSS VSS HRxD1 HTxD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 P90/AN8 P91/AN9 P92/AN10 P93/AN11 AVSS MD0 MD1 MD2 PF0/IRQ2 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 VSS PB0/A8/TIOCA3 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 TOP VIEW (FP-128B) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 PWMVSS PJ7/PWM2H PJ6/PWM2G PJ5/PWM2F PJ4/PWM2E PWMVCC PJ3/PWM2D PJ2/PWM2C PJ1/PWM2B PJ0/PWM2A PWMVSS PH7/PWM1H PH6/PWM1G PH5/PWM1F PH4/PWM1E PWMVCC PH3/PWM1D PH2/PWM1C PH1/PWM1B PH0/PWM1A PWMVSS VSS PF3/LWR/ADTRG/IRQ3 PF4/HWR PF5/RD PF6/AS Notes: PPG and D/A converter pin functions not implemented. 1. Connect a 0.1 F capacitor between VCL and VSS (close to the pins). 2. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask version. INDEX These functions cannot be used with the other versions. See section 22A.7, Subclock Oscillator, for the method of fixing pins OSC1 and OSC2. 3. The FWE pin is for compatibility with the flash memory version. The FWE pin is a NC pin in the mask ROM versions. In the mask ROM version, the FWE pin must be left open or be connected to Vss. INDEX 64F2636F20 H8S/2636 (U-Mask Version) 64F2636F20 H8S/2636 U Figure 1-2 Pin Arrangement of H8S/2636 Group (FP-128B: Top View) Rev. 6.00 Feb 22, 2005 page 9 of 1484 REJ09B0103-0600 Section 1 Overview Vref AVCC NC VSS HRxD0 HTxD0 P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2/IRQ1 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1/IRQ0 P13/PO11/TIOCD0/TCLKB/A23 P12/PO10/TIOCC0/TCLKA/A22 P11/PO9/TIOCB0/A21 P10/PO8/TIOCA0/A20 PF7/ STBY FWE*4 EXTAL *1 VSS 0.1 F XTAL 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VCL VCC VCC OSC1*2 OSC2*2 PLLVSS VSS PLLCAP NMI RES P35/SCK1/SCL0*3/IRQ5 P34/RxD1/SDA0*3 P33/TxD1/SCL1*3 P32/SCK0/SDA1*3/IRQ4 VSS VSS P31/RxD0 P30/TxD0 Notes: The PPG and D/A converter pin functions not implemented. 1. Connect a 0.1 F capacitor between VCL and VSS (close to the pins). 2. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions. These functions cannot be used with the other versions. See section 22A.7, Subclock Oscillator, for the method of fixing pins OSC1 and OSC2. 3. These pins are used for the I2C bus interface. The I2C bus interface is available as an option. The product equipped with the I2C bus interface is the W-mask version. 4. The FWE pin is for compatibility with the flash memory version. The FWE pin is a NC pin in the mask ROM versions. In the mask ROM version, the FWE pin must be left open or be connected to Vss. VCC VCC NC NC PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 VCC PD0/D8 VSS PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 VSS VSS HRxD1 HTxD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 P90/AN8 P91/AN9 P92/AN10 P93/AN11 AVSS MD0 MD1 MD2 PF0/IRQ2 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 VSS PB0/A8/TIOCA3 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 TOP VIEW (FP-128B) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 PWMVSS PJ7/ P W M 2 H PJ6/ P W M 2 G PJ5/ P W M 2 F PJ4/ P W M 2 E PWMVCC PJ3/ P W M 2 D PJ2/ P W M 2 C PJ1/ P W M 2 B PJ0/ P W M 2 A PWMVSS PH7/ P W M 1 H PH6/ P W M 1 G PH5/ P W M 1 F PH4/ P W M 1 E PWMVCC PH3/ P W M 1 D PH2/ P W M 1 C PH1/ P W M 1 B PH0/ P W M 1 A PWMVSS VSS PF3/LWR/ADTRG/IRQ3 PF4/HWR PF5/RD PF6/AS 64F2638F20 H8S/2638 INDEX INDEX 64F2630F20 H8S/2630 (U-Mask Version) 64F2638F20 H8S/2638 U INDEX INDEX (U-Mask Version) 64F2630F20 H8S/2630 U (W-Mask Version) 64F2638F20 H8S/2638 W INDEX INDEX (W-Mask Version) 64F2630F20 H8S/2630 W Figure 1-3 Pin Arrangement of H8S/2638 Group and H8S/2630 Group (FP-128B: Top View) Rev. 6.00 Feb 22, 2005 page 10 of 1484 REJ09B0103-0600 Section 1 Overview 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 Vref AVCC NC VSS HRxD0 HTxD0 P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2/IRQ1 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1/IRQ0 P13/PO11/TIOCD0/TCLKB/A23 P12/PO10/TIOCC0/TCLKA/A22 P11/PO9/TIOCB0/A21 P10/PO8/TIOCA0/A20 PF7/ STBY FWE*3 EXTAL *1 VSS 0.1 F XTAL VCL VCC VCC VSS NC PLLVSS VSS PLLCAP NMI RES P35/SCK1/SCL0*2/IRQ5 P34/RxD1/SDA0*2 P33/TxD1/SCL1*2 P32/SCK0/SDA1*2/IRQ4 VSS VSS P31/RxD0 P30/TxD0 Notes: 1. Connect a 0.1 F capacitor between VCL and VSS (close to the pins). 2. These pins are used for the I2C bus interface. The I2C bus interface is available as an option. The product equipped with the I2C bus interface is the W-mask version. INDEX 3. The FWE pin is for compatibility with the flash memory version. The FWE pin is a NC pin in the mask ROM versions. In the mask ROM version, the FWE pin must be left open or be connected to Vss. Figure 1-4 Pin Arrangement of H8S/2639 Group (FP-128B: Top View) VCC VCC NC NC PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 VCC PD0/D8 VSS PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 VSS VSS HRxD1 HTxD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 P90/AN8 P91/AN9 P92/AN10 P93/AN11 AVSS MD0 MD1 MD2 PF0/IRQ2 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 VSS PB0/A8/TIOCA3 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 TOP VIEW (FP-128B) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 PWMVSS PJ7/P W M 2 H PJ6/P W M 2 G PJ5/P W M 2 F PJ4/P W M 2 E PWMVCC PJ3/P W M 2 D PJ2/P W M 2 C PJ1/P W M 2 B PJ0/P W M 2 A PWMVSS PH7/ P W M 1 H PH6/ P W M 1 G PH5/ P W M 1 F PH4/ P W M 1 E PWMVCC PH3/ P W M 1 D PH2/ P W M 1 C PH1/ P W M 1 B PH0/ P W M 1 A PWMVSS VSS PF3/LWR/ADTRG/IRQ3 PF4/HWR PF5/RD PF6/AS (U-Mask Version) 64F2639F20 H8S/2639 U (W-Mask Version) 64F2639F20 H8S/2639 W INDEX Rev. 6.00 Feb 22, 2005 page 11 of 1484 REJ09B0103-0600 Section 1 Overview 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 Vref AVCC NC VSS HRxD0 HTxD0 P17/TIOCB2/TCLKD P16/TIOCA2/IRQ1 P15/TIOCB1/TCLKC P14/TIOCA1/IRQ0 P13/TIOCD0/TCLKB/A23 P12/TIOCC0/TCLKA/A22 P11/PO9/TIOCB0/A21 P10/PO8/TIOCA0/A20 PF7/ STBY FWE*2 EXTAL *1 VSS 0.1 F XTAL VCL VCC VCC VSS NC PLLVSS VSS PLLCAP NMI RES P35/SCK1/IRQ5 P34/RxD1 P33/TxD1 P32/SCK0/IRQ4 VSS VSS P31/RxD0 P30/TxD0 Notes: 1. Connect a 0.1 F capacitor between VCL and VSS (close to the pins). 2. The FWE pin is for compatibility with the flash memory version. The FWE pin is a NC pin in the mask ROM versions. In the mask ROM version, the FWE pin must be left open or be connected to Vss. Figure 1-5 Pin Arrangement of H8S/2635 Group (FP-128B: Top View) Rev. 6.00 Feb 22, 2005 page 12 of 1484 REJ09B0103-0600 VCC VCC NC NC PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 VCC PD0/D8 VSS PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 VSS VSS VSS VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9 P92/AN10 P93/AN11 AVSS MD0 MD1 MD2 PF0/IRQ2 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 VSS PB0/A8/TIOCA3 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 TOP VIEW (FP-128B) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 PWMVSS PJ7/ P W M 2 H PJ6/ P W M 2 G PJ5/ P W M 2 F PJ4/ P W M 2 E PWMVCC PJ3/ P W M 2 D PJ2/ P W M 2 C PJ1/ P W M 2 B PJ0/ P W M 2 A PWMVSS PH7/ P W M 1 H PH6/ P W M 1 G PH5/ P W M 1 F PH4/ P W M 1 E PWMVCC PH3/ P W M 1 D PH2/ P W M 1 C PH1/ P W M 1 B PH0/ P W M 1 A PWMVSS VSS PF3/LWR/ADTRG/IRQ3 PF4/HWR PF5/RD PF6/AS Section 1 Overview 1.3.2 Pin Functions in Each Operating Mode Table 1-2 shows the pin functions for each operating mode. Table 1-2 Pin No. FP-128B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Mode 4 VCC VCC NC NC PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 VCC D8 VSS Mode 5 VCC VCC NC NC PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 VCC D8 VSS Pin Functions in Each Operating Mode Pin Name Mode 6 VCC VCC NC NC PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 D15 D14 D13 D12 D11 D10 D9 VCC D8 VSS Mode 7 VCC VCC NC NC PA0 PA1/TxD2 PA2/RxD2 PA3/SCK2 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 VCC PD0 VSS Rev. 6.00 Feb 22, 2005 page 13 of 1484 REJ09B0103-0600 Section 1 Overview Pin No. FP-128B 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Mode 4 PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 VSS VSS HRxD1 HTxD1 Mode 5 PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 VSS VSS HRxD1 HTxD1 Pin Name Mode 6 PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 VSS VSS HRxD1 HTxD1 Mode 7 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 VSS VSS HRxD1 HTxD1 PF6 PF5 PF4 PF3/ADTRG/ VSS / / PF3/LWR/ADTRG/ PF3/LWR/ADTRG/ VSS VSS VSS PWMVSS PH0/PWM1A PH1/PWM1B PH2/PWM1C PH3/PWM1D PWMVCC PH4/PWM1E PH5/PWM1F PH6/PWM1G PH7/PWM1H PWMVSS PJ0/PWM2A PJ1/PWM2B PWMVSS PH0/PWM1A PH1/PWM1B PH2/PWM1C PH3/PWM1D PWMVCC PH4/PWM1E PH5/PWM1F PH6/PWM1G PH7/PWM1H PWMVSS PJ0/PWM2A PJ1/PWM2B PWMVSS PH0/PWM1A PH1/PWM1B PH2/PWM1C PH3/PWM1D PWMVCC PH4/PWM1E PH5/PWM1F PH6/PWM1G PH7/PWM1H PWMVSS PJ0/PWM2A PJ1/PWM2B PH0/PWM1A PH1/PWM1B PH2/PWM1C PH3/PWM1D PWMVCC PH4/PWM1E PH5/PWM1F PH6/PWM1G PH7/PWM1H PWMVSS PJ0/PWM2A PJ1/PWM2B Rev. 6.00 Feb 22, 2005 page 14 of 1484 REJ09B0103-0600 3QRI PWMVSS RWH DR SA 3QRI RWH DR SA 3QRI 3QRI GRTDA RWL RWH DR SA Section 1 Overview Pin No. FP-128B 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Mode 4 PJ2/PWM2C PJ3/PWM2D PWMVCC PJ4/PWM2E PJ5/PWM2F PJ6/PWM2G PJ7/PWM2H PWMVSS P30/TxD0 P31/RxD0 VSS VSS P32/SCK0/SDA1 / *2 Mode 5 PJ2/PWM2C PJ3/PWM2D PWMVCC PJ4/PWM2E PJ5/PWM2F PJ6/PWM2G PJ7/PWM2H PWMVSS P30/TxD0 P31/RxD0 VSS VSS P32/SCK0/SDA1 / *2 Pin Name Mode 6 PJ2/PWM2C PJ3/PWM2D PWMVCC PJ4/PWM2E PJ5/PWM2F PJ6/PWM2G PJ7/PWM2H PWMVSS P30/TxD0 P31/RxD0 VSS VSS P32/SCK0/SDA1 / *2 Mode 7 PJ2/PWM2C PJ3/PWM2D PWMVCC PJ4/PWM2E PJ5/PWM2F PJ6/PWM2G PJ7/PWM2H PWMVSS P30/TxD0 P31/RxD0 VSS VSS P32/SCK0/SDA1*2/ P33/TxD1/SCL1*2 P34/RxD1/SDA0*2 P33/TxD1/SCL1*2 P34/RxD1/SDA0*2 P35/SCK1/SCL0 / *2 P33/TxD1/SCL1*2 P34/RxD1/SDA0*2 P35/SCK1/SCL0 / *2 P35/SCK1/SCL0 / *2 NMI NMI NMI PLLCAP VSS PLLVSS OSC2 *1 PLLCAP VSS PLLVSS OSC2 *1 PLLCAP VSS PLLVSS OSC2 *1 VSS PLLVSS OSC2*1 OSC1*1 VCC VCC VCL XTAL VSS EXTAL FWE*3 OSC1*1 VCC VCC VCL XTAL VSS EXTAL FWE*3 OSC1*1 VCC VCC VCL XTAL VSS EXTAL FWE*3 OSC1*1 VCC VCC VCL XTAL VSS EXTAL FWE*3 Rev. 6.00 Feb 22, 2005 page 15 of 1484 REJ09B0103-0600 4QRI SER 5QRI NMI 4QRI SER 5QRI 4QRI SER 5QRI 4QRI SER 5QRI P33/TxD1/SCL1*2 P34/RxD1/SDA0*2 P35/SCK1/SCL0*2/ PLLCAP Section 1 Overview Pin No. FP-128B 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Mode 4 Mode 5 Pin Name Mode 6 Mode 7 PF7/ *4 4 PF7/ *4 4 PF7/ *4 4 PF7/ P10/PO8 /TIOCA0/A20 P10/PO8 /TIOCA0/A20 P10/PO8 /TIOCA0/A20 P10/PO8*4/TIOCA0 P11/PO9* /TIOCB0/A21 P11/PO9* /TIOCB0/A21 P11/PO9* /TIOCB0/A21 P11/PO9* /TIOCB0 P12/PO10*4/TIOCC0/ TCLKA/A22 P13/PO11*4/TIOCD0/ TCLKB/A23 P14/PO12* /TIOCA1/ 4 4 P12/PO10*4/TIOCC0/ TCLKA/A22 P13/PO11* /TIOCD0/ TCLKB/A23 P14/PO12* /TIOCA1/ P15/PO13* /TIOCB1/ TCLKC P16/PO14*4/TIOCA2/ P17/PO15* /TIOCB2/ TCLKD HTxD0 HRxD0 VSS NC AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0*4 P47/AN7/DA1*4 P90/AN8 P91/AN9 4 4 P12/PO10*4/TIOCC0/ TCLKA/A22 P13/PO11* /TIOCD0/ TCLKB/A23 P14/PO12* /TIOCA1/ P15/PO13* /TIOCB1/ TCLKC P16/PO14*4/TIOCA2/ P17/PO15* /TIOCB2/ TCLKD HTxD0 HRxD0 VSS NC AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0*4 P47/AN7/DA1*4 P90/AN8 P91/AN9 4 4 P12/PO10*4/TIOCC0/ TCLKA P13/PO11* /TIOCD0/ TCLKB P14/PO12* /TIOCA1/ P15/PO13* /TIOCB1/ TCLKC P16/PO14*4/TIOCA2/ P17/PO15* /TIOCB2/ TCLKD HTxD0 HRxD0 VSS NC AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0*4 P47/AN7/DA1*4 P90/AN8 P91/AN9 4 4 P15/PO13* /TIOCB1/ TCLKC P16/PO14*4/TIOCA2/ 4 4 4 P17/PO15* /TIOCB2/ TCLKD HTxD0 HRxD0 VSS NC AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0*4 P47/AN7/DA1*4 P90/AN8 P91/AN9 4 4 4 Rev. 6.00 Feb 22, 2005 page 16 of 1484 REJ09B0103-0600 YBTS 0QRI 1QRI YBTS 0QRI 1QRI YBTS 0QRI 1QRI YBTS 0QRI 1QRI 4 4 Section 1 Overview Pin No. FP-128B 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Mode 4 P92/AN10 P93/AN11 AVSS MD0 MD1 MD2 PF0/IRQ2 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 VSS PB0/A8/TIOCA3 Mode 5 P92/AN10 P93/AN11 AVSS MD0 MD1 MD2 PF0/IRQ2 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 VSS PB0/A8/TIOCA3 Pin Name Mode 6 P92/AN10 P93/AN11 AVSS MD0 MD1 MD2 PF0/IRQ2 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 VSS PB0/A8/TIOCA3 Mode 7 P92/AN10 P93/AN11 AVSS MD0 MD1 MD2 PF0/IRQ2 PB7/TIOCB5 PB6/TIOCA5 PB5/TIOCB4 PB4/TIOCA4 PB3/TIOCD3 PB2/TIOCC3 PB1/TIOCB3 VSS PB0/TIOCA3 Notes: NC pins should be connected to VSS or left open. 1. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group. These functions cannot be used with the other versions. See section 22A.7, Subclock Oscillator, for the method of fixing pins OSC1 and OSC2. The H8S/2639 and H8S/2635 Groups have no OSC1 and OSC2 pins. 2. These pins are used for the I2C bus interface. The I2C bus interface is available as an option (H8S/2638, H8S/2639, H8S/2630 only). The product equipped with the I2C bus interface is the W-mask version. 3. The FWE pin is for compatibility with the flash memory version. The FWE pin is a NC pin in the mask ROM versions. In the mask ROM version, the FWE pin must be left open or be connected to Vss. 4. The PPG output, DA0, and DA1 are not supported in H8S/2635 Group. Rev. 6.00 Feb 22, 2005 page 17 of 1484 REJ09B0103-0600 Section 1 Overview 1.3.3 Pin Functions Table 1-3 outlines the pin functions of the H8S/2636. Table 1-3 Type Power Pin Functions Symbol VCC I/O Input Name and Function Power supply: For connection to the power supply. All VCC pins should be connected to the system power supply. Ground: For connection to ground (0 V). All VSS pins should be connected to the system power supply (0 V). On-chip step-down power supply pin: The VCL pin need not be connected to the power supply. Connect this pin to VSS via a 0.1 F capacitor (placed close to the pins). PLL ground: Ground for on-chip PLL oscillator. PLL capacitance: External capacitance pin for on-chip PLL oscillator. Crystal: Connects to a crystal oscillator. See section 22A, 22B, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator. External clock: Connects to a crystal oscillator. See section 22A, 22B, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator. Subclock: Connects to a 32.768 kHz crystal oscillator. See section 22A, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator. Subclock: Connects to a 32.768 kHz crystal oscillator. See section 22A, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator. System clock: Supplies the system clock to an external device. HCAN transmit data: Pin for CAN bus transmission. HCAN receive data: Pin for CAN bus reception. VSS Input VCL Output Clock PLLVSS PLLCAP XTAL Input Input Input EXTAL Input OSC1*1 Input OSC2*1 Input HCAN HTxD0, 3 HTxD1* HRxD0, HRxD1*3 Output Output Input Rev. 6.00 Feb 22, 2005 page 18 of 1484 REJ09B0103-0600 Section 1 Overview Type Operating mode control Symbol MD2 to MD0 I/O Input Name and Function Mode pins: These pins set the operating mode. The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the H8S/2636 is operating. MD2 0 MD1 0 1 1 0 1 MD0 0 1 0 1 0 1 0 1 System control Input Input Input Input Operating Mode -- -- -- -- Mode 4 Mode 5 Mode 6 Mode 7 Reset input: When this pin is driven low, the chip is reset. Standby: When this pin is driven low, a transition is made to hardware standby mode. Flash write enable: Pin for flash memory use (in planning stage). Nonmaskable interrupt: Requests a nonmaskable interrupt. When this pin is not used, it should be fixed high. Interrupt request 5 to 0: These pins request a maskable interrupt. Address bus: These pins output an address. Data bus: These pins constitute a bidirectional data bus. Address strobe: When this pin is low, it indicates that address output on the address bus is enabled. Read: When this pin is low, it indicates that the external address space can be read. High write: A strobe signal that writes to external space and indicates that the upper half (D15 to D8) of the data bus is enabled. Interrupts Address bus Data bus Bus control A23 to A0 D15 to D0 0QRI YBTS RWH 5QRI SER FWE*2 NMI to Input Output I/O Output Output Output DR SA Rev. 6.00 Feb 22, 2005 page 19 of 1484 REJ09B0103-0600 Section 1 Overview Type Bus control Symbol RWL I/O Output Name and Function Low write: A strobe signal that writes to external space and indicates that the lower half (D7 to D0) of the data bus is enabled. Clock input D to A: These pins input an external clock. Input capture/output compare match A0 to D0: The TGR0A to TGR0D input capture input or output compare output, or PWM output pins. Input capture/output compare match A1 and B1: The TGR1A and TGR1B input capture input or output compare output, or PWM output pins. Input capture/output compare match A2 and B2: The TGR2A and TGR2B input capture input or output compare output, or PWM output pins. Input capture/output compare match A3 to D3: The TGR3A to TGR3D input capture input or output compare output, or PWM output pins. Input capture/output compare match A4 and B4: The TGR4A and TGR4B input capture input or output compare output, or PWM output pins. Input capture/output compare match A5 and B5: The TGR5A and TGR5B input capture input or output compare output, or PWM output pins. Pulse output 15 to 8: Pulse output pins. 16-bit timerpulse unit (TPU) TCLKD to TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 TIOCA2, TIOCB2 TIOCA3, TIOCB3, TIOCC3, TIOCD3 TIOCA4, TIOCB4 TIOCA5, TIOCB5 Input I/O I/O I/O I/O I/O I/O Programmable pulse generator (PPG) Serial communication interface (SCI)/ Smart Card interface PO15 to 4 PO8* TxD2, TxD1, TxD0 RxD2, RxD1, RxD0 SCK2, SCK1, SCK0 Output Output Transmit data (channel 0, 1, 2): Data output pins. Input Receive data (channel 0, 1, 2): Data input pins. I/O Serial clock (channel 0, 1, 2): Clock I/O pins. A/D converter AN11 to AN0 Input Input GRTDA Analog 11 to 0: Analog input pins. A/D conversion external trigger input: Pin for input of an external trigger to start A/D conversion. Rev. 6.00 Feb 22, 2005 page 20 of 1484 REJ09B0103-0600 Section 1 Overview Type D/A converter A/D converter, D/A converter Symbol DA1, DA0*5 AVCC I/O Output Input Name and Function Analog output: Analog output pins for D/A converter. Analog power supply: A/D converter and D/A converter power supply pin. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+5 V). AVSS Input Analog ground: Ground pin for A/D converter and D/A converter. Connect to system power supply (0 V). Vref Input Analog reference power supply: A/D converter and D/A converter reference voltage input pin. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+5 V). I/O ports P17 to P10 I/O Port 1: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 1 data direction register (P1DDR). Port 3: A 6-bit I/O port. Input or output can be designated for each bit by means of the port 3 data direction register (P3DDR). Port 4: An 8-bit input port. Port 9: A 4-bit input port. Port A: A 4-bit I/O port. Input or output can be designated for each bit by means of the port A data direction register (PADDR). Port B: An 8-bit I/O port. Input or output can be designated for each bit by means of the port B data direction register (PBDDR). Port C: An 8-bit I/O port. Input or output can be designated for each bit by means of the port C data direction register (PCDDR). Port D: An 8-bit I/O port. Input or output can be designated for each bit by means of the port D data direction register (PDDDR). Port E: An 8-bit I/O port. Input or output can be designated for each bit by means of the port E data direction register (PEDDR). P35 to P30 I/O P47 to P40 P93 to P90 PA3 to PA0 Input Input I/O PB7 to PB0 I/O PC7 to PC0 I/O PD7 to PD0 I/O PE7 to PE0 I/O Rev. 6.00 Feb 22, 2005 page 21 of 1484 REJ09B0103-0600 Section 1 Overview Type I/O ports Symbol PF7 to PF3, PF0 PH7 to PH0 I/O I/O Name and Function Port F: A 6-bit I/O port. Input or output can be designated for each bit by means of the port F data direction register (PFDDR). Port H: An 8-bit I/O port. Input or output can be designated for each bit by means of the port B data direction register (PHDDR). Port J: An 8-bit I/O port. Input or output can be designated for each bit by means of the port J data direction register (PJDDR). PWM output: Motor control PWM channel 1 output pins. PWM output: Motor control PWM channel 2 output pins. PWM Power Supply: Power supply pin for motorcontrol PWM. Connect to the system power supply (+5 V) when the motor-control function is not used. PWM Ground: Ground pin for motor-control PWM. Connect to the system power supply (0 V). I2C clock input/output (Channel 0/1): I2C clock input/output pins that have bus-driving capability. The output of SCL0 is an NMOS open-drain type. I2C data input/output (Channel 0/1): I2C data input/output pins that have bus-driving capability. The output of SDA0 is an NMOS open-drain type. I/O PJ7 to PJ0 I/O Motor control PWM PWM1A to PWM1H PWM2A to PWM2H PWMVCC Output Output Input PWMVSS Input I2C bus interface SCL0, SCL1 I/O (IIC) (Optionk) (Only for the Wmask version of SDA0, SDA1 I/O the H8S/2638, H8S/2639, and H8S/2630) Notes: 1. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group. These functions cannot be used with the other versions. See section 22A.7, Subclock Oscillator, for the method of fixing pins OSC1 and OSC2. The H8S/2639 and H8S/2635 Groups have no OSC1 and OSC2 pins. 2. The FWE pin is functional only in the flash memory version. The FWE pin is a NC pin in the mask ROM versions. In the mask ROM version, the FWE pin must be left open or be connected to Vss. 3. The HTxD1 and HRxD1 pins are not supported in H8S/2635 Group. 4. The PO15 to PO8 output are not supported in H8S/2635 Group. 5. The DA1 and DA0 output are not supported in H8S/2635 Group. Rev. 6.00 Feb 22, 2005 page 22 of 1484 REJ09B0103-0600 Section 1 Overview 1.4 Differences between H8S/2636, H8S/2638, H8S/2639, H8S/2630, H8S/2635, and H8S/2634 There are four versions of the H8S/2636, including ROM and U-mask options; there are six versions of the H8S/2638, including ROM, U-mask, and W-mask options; and there are four versions of the H8S/2639, including ROM, U-mask, and W-mask options; and there are six versions of the H8S/2630, including ROM, U-mask, and W-mask options. The specifications of these products are compared in table 1-4 below. Table 1-4 Comparison of Product Specifications Product Specifications Product Type Model ROM RAM 2 Subclock I C Bus Function Interface HCAN DTC, PBC, Power-Down PPG, Modes DAC See section 23A, PowerDown Modes See section 23B, PowerDown Modes H8S/2636 HD64F2636F HD64F2636UF 128-kbyte on-chip flash memory 4-kbyte SRAM No No 2 Yes channels Yes HD6432636F 128-kbyte mask ROM No No See section 23A, PowerDown Modes See section 23B, PowerDown Modes HD6432636UF Yes H8S/2638 HD64F2638F HD64F2638UF HD64F2638WF HD6432638F 256-kbyte on-chip flash memory 16-kbyte No SRAM Yes No See section 23A, PowerDown Modes See section 23B, PowerDown Modes See section 23A, PowerDown Modes See section 23B, PowerDown Modes Yes 256-kbyte mask ROM No No HD6432638UF HD6432638WF Yes Yes Rev. 6.00 Feb 22, 2005 page 23 of 1484 REJ09B0103-0600 Section 1 Overview Product Specifications Product Type Model 2 Subclock I C Bus Function Interface ROM RAM HCAN DTC, PBC, Power-Down PPG, Modes DAC See section 23B, PowerDown Modes H8S/2639* 1 HD64F2639UF 256-kbyte on-chip HD64F2639WF flash memory HD6432639UF 256-kbyte mask ROM HD6432639WF 16-kbyte Yes SRAM No Yes 2 Yes channels No Yes 16-kbyte No SRAM Yes Yes No See section 23A, PowerDown Modes See section 23B, PowerDown Modes See section 23A, PowerDown Modes See section 23B, PowerDown Modes 1 channel No H8S/2630 HD64F2630F HD64F2630UF HD64F2630WF HD6432630F 384-kbyte on-chip flash memory 384-kbyte mask ROM No No HD6432630UF HD6432630WF H8S/2635*1 HD64F2635F 192-kbyte on-chip flash memory 6-kbyte SRAM Yes Yes Yes No HD6432635F*2 192-kbyte mask ROM H8S/2634* 1 HD6432634F* 2 128-kbyte mask ROM Notes: 1. For details of the H8S/2639, H8S/2635, and H8S/2634 clock pulse generator, see section 22B, Clock Pulse Generator (H8S/2639 Group, H8S/2635 Group). 2. Under development Rev. 6.00 Feb 22, 2005 page 24 of 1484 REJ09B0103-0600 Section 2 CPU Section 2 CPU 2.1 Overview The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features The H8S/2600 CPU has the following features. * Upward-compatible with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H object programs * General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * Sixty-nine basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions Multiply-and-accumulate instruction * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes (4 Gbytes architecturally) Rev. 6.00 Feb 22, 2005 page 25 of 1484 REJ09B0103-0600 Section 2 CPU * High-speed operation All frequently-used instructions execute in one or two states Maximum clock rate : 20 MHz 8/16/32-bit register-register add/subtract : 50 ns 8 x 8-bit register-register multiply : 150 ns 16 / 8-bit register-register divide : 600 ns 16 x 16-bit register-register multiply : 200 ns 32 / 16-bit register-register divide : 1000 ns * Two CPU operating modes Normal mode* Advanced mode Note: * Not available in the chip. * Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. * Register configuration The MAC register is supported only by the H8S/2600 CPU. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. * Number of execution states The number of execution states of the MULXU and MULXS instructions is different in each CPU. Execution States Instruction MULXU MULXS Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21 Rev. 6.00 Feb 22, 2005 page 26 of 1484 REJ09B0103-0600 Section 2 CPU In addition, there are differences in address space, CCR and EXR register functions, power-down modes, etc., depending on the model. 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements. * More general registers and control registers Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been added * Expanded address space Normal mode* supports the same 64-kbyte address space as the H8/300 CPU Advanced mode supports a maximum 16-Mbyte address space Note: * Not available in the chip. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced Signed multiply and divide instructions have been added A multiply-and-accumulate instruction has been added Two-bit shift instructions have been added Instructions for saving and restoring multiple registers have been added A test and set instruction has been added * Higher speed Basic instructions execute twice as fast Rev. 6.00 Feb 22, 2005 page 27 of 1484 REJ09B0103-0600 Section 2 CPU 2.1.4 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements. * Additional control register One 8-bit and two 32-bit control registers have been added * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced A multiply-and-accumulate instruction has been added Two-bit shift instructions have been added Instructions for saving and restoring multiple registers have been added A test and set instruction has been added * Higher speed Basic instructions execute twice as fast 2.2 CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode* supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for program and data areas combined). The mode is selected by the mode pins of the microcontroller. Note: * Not available in the chip. Maximum 64 kbytes, program and data areas combined Normal mode* CPU operating modes Advanced mode Note: * Not available in the chip. Maximum 16-Mbytes for program and data areas combined Figure 2-1 CPU Operating Modes Rev. 6.00 Feb 22, 2005 page 28 of 1484 REJ09B0103-0600 Section 2 CPU (1) Normal Mode (Not Available in the Chip) The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be accessed. Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits (figure 2-2). The exception vector table differs depending on the microcontroller. For details of the exception vector table, see section 4, Exception Handling. H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2-2 Exception Vector Table (Normal Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16Rev. 6.00 Feb 22, 2005 page 29 of 1484 REJ09B0103-0600 Section 2 CPU bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2-3. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. SP PC (16 bits) SP *2 (SP ) EXR*1 Reserved*1 *3 CCR CCR*3 PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning. Figure 2-3 Stack Structure in Normal Mode (2) Advanced Mode Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4 Gbytes for program and data areas combined). Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. Instruction Set: All instructions and addressing modes can be used. Rev. 6.00 Feb 22, 2005 page 30 of 1484 REJ09B0103-0600 Section 2 CPU Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2-4). For details of the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Reset exception vector H'00000003 H'00000004 Reserved H'00000007 H'00000008 Exception vector table H'0000000B H'0000000C (Reserved for system use) H'00000010 Reserved Exception vector 1 Figure 2-4 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table. Rev. 6.00 Feb 22, 2005 page 31 of 1484 REJ09B0103-0600 Section 2 CPU Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2-5. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. SP SP Reserved PC (24 bits) (SP *2 ) EXR*1 Reserved*1 *3 CCR PC (24 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning. Figure 2-5 Stack Structure in Advanced Mode Rev. 6.00 Feb 22, 2005 page 32 of 1484 REJ09B0103-0600 Section 2 CPU 2.3 Address Space Figure 2-6 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF Data area Cannot be used by the chip H'FFFFFFFF (a) Normal Mode* Note: * Not available in the chip. (b) Advanced Mode Figure 2-6 Memory Map Rev. 6.00 Feb 22, 2005 page 33 of 1484 REJ09B0103-0600 Section 2 CPU 2.4 2.4.1 Register Configuration Overview The CPU has the internal registers shown in figure 2-7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) Control Registers (CR) 23 PC 76543210 EXR T I2 I1 I0 76543210 CCR I UI H U N Z V C 63 MAC 31 Legend: SP: PC: EXR: T: I2 to I0: CCR: I: UI: Sign extension MACL 0 41 MACH 32 0 E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit* H: U: N: Z: V: C: MAC: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Multiply-accumulate register Note: * Cannot be used as an interrupt mask bit in the chip. Figure 2-7 CPU Registers Rev. 6.00 Feb 22, 2005 page 34 of 1484 REJ09B0103-0600 Section 2 CPU 2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2-8 illustrates the usage of the general registers. The usage of each register can be selected independently. * Address registers * 32-bit registers * 16-bit registers E registers (extended registers) (E0 to E7) * 8-bit registers ER registers (ER0 to ER7) R registers (R0 to R7) RH registers (R0H to R7H) RL registers (R0L to R7L) Figure 2-8 Usage of General Registers Rev. 6.00 Feb 22, 2005 page 35 of 1484 REJ09B0103-0600 Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2-9 shows the stack. Free area SP (ER7) Stack area Figure 2-9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR), and 64-bit multiply-accumulate register (MAC). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored (When an instruction is fetched, the least significant PC bit is regarded as 0). (2) Extended Control Register (EXR) This 8-bit register contains the trace bit (T) and three interrupt mask bits (I2 to I0). Bit 7--Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is executed. Bits 6 to 3--Reserved: These bits are reserved. They are always read as 1. Rev. 6.00 Feb 22, 2005 page 36 of 1484 REJ09B0103-0600 Section 2 CPU Bits 2 to 0--Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. All interrupts, including NMI, are disabled for three states after one of these instructions is executed, except for STC. (3) Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7--Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1 (NMI is accepted regardless of the I bit setting). The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. For details, refer to section 5, Interrupt Controller. Bit 6--User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details, refer to section 5, Interrupt Controller. Bit 5--Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4--User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3--Negative Flag (N): Stores the value of the most significant bit (sign bit) of data. Bit 2--Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1--Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * Add instructions, to indicate a carry * Subtract instructions, to indicate a borrow * Shift and rotate instructions, to store the value shifted out of the end bit Rev. 6.00 Feb 22, 2005 page 37 of 1484 REJ09B0103-0600 Section 2 CPU The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to Appendix A.1, List of Instructions. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. (4) Multiply-Accumulate Register (MAC) This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are a sign extension. 2.4.4 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. Rev. 6.00 Feb 22, 2005 page 38 of 1484 REJ09B0103-0600 Section 2 CPU 2.5 Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2-10 shows the data formats in general registers. Data Type Register Number Data Format 1-bit data RnH 7 0 76543210 Don't care 1-bit data RnL Don't care 7 0 76543210 4-bit BCD data RnH 7 Upper 43 Lower 0 Don't care 4-bit BCD data RnL Don't care 7 Upper 43 Lower 0 Byte data RnH 7 MSB 0 Don't care LSB 7 Don't care Byte data RnL 0 LSB MSB Figure 2-10 General Register Data Formats Rev. 6.00 Feb 22, 2005 page 39 of 1484 REJ09B0103-0600 Section 2 CPU Data Type Register Number Data Format Word data Rn 15 MSB 0 LSB Word data 15 MSB Longword data 31 MSB En 0 LSB ERn 16 15 En Rn 0 LSB Legend: ERn: En: Rn: RnH: RnL: MSB: LSB: General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit Figure 2-10 General Register Data Formats (cont) Rev. 6.00 Feb 22, 2005 page 40 of 1484 REJ09B0103-0600 Section 2 CPU 2.5.2 Memory Data Formats Figure 2-11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 0 0 Data Format Byte data Address L MSB LSB Word data Address 2M MSB Address 2M + 1 LSB Longword data Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB Figure 2-11 Memory Data Formats When ER7 is used as an address register to access the stack, the operand size should be word size or longword size. Rev. 6.00 Feb 22, 2005 page 41 of 1484 REJ09B0103-0600 Section 2 CPU 2.6 2.6.1 Instruction Set Overview The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in table 2-1. Table 2-1 Function Data transfer Instruction Classification Instructions MOV POP*1, PUSH*1 LDM*5, STM*5 MOVFPE*3, MOVTPE*3 Size BWL WL L B BWL B BWL L BW WL B -- BWL B -- -- 4 8 14 5 9 1 23 Types 5 Arithmetic operations ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS*4 MAC, LDMAC, STMAC, CLRMAC Logic operations Shift Bit manipulation Branch System control AND, OR, XOR, NOT BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc*2, JMP, BSR, JSR, RTS SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP -- Block data transfer EEPMOV Total: 69 types Legend: B: Byte W: Word L: Longword Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Bcc is the general name for conditional branch instructions. 3. Not available in the chip. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 5. Only registers ER0 to ER6 should be used when using the STM/LDM instruction. Rev. 6.00 Feb 22, 2005 page 42 of 1484 REJ09B0103-0600 2.6.2 Addressing Modes Table 2-2 Function Instruction #xx Rn @ERn @(d:16,ERn) @(d:32,ERn) @-ERn/@ERn+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,PC) @(d:16,PC) @@aa:8 Data transfer WL L B BWL WL B L BWL B BW BW BWL WL B L B BWL BWL MOV BWL BWL BWL BWL BWL BWL B BWL BWL POP, PUSH LDM*3, STM*3 MOVFPE*1, MOVTPE*1 Arithmetic operations ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS Instructions and Addressing Modes MULXU, DIVXU MULXS, DIVXS NEG EXTU, EXTS TAS*2 MAC CLRMAC Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Combinations of Instructions and Addressing Modes Rev. 6.00 Feb 22, 2005 page 43 of 1484 REJ09B0103-0600 LDMAC, STMAC Section 2 CPU Addressing Modes Function Instruction #xx Rn @ERn @(d:16,ERn) @(d:32,ERn) @-ERn/@ERn+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,PC) @(d:16,PC) @@aa:8 Section 2 CPU Logic operations AND, OR, XOR NOT BWL B B B W W W W W W W W W W W W B B B B B B Bcc, BSR JMP, JSR RTS TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP BWL BWL BWL Shift Bit manipulation Branch Rev. 6.00 Feb 22, 2005 page 44 of 1484 REJ09B0103-0600 BW System control Block data transfer Legend: B: Byte W: Word L: Longword Notes: 1. Not available in the chip. 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 3. Only registers ER0 to ER6 should be used when using the STM/LDM instruction. Section 2 CPU 2.6.3 Table of Instructions Classified by Function Table 2-3 summarizes the instructions in each functional category. The notation used in table 2-3 is defined below. Operation Notation Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / :8/:16/:24/:32 General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev. 6.00 Feb 22, 2005 page 45 of 1484 REJ09B0103-0600 Section 2 CPU Table 2-3 Type Data transfer Instructions Classified by Function Instruction MOV Size*1 B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. Cannot be used in this LSI. Cannot be used in this LSI. @SP+ Rn Pops a register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn @-SP Pushes a register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. @SP+ Rn (register list) Pops two or more general registers from the stack. Rn (register list) @-SP Pushes two or more general registers onto the stack. MOVFPE MOVTPE POP B B W/L PUSH W/L LDM*2 STM*2 L L Rev. 6.00 Feb 22, 2005 page 46 of 1484 REJ09B0103-0600 Section 2 CPU Type Arithmetic operations Instruction ADD SUB Size*1 B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction). Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2 (Byte operands can be incremented or decremented by 1 only). Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16bit remainder. ADDX SUBX B INC DEC B/W/L ADDS SUBS DAA DAS L B MULXU B/W MULXS B/W DIVXU B/W Rev. 6.00 Feb 22, 2005 page 47 of 1484 REJ09B0103-0600 Section 2 CPU Type Arithmetic operations Instruction DIVXS Size*1 B/W Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. @ERd - 0, 1 ( CMP B/W/L NEG B/W/L EXTU W/L EXTS W/L TAS B MAC -- CLRMAC LDMAC STMAC -- L Rev. 6.00 Feb 22, 2005 page 48 of 1484 REJ09B0103-0600 Section 2 CPU Type Logic operations Instruction AND Size*1 B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. (Rd) (Rd) Takes the one's complement of general register contents. Rd (shift) Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. Rd (shift) Rd Performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. Rd (rotate) Rd Rotates general register contents. 1-bit or 2-bit rotation is possible. Rd (rotate) Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. OR B/W/L XOR B/W/L NOT B/W/L Shift operations SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR B/W/L B/W/L B/W/L B/W/L Rev. 6.00 Feb 22, 2005 page 49 of 1484 REJ09B0103-0600 Section 2 CPU Type Bitmanipulation instructions Instruction BSET Size*1 B Function 1 ( BCLR B BNOT B BTST B BAND B BIAND B BOR B BIOR B Rev. 6.00 Feb 22, 2005 page 50 of 1484 REJ09B0103-0600 Section 2 CPU Type Bitmanipulation instructions Instruction BXOR Size*1 B Function C ( BIXOR B BLD B BILD B BST B BIST B Rev. 6.00 Feb 22, 2005 page 51 of 1484 REJ09B0103-0600 Section 2 CPU Type Branch instructions Instruction Bcc Size*1 -- Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE JMP BSR JSR RTS -- -- -- -- Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z(N V) = 0 Z(N V) = 1 Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine Rev. 6.00 Feb 22, 2005 page 52 of 1484 REJ09B0103-0600 Section 2 CPU Type Instruction Size*1 -- -- -- B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR, (EAs) EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 PC Only increments the program counter. System control TRAPA instructions RTE SLEEP LDC STC B/W ANDC B ORC B XORC B NOP -- Rev. 6.00 Feb 22, 2005 page 53 of 1484 REJ09B0103-0600 Section 2 CPU Type Block data transfer instruction Instruction EEPMOV.B Size*1 -- Function if R4L 0 then Repeat @ER5+ @ER6+ R4L-1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5+ @ER6+ R4-1 R4 Until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6. R4L or R4: size of block (bytes) ER5: starting source address ER6: starting destination address Execution of the next instruction begins as soon as the transfer is completed. Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only registers ER0 to ER6 should be used when using the STM/LDM instruction. 3. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. EEPMOV.W -- 2.6.4 Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). (1) Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. (2) Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. (3) Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. Rev. 6.00 Feb 22, 2005 page 54 of 1484 REJ09B0103-0600 Section 2 CPU (4) Condition Field: Specifies the branching condition of Bcc instructions. Figure 2-12 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc rn rm MOV.B @(d:16, Rn), Rm, etc. Figure 2-12 Instruction Formats (Examples) Rev. 6.00 Feb 22, 2005 page 55 of 1484 REJ09B0103-0600 Section 2 CPU 2.7 2.7.1 Addressing Modes and Effective Address Calculation Addressing Mode The CPU supports the eight addressing modes listed in table 2-4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2-4 No. 1 2 3 4 5 6 7 8 Addressing Modes Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect (1) Register Direct--Rn: The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. (2) Register Indirect--@ERn: The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). (3) Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn): A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. Rev. 6.00 Feb 22, 2005 page 56 of 1484 REJ09B0103-0600 Section 2 CPU (4) Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn: * Register indirect with post-increment--@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. * Register indirect with pre-decrement--@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. (5) Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32: The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2-5 indicates the accessible absolute address ranges. Table 2-5 Absolute Address Access Ranges Normal Mode* 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address 24 bits (@aa:24) H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF Absolute Address Data address Note: * Not available in the chip. Rev. 6.00 Feb 22, 2005 page 57 of 1484 REJ09B0103-0600 Section 2 CPU (6) Immediate--#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) Program-Counter Relative--@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. (8) Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode*, H'000000 to H'0000FF in advanced mode). In normal mode* the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. Note: * Not available in the chip. Rev. 6.00 Feb 22, 2005 page 58 of 1484 REJ09B0103-0600 Section 2 CPU Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode* Note: * Not available in the chip. (b) Advanced Mode Figure 2-13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address (For further information, see section 2.5.2, Memory Data Formats). 2.7.2 Effective Address Calculation Table 2-6 indicates how effective addresses are calculated in each addressing mode. In normal mode* the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: * Not available in the chip. Rev. 6.00 Feb 22, 2005 page 59 of 1484 REJ09B0103-0600 No. Effective Address Calculation Addressing Mode and Instruction Format Effective Address (EA) 1 Operand is general register contents. Table 2.6 Register direct (Rn) Section 2 CPU op rm rn 2 31 General register contents Don't care 0 31 24 23 Register indirect (@ERn) 0 op r 3 31 General register contents 31 disp 31 Sign extension disp 0 0 Register indirect with displacement @(d:16, ERn) or @(d:32, ERn) 24 23 0 Rev. 6.00 Feb 22, 2005 page 60 of 1484 REJ09B0103-0600 Effective Address Calculation op r Don't care 4 31 General register contents Register indirect with post-increment or pre-decrement * Register indirect with post-increment @ERn+ 0 31 24 23 Don't care 0 op r 1, 2, or 4 31 General register contents 31 24 23 Don't care Operand Size Value added Byte Word Longword 1 2 4 1, 2, or 4 0 0 * Register indirect with pre-decrement @-ERn op r No. Effective Address Calculation Addressing Mode and Instruction Format Effective Address (EA) 5 31 24 23 H'FFFF abs Don't care Absolute address 87 0 @aa:8 op @aa:16 31 abs op Don't care extension 16 15 24 23 Sign 0 @aa:24 abs 31 24 23 Don't care 0 op @aa:32 31 abs 24 23 Don't care op 0 6 IMM Immediate #xx:8/#xx:16/#xx:32 Operand is immediate data. Rev. 6.00 Feb 22, 2005 page 61 of 1484 REJ09B0103-0600 op Section 2 CPU No. Effective Address Calculation 23 PC contents 0 Addressing Mode and Instruction Format Effective Address (EA) 7 Program-counter relative Section 2 CPU @(d:8, PC)/@(d:16, PC) op 23 Sign extension disp 31 24 23 Don't care disp 0 0 8 Memory indirect @@aa:8 Rev. 6.00 Feb 22, 2005 page 62 of 1484 REJ09B0103-0600 abs 31 H'000000 87 abs 0 31 24 23 Don't care * Normal mode* op 16 15 H'00 0 0 15 Memory contents * Advanced mode abs 31 H'000000 31 Memory contents 87 abs 0 31 24 23 Don't care op 0 0 Note: * Not available in the chip. Section 2 CPU 2.8 2.8.1 Processing States Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2-14 shows a diagram of the processing states. Figure 2-15 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response to a reset, interrupt, or trap instruction. Processing states Program execution state The CPU executes program instructions in sequence. Bus-released state The external bus has been released in response to a bus request signal from a bus master other than the CPU. Sleep mode Power-down state CPU operation is stopped to conserve power.* Software standby mode Hardware standby mode Note: * The power-down state also includes a medium-speed mode, module stop mode, subactive mode, subsleep mode, and watch mode. See section 23A and 23B, Power-Down Modes, for details. Figure 2-14 Processing States Rev. 6.00 Feb 22, 2005 page 63 of 1484 REJ09B0103-0600 Section 2 CPU End of bus request Bus request Program execution state En d o ha f ex nd ce lin pti g on Re qu es tf or ex ce Bus-released state ion ha nd lin g s bu t of est es du qu En req re s Bu SLEEP instruction with SSBY = 0 Sleep mode pt r eq t ues SLEEP instruction with SSBY = 1 pt Inte rru Exception handling state External interrupt request Software standby mode RES = High STBY = High, RES = Low Reset state *1 Reset state Hardware standby mode*2 Power-down state*3 Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. 3. Apart from these states, there are also the watch mode, subactive mode, and the subsleep mode. See section 23A, 23B, Power-Down Modes. Figure 2-15 State Transitions 2.8.2 Reset State When the goes low, all current processing stops and the CPU enters the reset state. In reset state all interrupts are disenabled. The reset state can also be entered by a watchdog timer overflow. For details, refer to section 12, Watchdog Timer. Rev. 6.00 Feb 22, 2005 page 64 of 1484 REJ09B0103-0600 SER Reset exception handling starts when the SER signal changes from low to high. Section 2 CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2-7 indicates the types of exception handling and their priority. Trap instruction exception handling is always accepted, in the program execution state. Exception handling and the stack structure depend on the interrupt control mode set in SYSCR. Table 2-7 Priority High Exception Handling Types and Priority Type of Exception Reset Detection Timing Synchronized with clock Start of Exception Handling Exception handling starts immediately after a low-to-high transition at the pin, or when the watchdog timer overflows. When the trace (T) bit is set to 1, the trace starts at the end of the current instruction or current exception-handling sequence When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Exception handling starts when a trap (TRAPA) instruction is executed*3 Trace End of instruction execution or end of exception-handling sequence*1 End of instruction execution or end of exception-handling sequence*2 When TRAPA instruction is executed Interrupt Trap instruction Low Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception-handling is not executed at the end of the RTE instruction. 2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. 3. Trap instruction exception handling is always accepted, in the program execution state. Rev. 6.00 Feb 22, 2005 page 65 of 1484 REJ09B0103-0600 SER Section 2 CPU (2) Reset Exception Handling pin has gone low and the reset state has been entered, when goes high again, After the reset exception handling starts. The CPU enters the reset state when the is low. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends. (3) Traces Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR is set to 1. When trace mode is established, trace exception handling starts at the end of each instruction. At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode is cleared. Interrupt masks are not affected. The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to return from the trace exception-handling routine, trace mode is entered again. Trace exceptionhandling is not executed at the end of the RTE instruction. Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit. (4) Interrupt Exception Handling and Trap Instruction Exception Handling When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start address (vector) from the exception vector table and program execution starts from that start address. Figure 2-16 shows the stack after exception handling ends. Rev. 6.00 Feb 22, 2005 page 66 of 1484 REJ09B0103-0600 SER SER SER Section 2 CPU Normal mode*2 SP SP CCR CCR*1 PC (16 bits) EXR Reserved*1 CCR CCR*1 PC (16 bits) (a) Interrupt control mode 0 (b) Interrupt control mode 2 Advanced mode SP SP CCR PC (24 bits) EXR Reserved*1 CCR PC (24 bits) (c) Interrupt control mode 0 Notes: 1. Ignored when returning. 2. Not available in the chip. (d) Interrupt control mode 2 Figure 2-16 Stack Structure after Exception Handling (Examples) Rev. 6.00 Feb 22, 2005 page 67 of 1484 REJ09B0103-0600 Section 2 CPU 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. Bus masters other than the CPU is data transfer controller (DTC). For further details, refer to section 7, Bus Controller. 2.8.6 Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode, software standby mode, hardware standby mode, subsleep mode, and watch mode. There are also three other power-down modes: medium-speed mode, module stop mode, and subactive mode. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation of individual modules, other than the CPU. Subactive mode, subsleep mode, and watch mode are power-down states using subclock input. For details, refer to section 23A, 23B, Power-Down Modes. (1) Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit (SSBY) in the standby control register (SBYCR) is cleared to 0. In sleep mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of CPU registers are retained. (2) Software Standby Mode: A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is set to 0, and the PSS bit in TCSR (WDT1) is set to 0. In software standby mode, the CPU and clock halt and all MCU operations stop. As long as a specified voltage is supplied, the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states. Rev. 6.00 Feb 22, 2005 page 68 of 1484 REJ09B0103-0600 YBTS (3) Hardware Standby Mode: A transition to hardware standby mode is made when the pin goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained. Section 2 CPU 2.9 2.9.1 Basic Timing Overview The H8S/2600 CPU is driven by a system clock, denoted by the symbol . The period from one rising edge of to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 2.9.2 On-Chip Memory (ROM, RAM) On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 2-17 shows the on-chip memory access cycle. Figure 2-18 shows the pin states. Bus cycle T1 Internal address bus Internal read signal Internal data bus Internal write signal Write access Internal data bus Write data Read data Address Read access Figure 2-17 On-Chip Memory Access Cycle Rev. 6.00 Feb 22, 2005 page 69 of 1484 REJ09B0103-0600 Section 2 CPU Bus cycle T1 Address bus AS RD HWR, LWR Data bus Unchanged High High High High-impedance state Figure 2-18 Pin States during On-Chip Memory Access Rev. 6.00 Feb 22, 2005 page 70 of 1484 REJ09B0103-0600 Section 2 CPU 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2-19 shows the access timing for the on-chip supporting modules. Figure 2-20 shows the pin states. Bus cycle T1 T2 Internal address bus Address Internal read signal Read access Internal data bus Internal write signal Write access Internal data bus Write data Read data Figure 2-19 On-Chip Supporting Module Access Cycle Rev. 6.00 Feb 22, 2005 page 71 of 1484 REJ09B0103-0600 Section 2 CPU Bus cycle T1 T2 Address bus Unchanged AS RD HWR, LWR High High High Data bus High-impedance state Figure 2-20 Pin States during On-Chip Supporting Module Access Rev. 6.00 Feb 22, 2005 page 72 of 1484 REJ09B0103-0600 Section 2 CPU 2.9.4 On-Chip HCAN Module Access Timing On-chip HCAN module access is performed in four states. The data bus width is 16 bits. Wait states can be inserted by means of a wait request from the HCAN. On-chip HCAN module access timing is shown in figures 2-21 and 2-22, and the pin states in figure 2-23. Bus cycle T1 Internal address bus HCAN read signal Read Internal data bus HCAN write signal Write Internal data bus Write data Read data Address T2 T3 T4 Figure 2-21 On-Chip HCAN Module Access Cycle (No Wait State) Rev. 6.00 Feb 22, 2005 page 73 of 1484 REJ09B0103-0600 Section 2 CPU Bus cycle T1 Internal address bus HCAN read signal Read Internal data bus HCAN write signal Write Internal data bus Write data Read data Address T2 T3 Tw Tw T4 Figure 2-22 On-Chip HCAN Module Access Cycle (Wait States Inserted) Bus cycle T1 Address bus AS RD HWR, LWR Data bus Held High High High High-impedance state T2 T3 T4 Figure 2-23 Pin States in On-Chip HCAN Module Access Rev. 6.00 Feb 22, 2005 page 74 of 1484 REJ09B0103-0600 Section 2 CPU 2.9.5 Port H and J Register Access Timing Accesses to port H and J registers and the on-chip motor control PWM timer module are performed in four states. The data bus width is 8 or 16 bits depending on the internal I/O register. Access timing for port H and J registers and the on-chip motor control PWM timer module is shown in figure 2-24, and the pin states are shown in figure 2-25. Bus cycle T1 Internal address bus Read signal Read Internal data bus Write signal Write Internal data bus Write data Read data Address T2 T3 T4 Figure 2-24 Access Cycle for Ports H and J Registers and On-Chip Motor Control PWM Timer Module Rev. 6.00 Feb 22, 2005 page 75 of 1484 REJ09B0103-0600 Section 2 CPU Bus cycle T1 Address bus AS RD HWR, LWR Data bus Held High High High T2 T3 T4 High impedance Figure 2-25 Pin States in Access to Ports H and J Registers and On-Chip Motor Control PWM Timer Module 2.9.6 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 7, Bus Controller. Rev. 6.00 Feb 22, 2005 page 76 of 1484 REJ09B0103-0600 Section 2 CPU 2.10 2.10.1 Usage Note TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas Technology H8S Family and H8/300 Series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used. 2.10.2 STM/LDM Instructions With STM and LDM instructions, register ER7 cannot be used as a register that can be saved (STM) or restored (LDM) since it is the stack pointer. The number of registers that can be saved (STM) or restored (LDM) by a single instruction is two, three, or four. The registers that can be used in these cases are as follows. Two registers: ER0-ER1, ER2-ER3, ER4-ER5 Three registers: ER0-ER2, ER4-ER6 Four registers: ER0-ER3 The Renesas Technology H8S Family and H8/300 Series C/C++ compilers do not generate STM/LDM instructions that include ER7. 2.10.3 Caution to Observe when Using Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read data in a unit of byte, then, after bit manipulation, they write data in a unit of byte. Therefore, caution must be exercised when executing any of these instructions for registers and ports that include write-only bits. The BCLR instruction can be used to clear the flag of an internal I/O register to 0. In that case, if it is clearly known that the pertinent flag is set to 1 in an interrupt processing routine or other processing, there is no need to read the flag in advance. Rev. 6.00 Feb 22, 2005 page 77 of 1484 REJ09B0103-0600 Section 2 CPU Rev. 6.00 Feb 22, 2005 page 78 of 1484 REJ09B0103-0600 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 3.1.1 Overview Operating Mode Selection The chip has four operating modes (modes 4 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by setting the mode pins (MD2 to MD0). Table 3-1 lists the MCU operating modes. Table 3-1 MCU Operating Mode Selection External Data Bus On-Chip Initial ROM Width -- -- Max. Width -- MCU CPU Operating Operating Mode MD2 MD1 MD0 Mode Description 0* 1* 2* 3* 4 5 6 1 1 0 0 1 0 0 1 0 1 0 1 0 Advanced On-chip ROM disabled, expanded mode On-chip ROM enabled, expanded mode Single-chip mode -- -- -- Disabled 16 bits 8 bits Enabled 8 bits 16 bits 16 bits 16 bits 7 1 -- -- Note: * Not available in the chip. The CPU's architecture allows for 4 Gbytes of address space, but the chip actually accesses a maximum of 16 Mbytes. Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on Rev. 6.00 Feb 22, 2005 page 79 of 1484 REJ09B0103-0600 Section 3 MCU Operating Modes the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8bit access is selected for all areas, 8-bit bus mode is set. Note that the functions of each pin depend on the operating mode. The chip can be used only in modes 4 to 7. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.2 Register Configuration The chip has a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR) that controls the operation of the chip. Table 3-2 summarizes these registers. Table 3-2 Name Mode control register System control register Pin function control register MCU Registers Abbreviation MDCR SYSCR PFCR R/W R R/W R/W Initial Value Undetermined H'01 H'0D/H'00 Address* H'FDE7 H'FDE5 H'FDEB Note: * Lower 16 bits of the address. 3.2 3.2.1 Bit Register Descriptions Mode Control Register (MDCR) : 7 1 R/W 6 0 5 0 4 0 3 0 2 MDS2 * R 1 MDS1 * R 0 MDS0 * R Initial value : R/W : Note: * Determined by pins MD2 to MD0. MDCR is an 8-bit register that indicates the current operating mode of the chip. Rev. 6.00 Feb 22, 2005 page 80 of 1484 REJ09B0103-0600 Section 3 MCU Operating Modes Bit 7--Reserved: Only 1 should be written to these bits. Bits 6 to 3--Reserved: These bits are always read as 0 and cannot be modified. Bits 2 to 0--Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to MDS0 are read-only bits, and they cannot be written to. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are cancelled by a reset. 3.2.2 Bit System Control Register (SYSCR) : 7 MACS 0 R/W 6 0 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 0 1 0 0 RAME 1 R/W Initial value : R/W : SYSCR is an 8-bit readable-writable register that selects saturating or non-saturating calculation for the MAC instruction, selects the interrupt control mode, selects the detected edge for NMI, and enables or disenables on-chip RAM. SYSCR is initialized to H'01 by a reset and in hardware standby mode. SYSCR is not initialized in software standby mode. Bit 7--MAC Saturation (MACS): Selects either saturating or non-saturating calculation for the MAC instruction. Bit 7 MACS 0 1 Description Non-saturating calculation for MAC instruction Saturating calculation for MAC instruction (Initial value) Bit 6--Reserved: This bit is always read as 0 and cannot be modified. Rev. 6.00 Feb 22, 2005 page 81 of 1484 REJ09B0103-0600 Section 3 MCU Operating Modes Bits 5 and 4--Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1, Interrupt Control Modes and Interrupt Operation. Bit 5 INTM1 0 1 Bit 4 INTM0 0 1 0 1 Interrupt Control Mode Description 0 -- 2 -- Control of interrupts by I bit Setting prohibited Control of interrupts by I2 to I0 bits and IPR Setting prohibited (Initial value) Bit 3--NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input. Bit 3 NMIEG 0 1 Description An interrupt is requested at the falling edge of NMI input An interrupt is requested at the rising edge of NMI input (Initial value) Bit 2-- Reserved: Only 0 should be written to this bit. Bit 1--Reserved: This bit is always read as 0 and cannot be modified. Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset status is released. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) Note: When the DTC is used, the RAME bit must not be cleared to 0. Rev. 6.00 Feb 22, 2005 page 82 of 1484 REJ09B0103-0600 Section 3 MCU Operating Modes 3.2.3 Bit Pin Function Control Register (PFCR) : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 AE3 1/0 R/W 2 AE2 1/0 R/W 1 AE1 0 R/W 0 AE0 1/0 R/W Initial value : R/W : PFCR is an 8-bit readable-writeable register that performs address output control in on-chip ROMenabled expansion mode. PFCR is initialized to H'0D/H'00 by a reset and in the hardware standby mode. Bits 7 to 4-- Reserved: Only 0 should be written to these bits. Bits 3 to 0--Address Output Enable 3 to 0 (AE3 to AE0): These bits select enabling or disabling of address outputs A8 to A23 in on-chip ROM-disabled expansion mode and on-chip ROM-enabled expansion mode. When a pin is enabled for address output, the address is output regardless of the corresponding DDR setting. When a pin is disabled for address output, it becomes an output port when the corresponding DDR bit is set to 1. Rev. 6.00 Feb 22, 2005 page 83 of 1484 REJ09B0103-0600 Section 3 MCU Operating Modes Bit 3 AE3 0 Bit 2 AE2 0 Bit 1 AE1 0 1 Bit 0 AE0 0 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Description A8 to A23 address output disabled (Initial value*) A8 address output enabled; A9 to A23 address output disabled A8, A9 address output enabled; A10 to A23 address output disabled A8 to A10 address output enabled; A11 to A23 address output disabled A8 to A11 address output enabled; A12 to A23 address output disabled A8 to A12 address output enabled; A13 to A23 address output disabled A8 to A13 address output enabled; A14 to A23 address output disabled A8 to A14 address output enabled; A15 to A23 address output disabled A8 to A15 address output enabled; A16 to A23 address output disabled A8 to A16 address output enabled; A17 to A23 address output disabled A8 to A17 address output enabled; A18 to A23 address output disabled A8 to A18 address output enabled; A19 to A23 address output disabled A8 to A19 address output enabled; A20 to A23 address output disabled A8 to A20 address output enabled; A21 to A23 address output disabled (Initial value*) A8 to A21 address output enabled; A22, A23 address output disabled A8 to A23 address output enabled Note: * In on-chip ROM-enabled expansion mode, bits AE3 to AE0 are initialized to B'0000. In on-chip ROM-disabled expansion mode, bits AE3 to AE0 are initialized to B'1101. Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to 1. Rev. 6.00 Feb 22, 2005 page 84 of 1484 REJ09B0103-0600 Section 3 MCU Operating Modes 3.3 3.3.1 Operating Mode Descriptions Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports 1, A, B, and C function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits. 3.3.2 Mode 5 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports 1, A, B, and C function as an address bus, port D function as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.3 Mode 6 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Ports 1, A, B, and C function as input port pins immediately after a reset. Address output can be performed by setting the corresponding DDR (data direction register) bits to 1. Port D functions as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port E becomes a data bus. Rev. 6.00 Feb 22, 2005 page 85 of 1484 REJ09B0103-0600 Section 3 MCU Operating Modes 3.3.4 Mode 7 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports. 3.4 Pin Functions in Each Operating Mode The pin functions of ports 1 and A to F vary depending on the operating mode. Table 3-3 shows their functions in each operating mode. Table 3-3 Port Port A Port B Port C Port D Port E Port F PF7 PF6 to PF4 PF3 PF0 Port 1 P11 to P13 P10 Legend: P: I/O port A: Address bus output D: Data bus I/O C: Control signals, clock I/O *: After reset Pin Functions in Each Mode Mode 4 P/A* P/A* A D P/D* P/C* C P/C* P*/C P*/A P/A* Mode 5 P/A* P/A* A D P*/D P/C* C P*/C P*/C P*/A P/A* Mode 6 P*/A P*/A P*/A D P*/D P/C* C P*/C P*/C P*/A P*/A Mode 7 P P P P P P*/C P P Rev. 6.00 Feb 22, 2005 page 86 of 1484 REJ09B0103-0600 Section 3 MCU Operating Modes 3.5 Address Map in Each Operating Mode An address map of the H8S/2636 is shown in figure 3-1. An address map of the H8S/2638 and H8S/2639 is shown in figure 3-2. An address map of the H8S/2630 is shown in figure 3-3. An address map of the H8S/2635 is shown in figure 3-4. An address map of the H8S/2634 is shown in figure 3-5. The address space is 16 Mbytes in modes 4 to 7 (advanced modes). The address space is divided into eight areas for modes 4 to 7. For details, see section 7, Bus Controller. Rev. 6.00 Feb 22, 2005 page 87 of 1484 REJ09B0103-0600 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) Mode 7 (advanced single-chip mode) H'000000 H'000000 External address space On-chip ROM On-chip ROM H'01FFFF H'020000 H'FFAFFF H'FFB000 Reserved area H'FFDFFF H'FFE000 On-chip RAM* H'FFEFBF H'FFEFC0 H'FFF7FF External address space H'FFF800 Internal I/O registers H'FFFF3F H'FFFF40 H'FFFF5F External address space H'FFFF60 H'FFFFBF Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF H'FFDFFF H'FFE000 H'FFAFFF H'FFB000 H'01FFFF External address space Reserved area H'FFE000 On-chip RAM* On-chip RAM H'FFEFBF H'FFF800 Internal I/O registers H'FFFF3F H'FFFF60 H'FFFFBF Internal I/O registers H'FFFFC0 On-chip RAM H'FFFFFF H'FFEFBF H'FFEFC0 H'FFF7FF External address space H'FFF800 Internal I/O registers H'FFFF3F H'FFFF40 H'FFFF5F External address space H'FFFF60 H'FFFFBF Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF Note: * External addresses can be accessed by clearing th RAME bit in SYSCR to 0. Figure 3-1 Memory Map in Each Operating Mode in the H8S/2636 Rev. 6.00 Feb 22, 2005 page 88 of 1484 REJ09B0103-0600 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) Mode 7 (advanced single-chip mode) H'000000 H'000000 External address space On-chip ROM On-chip ROM H'03FFFF H'040000 H'FFAFFF H'FFB000 H'FFAFFF H'FFB000 H'03FFFF External address space H'FFB000 On-chip RAM* On-chip RAM* On-chip RAM H'FFEFBF H'FFEFC0 H'FFF7FF External address space H'FFF800 Internal I/O registers H'FFFF3F H'FFFF40 H'FFFF5F External address space H'FFFF60 H'FFFFBF Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF H'FFEFBF H'FFEFC0 H'FFF7FF External address space H'FFF800 Internal I/O registers H'FFFF3F H'FFFF40 H'FFFF5F External address space H'FFFF60 H'FFFFBF Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF H'FFEFBF H'FFF800 Internal I/O registers H'FFFF3F H'FFFF60 H'FFFFBF Internal I/O registers H'FFFFC0 On-chip RAM H'FFFFFF Note: * External addresses can be accessed by clearing th RAME bit in SYSCR to 0. Figure 3-2 Memory Map in Each Operating Mode in the H8S/2638 and H8S/2639 Rev. 6.00 Feb 22, 2005 page 89 of 1484 REJ09B0103-0600 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) Mode 7 (advanced single-chip mode) H'000000 H'000000 External address space On-chip ROM On-chip ROM H'05FFFF H'060000 H'FFAFFF H'FFB000 H'FFAFFF H'FFB000 H'05FFFF External address space H'FFB000 On-chip RAM* On-chip RAM* On-chip RAM H'FFEFBF H'FFEFC0 H'FFF7FF External address space H'FFF800 Internal I/O registers H'FFFF3F H'FFFF40 H'FFFF5F External address space H'FFFF60 H'FFFFBF Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF H'FFEFBF H'FFEFC0 H'FFF7FF External address space H'FFF800 Internal I/O registers H'FFFF3F H'FFFF40 H'FFFF5F External address space H'FFFF60 H'FFFFBF Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF H'FFEFBF H'FFF800 Internal I/O registers H'FFFF3F H'FFFF60 H'FFFFBF Internal I/O registers H'FFFFC0 On-chip RAM H'FFFFFF Note: * External addresses can be accessed by clearing th RAME bit in SYSCR to 0. Figure 3-3 Memory Map in Each Operating Mode in the H8S/2630 Rev. 6.00 Feb 22, 2005 page 90 of 1484 REJ09B0103-0600 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) Mode 7 (advanced single-chip mode) H'000000 H'000000 On-chip ROM On-chip ROM External address space H'02FFFF H'030000 Reserved area H'03FFFF H'040000 H'FFAFFF H'FFB000 Reserved area H'FFD7FF H'FFD800 On-chip RAM* H'FFEFBF H'FFEFC0 H'FFF7FF External address space H'FFF800 Internal I/O registers H'FFFF3F H'FFFF40 H'FFFF5F External address space H'FFFF60 H'FFFFBF Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF H'FFD7FF H'FFD800 On-chip RAM* H'FFEFBF H'FFEFC0 H'FFF7FF External address space H'FFF800 Internal I/O registers H'FFFF3F H'FFFF40 H'FFFF5F External address space H'FFFF60 H'FFFFBF Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF H'FFFF3F H'FFFF60 H'FFFFBF Internal I/O registers H'FFFFC0 On-chip RAM H'FFFFFF H'FFEFBF H'FFF800 Internal I/O registers H'FFAFFF H'FFB000 H'02FFFF External address space Reserved area H'FFD800 On-chip RAM Note: * External addresses can be accessed by clearing th RAME bit in SYSCR to 0. Figure 3-4 Memory Map in Each Operating Mode in the H8S/2635 Rev. 6.00 Feb 22, 2005 page 91 of 1484 REJ09B0103-0600 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) Mode 7 (advanced single-chip mode) H'000000 H'000000 On-chip ROM On-chip ROM H'01FFFF H'020000 External address space Reserved area H'01FFFF H'03FFFF H'040000 H'FFAFFF H'FFB000 Reserved area H'FFD7FF H'FFD800 On-chip RAM* H'FFEFBF H'FFEFC0 H'FFF7FF External address space H'FFF800 Internal I/O registers H'FFFF3F H'FFFF40 H'FFFF5F External address space H'FFFF60 H'FFFFBF Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF H'FFD7FF H'FFD800 H'FFAFFF H'FFB000 External address space Reserved area H'FFD800 On-chip RAM* H'FFEFBF H'FFEFC0 H'FFF7FF External address space H'FFF800 Internal I/O registers H'FFFF3F H'FFFF40 H'FFFF5F External address space H'FFFF60 H'FFFFBF Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF H'FFFF3F H'FFFF60 H'FFFFBF Internal I/O registers H'FFFFC0 On-chip RAM H'FFFFFF H'FFEFBF H'FFF800 Internal I/O registers On-chip RAM Note: * External addresses can be accessed by clearing th RAME bit in SYSCR to 0. Figure 3-5 Memory Map in Each Operating Mode in the H8S/2634 Rev. 6.00 Feb 22, 2005 page 92 of 1484 REJ09B0103-0600 Section 4 Exception Handling Section 4 Exception Handling 4.1 4.1.1 Overview Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, direct transition*, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times, in the program execution state. Exception handling sources, the stack structure, and the operation of the CPU vary depending on the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR. Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used with the other versions. Table 4-1 Priority High Exception Types and Priority Exception Type Reset Start of Exception Handling Trace*1 Direct transition*4 Interrupt Low Starts when execution of the current instruction or exception handling ends, if the trace (T) bit is set to 1 Starts when a direct transition occurs due to execution of a SLEEP instruction. Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued*2 Trap instruction (TRAPA)*3 Started by execution of a trap instruction (TRAPA) Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in program execution state. 4. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used with the other versions. Supported by the H8S/2635. Rev. 6.00 Feb 22, 2005 page 93 of 1484 REJ09B0103-0600 SER Starts immediately after a low-to-high transition at the pin, or when the watchdog overflows. The CPU enters the reset state when the pin is low. SER Section 4 Exception Handling 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps 2 and 3 above are carried out. 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4-1. Different vector addresses are assigned to different exception sources. Table 4-2 lists the exception sources and their vector addresses. Reset Trace Exception sources Interrupts External interrupts: NMI, IRQ5 to IRQ0 Internal interrupts: 49 (+3: Option) interrupt sources in on-chip supporting modules Trap instruction Figure 4-1 Exception Sources Rev. 6.00 Feb 22, 2005 page 94 of 1484 REJ09B0103-0600 Section 4 Exception Handling Table 4-2 Exception Vector Table Vector Address*1 Exception Source Reset Reserved for system use Vector Number 0 1 2 3 4 Advanced Mode H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 H'0058 to H'005B H'005C to H'005F H'0060 to H'0063 H'01FC to H'01FF Trace Direct Transition*3 External interrupt NMI Trap instruction (4 sources) 5 6 7 8 9 10 11 Reserved for system use 12 13 14 15 External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 16 17 18 19 20 21 22 23 Reserved for system use Internal interrupt*2 24 127 Notes: 1. Lower 16 bits of the address. 2. For details of internal interrupt vectors, see section 5.3.3, Interrupt Exception Handling Vector Table. 3. See section 23B.11, Direct Transition for details on direct transition. Subclock functions are available in the U-mask and W-mask versions, and H8S/2635 Group only. Rev. 6.00 Feb 22, 2005 page 95 of 1484 REJ09B0103-0600 Section 4 Exception Handling 4.2 4.2.1 Reset Overview A reset has the highest exception priority. pin goes low, all current operations are stopped, and this LSI enters reset state. A When the reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. The H8S/2636 can also be reset by overflow of the watchdog timer. For details see section 12, Watchdog Timer. 4.2.2 Reset Sequence pin goes low. pin low for at least 20 ms at power-up. To reset To ensure that this LSI is reset, hold the pin low for at least 20 states. during operation, hold the pin goes high after being held low for the necessary time, this LSI starts reset When the exception handling as follows. 1. The internal state of the CPU and the registers of the on-chip supporting modules are initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 4-2 and 4-3 show examples of the reset sequence. Rev. 6.00 Feb 22, 2005 page 96 of 1484 REJ09B0103-0600 SER SER This LSI enters reset state when the SER SER SER When the SER pin goes from low to high, reset exception handling starts. Section 4 Exception Handling Vector fetch Internal Prefetch of first program processing instruction RES Internal address bus (1) (3) (5) Internal read signal Internal write signal Internal data bus (2) High (4) (6) (1) (3) Reset exception handling vector address (when power-on reset, (1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) (5) Start address ((5) = (2) (4)) (6) First program instruction Figure 4-2 Reset Sequence (Modes 6 and 7) Rev. 6.00 Feb 22, 2005 page 97 of 1484 REJ09B0103-0600 Section 4 Exception Handling Vector fetch Internal processing Prefetch of first program instruction * * * RES Address bus (1) (3) (5) RD HWR, LWR High D15 to D0 (2) (4) (6) (1) (3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) (5) Start address ((5) = (2) (4)) (6) First program instruction Note: * 3 program wait states are inserted. Figure 4-3 Reset Sequence (Mode 4) 4.2.3 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). Rev. 6.00 Feb 22, 2005 page 98 of 1484 REJ09B0103-0600 Section 4 Exception Handling 4.2.4 State of On-Chip Supporting Modules after Reset Release After reset release, MSTPCRA to MSTPCRD are initialized to H'3F, H'FF, H'FF, and B'11*******1, respectively, and all modules except the DTC, enter module stop mode. Consequently, on-chip supporting module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited. Note: 1. The value of bits 5 to 0 is undefined. 4.3 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking. Table 4-3 shows the state of CCR and EXR after execution of trace exception handling. Interrupts are accepted even within the trace exception handling routine. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Table 4-3 Status of CCR and EXR after Trace Exception Handling CCR I 1 UI -- I2 to I0 -- EXR T 0 Interrupt Control Mode 0 2 Legend: 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution. Trace exception handling cannot be used. Rev. 6.00 Feb 22, 2005 page 99 of 1484 REJ09B0103-0600 Section 4 Exception Handling 4.4 Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ5 to IRQ0) and 49 internal sources in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), 16-bit timer-pulse unit (TPU), serial communication interface (SCI), data transfer controller (DTC), PC break controller (PBC), A/D converter, controller area network (HCAN), motor control PWM timer, and I2C bus interface (IIC). Each interrupt source has a separate vector address. NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. For details of interrupts, see section 5, Interrupt Controller. Notes: The DTC, PBC, and IIC are not implemented in the H8S/2635 Group. NMI (1) IRQ5 to IRQ0 (6) WDT*1 (2) TPU (26) SCI (12) DTC (1) PBC (1) A/D converter (1) Motor control PWM (2) HCAN (4)*3 IIC*2 (3) [Option] External interrupts Interrupts Internal interrupts Notes: Numbers in parentheses are the numbers of interrupt sources. 1. When the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. 2. I2C bus interface is available as an option in the H8S/2638, H8S/2639, and H8S/2630. 3. 2 sources in the H8S/2635 Group. Figure 4-4 Interrupt Sources and Number of Interrupts Rev. 6.00 Feb 22, 2005 page 100 of 1484 REJ09B0103-0600 Section 4 Exception Handling 4.5 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4-4 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4-4 Status of CCR and EXR after Trap Instruction Exception Handling CCR I 1 1 UI -- -- I2 to I0 -- -- EXR T -- 0 Interrupt Control Mode 0 2 Legend: 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution. Rev. 6.00 Feb 22, 2005 page 101 of 1484 REJ09B0103-0600 Section 4 Exception Handling 4.6 Stack Status after Exception Handling Figure 4-5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP SP CCR CCR* PC (16 bits) EXR Reserved* CCR CCR* PC (16 bits) (a) Interrupt control mode 0 Note: * Ignored on return. (b) Interrupt control mode 2 Figure 4-5 (1) Stack Status after Exception Handling (Normal Modes: Not Available in the Chip) SP SP CCR PC (24 bits) EXR Reserved* CCR PC (24 bits) (a) Interrupt control mode 0 Note: * Ignored on return. (b) Interrupt control mode 2 Figure 4-5 (2) Stack Status after Exception Handling (Advanced Modes) Rev. 6.00 Feb 22, 2005 page 102 of 1484 REJ09B0103-0600 Section 4 Exception Handling 4.7 Notes on Use of the Stack When accessing word data or longword data, the chip assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4-6 shows an example of what happens when the SP value is odd. CCR SP PC SP R1L PC H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFF SP TRAP instruction executed MOV.B R1L, @-ER7 SP set to H'FFFEFF Data saved above SP Contents of CCR lost Legend: CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4-6 Operation when SP Value Is Odd Rev. 6.00 Feb 22, 2005 page 103 of 1484 REJ09B0103-0600 Section 4 Exception Handling Rev. 6.00 Feb 22, 2005 page 104 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 5.1.1 Overview Features The chip controls interrupts by means of an interrupt controller. The interrupt controller has the following features: * Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). * Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. NMI is assigned the highest priority level of 8, and can be accepted at all times. * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * Seven external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ5 to IRQ0. * DTC control* DTC activation is performed by means of interrupts. Note: * The H8S/2635 Group is not equipped with a DTC. Rev. 6.00 Feb 22, 2005 page 105 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 5-1. INTM1, INTM0 SYSCR NMIEG NMI input IRQ input NMI input unit IRQ input unit ISR ISCR IER Priority determination I I2 to I0 Interrupt request Vector number CPU Internal interrupt request SWDTEND to RM0 IPR Interrupt controller CCR EXR Legend: ISCR: IER: ISR: IPR: SYSCR: IRQ sense control register IRQ enable register IRQ status register Interrupt priority register System control register Figure 5-1 Block Diagram of Interrupt Controller Rev. 6.00 Feb 22, 2005 page 106 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller 5.1.3 Pin Configuration Table 5-1 summarizes the pins of the interrupt controller. Table 5-1 Name Nonmaskable interrupt External interrupt requests 5 to 0 Interrupt Controller Pins Symbol NMI 0QRI I/O Input Function Nonmaskable external interrupt; rising or falling edge can be selected Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected to Input 5.1.4 Register Configuration Table 5-2 summarizes the registers of the interrupt controller. Table 5-2 Name System control register IRQ sense control register H IRQ sense control register L IRQ enable register IRQ status register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt priority register J Interrupt priority register K Interrupt priority register L Interrupt priority register M Interrupt Controller Registers Abbreviation SYSCR ISCRH ISCRL IER ISR IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRJ IPRK IPRL IPRM R/W R/W R/W R/W R/W R/(W)*2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'01 H'00 H'00 H'00 H'00 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 Address*1 H'FDE5 H'FE12 H'FE13 H'FE14 H'FE15 H'FEC0 H'FEC1 H'FEC2 H'FEC3 H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC9 H'FECA H'FECB H'FECC Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. 5QRI Rev. 6.00 Feb 22, 2005 page 107 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller 5.2 Register Descriptions Note: The H8S/2635 Group is not equipped with a DTC, a PC brake controller, or an HCAN1. 5.2.1 Bit System Control Register (SYSCR) : 7 MACS 0 R/W 3/4 3/4 0 6 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 3/4 0 R/W 2 3/4 3/4 0 1 0 RAME 1 R/W Initial value : R/W : SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control Register (SYSCR). SYSCR is initialized to H'01 by a reset and in hardware standby mode. SYSCR is not initialized in software standby mode. Bits 5 and 4--Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two interrupt control modes for the interrupt controller. Bit 5 INTM1 0 1 Bit 4 INTM0 0 1 0 1 Interrupt Control Mode 0 -- 2 -- Description Interrupts are controlled by I bit Setting prohibited Interrupts are controlled by bits I2 to I0, and IPR Setting prohibited (Initial value) Bit 3--NMI Edge Select (NMIEG): Selects the input edge for the NMI pin. Bit 3 NMIEG 0 1 Description Interrupt request generated at falling edge of NMI input Interrupt request generated at rising edge of NMI input (Initial value) Rev. 6.00 Feb 22, 2005 page 108 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller 5.2.2 Bit Interrupt Priority Registers A to H, J to M (IPRA to IPRH, IPRJ to IPRM) : 3/4 3/4 0 7 6 IPR6 1 R/W 5 IPR5 1 R/W 4 IPR4 1 R/W 3/4 3/4 0 3 2 IPR2 1 R/W 1 IPR1 1 R/W 0 IPR0 1 R/W Initial value : R/W : The IPR registers are twelve 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between IPR settings and interrupt sources is shown in table 5-3. The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI. The IPR registers are initialized to H'77 by a reset and in hardware standby mode. Bits 7 and 3--Reserved: These bits are always read as 0 and cannot be modified. Table 5-3 Correspondence between Interrupt Sources and IPR Settings Bits Register IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRJ IPRK IPRL IPRM 6 to 4 IRQ0 IRQ2 IRQ3 --*1 Watchdog timer 0 PC break*3 TPU channel 0 TPU channel 2 TPU channel 4 --*1 SCI channel 1 --*1 PWM channel 1, 2 HCAN channel 1*3 2 to 0 IRQ1 IRQ4 IRQ5 DTC*3 --*1 A/D converter, watchdog timer 1 TPU channel 1 TPU channel 3 TPU channel 5 SCI channel 0 SCI channel 2 IIC (Option)*2 HCAN channel 0 Notes: 1. Reserved. These bits are always read as 1 and cannot be modified. 2. I2C bus interface is available as an option in the H8S/2638, H8S/2639, and H8S/2630. The IIC bit becomes reserved bit when this optional feature is not used. 3. The PC break, DTC, and HCAN channel 1 are reserved in the H8S/2635 Group. Rev. 6.00 Feb 22, 2005 page 109 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller As shown in table 5-3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority level, level 7, by setting H'7. When interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to the CPU. 5.2.3 Bit IRQ Enable Register (IER) : 3/4 0 R/W 7 3/4 0 R/W 6 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W Initial value : R/W : IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ5 to IRQ0. IER is initialized to H'00 by a reset and in hardware standby mode. Bits 7 and 6--Reserved: These bits are always read as 0, and should only be written with 0. Bits 5 to 0--IRQ5 to IRQ0 Enable (IRQ5E to IRQ0E): These bits select whether IRQ5 to IRQ0 are enabled or disabled. Bit n IRQnE 0 1 Description IRQn interrupts disabled IRQn interrupts enabled (n = 5 to 0) (Initial value) Rev. 6.00 Feb 22, 2005 page 110 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller 5.2.4 ISCRH Bit IRQ Sense Control Registers H and L (ISCRH, ISCRL) : 15 3/4 0 14 3/4 0 13 3/4 0 12 3/4 0 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : R/W : R/W R/W R/W R/W ISCRL Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : R/W : The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or to . both edge detection, or level sensing, for the input at pins The ISCR registers are initialized to H'0000 by a reset and in hardware standby mode. Bits 15 to 12--Reserved: These bits are always read as 0, and should only be written with 0. Bits 11 to 0--IRQ5 Sense Control A and B (IRQ5SCA, IRQ5SCB) to IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB) Bits 11 to 0 IRQ5SCB to IRQ0SCB 0 IRQ5SCA to IRQ0SCA 0 1 1 0 1 Description 0QRI 5QRI Interrupt request generated at Interrupt request generated at both falling and rising edges of to input 0QRI 5QRI Rev. 6.00 Feb 22, 2005 page 111 of 1484 REJ09B0103-0600 0QRI 5QRI Interrupt request generated at rising edge of to 0QRI 5QRI Interrupt request generated at falling edge of 0QRI 5QRI to input low level (initial value) to input input Section 5 Interrupt Controller 5.2.5 Bit IRQ Status Register (ISR) : 3/4 0 R/(W)* 7 3/4 0 R/(W)* 6 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* Initial value : R/W : Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ5 to IRQ0 interrupt requests. ISR is initialized to H'00 by a reset and in hardware standby mode. They are not initialized in software standby mode. Bits 7 and 6--Reserved: These bits are always read as 0. Bits 5 to 0--IRQ5 to IRQ0 Flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ5 to IRQ0 interrupt requests. Rev. 6.00 Feb 22, 2005 page 112 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller Bit n IRQnF 0 Description [Clearing conditions] * * * * 1 (Initial value) Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and input is high When IRQn interrupt exception handling is executed when falling, rising, or bothedge detection is set (IRQnSCB = 1 or IRQnSCA = 1) When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 When 0) input goes low when low-level detection is set (IRQnSCB = IRQnSCA = input when falling edge detection is set input when rising edge detection is set input when both-edge detection is set (n = 5 to 0) nQRI [Setting conditions] nQRI * * * * nQRI When a falling or rising edge occurs in (IRQnSCB = IRQnSCA = 1) nQRI When a rising edge occurs in (IRQnSCB = 1, IRQnSCA = 0) nQRI When a falling edge occurs in (IRQnSCB = 0, IRQnSCA = 1) Rev. 6.00 Feb 22, 2005 page 113 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller 5.3 Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ5 to IRQ0) and internal interrupts (49 sources). Note: The H8S/2635 Group is not equipped with a DTC, a PC brake controller, or an HCAN1. The H8S/2635 Group has 45 sources of internal interrupt. 5.3.1 External Interrupts There are seven external interrupts: NMI and IRQ5 to IRQ0. Of these, NMI and IRQ5 to IRQ0 can be used to restore the chip from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. The vector number for NMI interrupt exception handling is 7. 5QRI IRQ5 to IRQ0 Interrupts: Interrupts IRQ5 to IRQ0 are requested by an input signal at pins to . Interrupts IRQ5 to IRQ0 have the following features: 0QRI * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins to . * Enabling or disabling of interrupt requests IRQ5 to IRQ0 can be selected with IER. * The interrupt priority level can be set with IPR. * The status of interrupt requests IRQ5 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. 0QRI 5QRI Rev. 6.00 Feb 22, 2005 page 114 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller A block diagram of interrupts IRQ5 to IRQ0 is shown in figure 5-2. IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn S R Q IRQn interrupt request input Clear signal Note: n = 5 to 0 Figure 5-2 Block Diagram of Interrupts IRQ5 to IRQ0 Figure 5-3 shows the timing of setting IRQnF. B IRQn input pin IRQnF Figure 5-3 Timing of Setting IRQnF The vector numbers for IRQ5 to IRQ0 interrupt exception handling are 21 to 16. Detection of IRQ5 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 and use the pin as an I/O pin for another function. Rev. 6.00 Feb 22, 2005 page 115 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller 5.3.2 Internal Interrupts There are 49 sources for internal interrupts from on-chip supporting modules. * For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. * The interrupt priority level can be set by means of IPR. * The DTC can be activated by a TPU, SCI, or other interrupt request. When the DTC is activated by an interrupt, the interrupt control mode and interrupt mask bits are not affected. 5.3.3 Interrupt Exception Handling Vector Table Table 5-4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of the IPR. The situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 5-4. Rev. 6.00 Feb 22, 2005 page 116 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address*1 Vector Number 7 16 17 18 19 20 21 -- DTC*3 Watchdog timer 0 -- 22 23 24 25 26 Advanced Mode H'001C H'0040 H'0044 H'0048 H'004C H'0050 H'0054 H'0058 H'005C H'0060 H'0064 H'0068 H'006C H'0070 H'0074 H'0078 H'007C H'0080 H'0084 H'0088 H'008C H'0090 H'0094 to H'009C -- Low -- IPRF6 to 4 IPRA6 to 4 IPRA2 to 0 IPRB6 to 4 IPRB2 to 0 -- IPRC2 to 0 IPRD6 to 4 -- IPRE6 to 4 IPRE2 to 0 IPR Priority High Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Reserved for system use SWDTEND (software activation interrupt end) WOVI0 (interval timer) Reserved for system use PC break ADI (A/D conversion end) WOVI1 (interval timer) Reserved for system use TGI0A (TGR0A input capture/compare match) TGI0B (TGR0B input capture/compare match) TGI0C (TGR0C input capture/compare match) TGI0D (TGR0D input capture/compare match) TCI0V (overflow 0) Reserved for system use Origin of Interrupt Source External pin 27 PC break controller*3 A/D Watchdog timer 1 -- TPU channel 0 28 29 30 31 32 33 34 35 36 -- 37 to 39 Rev. 6.00 Feb 22, 2005 page 117 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller Vector Address*1 Vector Number 40 41 42 43 TPU channel 2 44 45 46 47 TPU channel 3 48 49 50 51 52 -- 53 to 55 56 57 58 59 Advanced Mode H'00A0 H'00A4 H'00A8 H'00AC H'00B0 H'00B4 H'00B8 H'00BC H'00C0 H'00C4 H'00C8 H'00CC H'00D0 H'00D4 to H'00DC H'00E0 H'00E4 H'00E8 H'00EC Low -- IPRG2 to 0 IPRG6 to 4 IPR IPRF2 to 0 Priority High Interrupt Source TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow 2) TCI2U (underflow 2) TGI3A (TGR3A input capture/compare match) TGI3B (TGR3B input capture/compare match) TGI3C (TGR3C input capture/compare match) TGI3D (TGR3D input capture/compare match) TCI3V (overflow 3) Reserved for system use Origin of Interrupt Source TPU channel 1 TGI4A (TGR4A input capture/compare match) TGI4B (TGR4B input capture/compare match) TCI4V (overflow 4) TCI4U (underflow 4) TPU channel 4 IPRH6 to 4 Rev. 6.00 Feb 22, 2005 page 118 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller Vector Address*1 Vector Number 60 61 62 63 -- 64 to 79 80 81 82 83 SCI channel 1 84 85 86 87 SCI channel 2 88 89 90 91 -- 92 to 99 100 101 102 103 Advanced Mode H'00F0 H'00F4 H'00F8 H'00FC H'0100 to H'013C H'0140 H'0144 H'0148 H'014C H'0150 H'0154 H'0158 H'015C H'0160 H'0164 H'0168 H'016C H'0170 to H'018C H'0190 H'0194 H'0198 H'019C Low -- IPRK2 to 0 IPRK6 to 4 -- IPR IPRH2 to 0 Priority High Interrupt Source TGI5A (TGR5A input capture/compare match) TGI5B (TGR5B input capture/compare match) TCI5V (overflow 5) TCI5U (underflow 5) Reserved for system use Origin of Interrupt Source TPU channel 5 ERI0 (receive error 0) RXI0 (reception completed 0) TXI0 (transmit data empty 0) TEI0 (transmission end 0) ERI1 (receive error 1) RXI1 (reception completed 1) TXI1 (transmit data empty 1) TEI1 (transmission end 1) ERI2 (receive error 2) RXI2 (reception completed 2) TXI2 (transmit data empty 2) TEI2 (transmission end 2) Reserved for system use SCI channel 0 IPRJ2 to 0 I2CI0 (1-byte transmission/ reception completed) DDCSW1 (format switch) I CI1 Reserved for system use 2 I2C channel 0 (option)*2 IC channel 1 (option)*2 2 IPRL2 to 0 Rev. 6.00 Feb 22, 2005 page 119 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller Vector Address*1 Vector Number 104 105 106 107 108 109 110 111 Advanced Mode H'01A0 H'01A4 H'01A8 H'01AC H'01B0 H'01B4 H'01B8 H'01BC Low IPRM2 to 0 IPR IPRM6 to 4 Priority High Interrupt Source PWM1 PWM2 ERS0, OVR0, RM1, SLE0, RM0 ERS0, OVR0, RM1, SLE0, RM0 Reserved for system use Origin of Interrupt Source PWM channel 1 PWM channel 2 3 HCAN1* HCAN0 -- Notes: 1. Lower 16 bits of the start address. 2. I2C is available as an option in the H8S/2638, H8S/2639, and H8S/2630 only. The product equipped with the I2C bus interface is the W-mask version. 3. The DTC, PC break, and HCAN1 interrupts are reserved in the H8S/2635 Group. 5.4 5.4.1 Interrupt Operation Interrupt Control Modes and Interrupt Operation Interrupt operations in the chip differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 5-5 shows the interrupt control modes. The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated by the I bit in the CPU's CCR, and bits I2 to I0 in EXR. Rev. 6.00 Feb 22, 2005 page 120 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller Table 5-5 Interrupt Control Modes Interrupt Mask Bits Description I -- I2 to I0 Interrupt mask control is performed by the I bit. Setting prohibited 8-level interrupt mask control is performed by bits I2 to I0. 8 priority levels can be set with IPR. Setting prohibited SYSCR Interrupt Priority Setting Control Mode INTM1 INTM0 Registers 0 -- 2 1 0 0 1 0 -- -- IPR -- 1 -- -- Figure 5-4 shows a block diagram of the priority decision circuit. Interrupt control mode 0 I Interrupt acceptance control Interrupt source Default priority determination 8-level mask control Vector number IPR I2 to I0 Interrupt control mode 2 Figure 5-4 Block Diagram of Interrupt Control Operation Rev. 6.00 Feb 22, 2005 page 121 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5-6 shows the interrupts selected in each interrupt control mode. Table 5-6 Interrupts Selected in Each Interrupt Control Mode (1) Interrupt Mask Bits Interrupt Control Mode 0 2 Legend: *: Don't care I 0 1 * Selected Interrupts All interrupts NMI interrupts All interrupts (2) 8-Level Control In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level. Table 5-7 Interrupts Selected in Each Interrupt Control Mode (2) Selected Interrupts All interrupts Highest-priority-level (IPR) interrupt whose priority level is greater than the mask level (IPR > I2 to I0). Interrupt Control Mode 0 2 Rev. 6.00 Feb 22, 2005 page 122 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller (3) Default Priority Determination When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 5-8 shows operations and control signal functions in each interrupt control mode. Table 5-8 Interrupt Control Mode Operations and Control Signal Functions in Each Interrupt Control Mode Setting INTM1 INTM0 Interrupt Acceptance Control I 8-Level Control I2 to I0 IPR Default Priority Determination T (Trace) 0 2 0 1 0 0 X IM --*1 X -- IM --*2 PR -- T Legend: : Interrupt operation control performed X: No operation (All interrupts enabled). IM: Used as interrupt mask bit PR: Sets priority. --: Not used. Notes: 1. Set to 1 when interrupt is accepted. 2. Keep the initial setting. Rev. 6.00 Feb 22, 2005 page 123 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller 5.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU's CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Figure 5-5 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. [3] Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. Rev. 6.00 Feb 22, 2005 page 124 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller Program execution status Interrupt generated? Yes Yes No NMI No No I=0 Yes Hold pending No IRQ0 Yes No IRQ1 Yes HCAN Yes Save PC and CCR I1 Read vector address Branch to interrupt handling routine Figure 5-5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 6.00 Feb 22, 2005 page 125 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller 5.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5-6 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5-4 is selected. [3] Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. Rev. 6.00 Feb 22, 2005 page 126 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller Program execution status Interrupt generated? Yes Yes NMI No Level 7 interrupt? Yes Mask level 6 or below? Yes No No No Level 6 interrupt? Yes Mask level 5 or below? Yes No Level 1 interrupt? No Yes No Mask level 0? Yes No Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5-6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 Rev. 6.00 Feb 22, 2005 page 127 of 1484 REJ09B0103-0600 5.4.4 Interrupt acceptance Instruction prefetch Stack Vector fetch Internal operation Internal operation Interrupt service routine instruction prefetch Interrupt level determination Wait for end of instruction Section 5 Interrupt Controller Interrupt request signal Rev. 6.00 Feb 22, 2005 page 128 of 1484 REJ09B0103-0600 (1) (3) (7) (9) (11) Internal address bus (5) (13) Interrupt Exception Handling Sequence Internal read signal Internal write signal (2) (8) Internal data us (4) (6) (10) (12) (14) Figure 5-7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Figure 5-7 Interrupt Exception Handling (1) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address) (2) (4) Instruction code (Not executed) (3) Instruction prefetch address (Not executed) (5) SP-2 (7) SP-4 (6) (8) Saved PC and saved CCR (9) (11) Vector address (10) (12) Interrupt handling routine start address (vector address contents) (13) Interrupt handling routine start address ((13) = (10) (12)) (14) First instruction of interrupt handling routine Section 5 Interrupt Controller 5.4.5 Interrupt Response Times The chip is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5-9 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5-9 are explained in table 5-10. Table 5-9 Interrupt Response Times Normal Mode*5 No. 1 2 3 4 5 6 Execution Status Interrupt priority determination *1 INTM1 = 0 3 INTM1 = 1 3 Advanced Mode INTM1 = 0 3 INTM1 = 1 3 1 to Number of wait states until executing 1 to 2 instruction ends* (19 + 2 * SI) (19 + 2 * SI) PC, CCR, EXR stack save Vector fetch Instruction fetch *3 *4 Internal processing 2 * SK SI 2 * SI 2 11 to 31 3 * SK SI 2 * SI 2 12 to 32 1 to 1 to (19 + 2 * SI) (19 + 2 * SI) 2 * SK 2*SI 2 * SI 2 12 to 32 3 * SK 2*SI 2 * SI 2 13 to 33 Total (using on-chip memory) Notes: 1. 2. 3. 4. 5. Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. Not implemented in the chip. Rev. 6.00 Feb 22, 2005 page 129 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller Table 5-10 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8 Bit Bus Symbol Instruction fetch Branch address read Stack manipulation SI SJ SK Internal Memory 1 2-State Access 4 3-State Access 6 + 2m 16 Bit Bus 2-State Access 2 3-State Access 3+m Legend: m: Number of wait states in an external device access. 5.5 5.5.1 Usage Notes Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5-8 shows an example in which the TCIEV bit in the TPU's TIER register is cleared to 0. Rev. 6.00 Feb 22, 2005 page 130 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller TIER write cycle by CPU TCFV exception handling B Internal address bus TIER address Internal write signal TCIEV TCFV TCFV interrupt signal Figure 5-8 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 5.5.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.5.3 Times when Interrupts Are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. Rev. 6.00 Feb 22, 2005 page 131 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller 5.5.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 5.5.5 IRQ Interrupts QRI pin is synchronized with the clock. When operating by clock input, acceptance of input to an In software standby mode, the input is accepted asynchronously. For details on the input conditions, see section 24.5.2, Control Signal Timing. 5.5.6 Notes on Use of NMI Interrupt When the system is operating normally under conditions conforming to the specified electrical properties, exception processing by the on-chip interrupt controller linked to the CPU is used to execute the NMI interrupt. When operation is not normal (runaway status) due to a software problem or abnormal input to one of the LSI's pins, no operations can be guaranteed, including the NMI interrupt. In such cases it is possible to cause the LSI to return to normal program execution by applying an external reset. Rev. 6.00 Feb 22, 2005 page 132 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller 5.6 DTC Activation by Interrupt Note: The DTC is not implemented in the H8S/2635 Group. 5.6.1 Overview The DTC can be activated by an interrupt. In this case, the following options are available: * Interrupt request to CPU * Activation request to DTC * Selection of a number of the above For details of interrupt requests that can be used with to activate the DTC, see section 8, Data Transfer Controller (DTC). 5.6.2 Block Diagram Figure 5-9 shows a block diagram of the DTC interrupt controller. Interrupt request IRQ interrupt Interrupt source clear signal Selection circuit Select signal Clear signal DTCER DTC activation request vector number Control logic Clear signal DTC On-chip supporting module DTVECR SWDTE clear signal Determination of priority Interrupt controller CPU interrupt request vector number CPU I, I2 to I0 Figure 5-9 Interrupt Control for DTC Rev. 6.00 Feb 22, 2005 page 133 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller 5.6.3 Operation The interrupt controller has three main functions in DTC control. (1) Selection of Interrupt Source: Interrupt factors are selected as DTC activation request or CPU interrupt request by the DTCE bit of DTCERA to DTCERG of DTC. By specifying the DISEL bit of the DTC's MRB, it is possible to clear the DTCE bit to 0 after DTC data transfer, and request a CPU interrupt. If DTC carries out the designate number of data transfers and the transfer counter reads 0, after DTC data transfer, the DTCE bit is also cleared to 0, and a CPU interrupt requested. (2) Determination of Priority: The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 8.3.3, DTC Vector Table for the respective priority. (3) Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. Table 5-11 shows the interrupt factor clear control and selection of interrupt factors by specification of the DTCE bit of DTCERA to DTCERG of DTC, and the DISEL bit of DTC's MRB. Rev. 6.00 Feb 22, 2005 page 134 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller Table 5-11 Interrupt Source Selection and Clearing Control Settings DTC DTCE 0 1 DISEL * 0 1 Interrupt Source Selection/Clearing Control DTC X CPU X Legend: : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used. The interrupt source is not cleared. X : The relevant bit cannot be used. * : Don't care (4) Notes on Use: SCI and A/D converter interrupt sources are cleared when the DTC reads or writes to the prescribed register. Rev. 6.00 Feb 22, 2005 page 135 of 1484 REJ09B0103-0600 Section 5 Interrupt Controller Rev. 6.00 Feb 22, 2005 page 136 of 1484 REJ09B0103-0600 Section 6 PC Break Controller (PBC) Section 6 PC Break Controller (PBC) Note: The H8S/2635 Group is not equipped with a PBC. 6.1 Overview The PC break controller (PBC) provides functions that simplify program debugging. Using these functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator. Four break conditions can be set in the PBC: instruction fetch, data read, data write, and data read/write. 6.1.1 Features The PC break controller has the following features: * Two break channels (A and B) * The following can be set as break compare conditions: 24 address bits Bit masking possible Bus cycle Instruction fetch Data access: data read, data write, data read/write Bus master Either CPU or CPU/DTC can be selected * The timing of PC break exception handling after the occurrence of a break condition is as follows: Immediately before execution of the instruction fetched at the set address (instruction fetch) Immediately after execution of the instruction that accesses data at the set address (data access) * Module stop mode can be set The initial setting is for PBC operation to be halted. Register access is enabled by clearing module stop mode. Rev. 6.00 Feb 22, 2005 page 137 of 1484 REJ09B0103-0600 Section 6 PC Break Controller (PBC) 6.1.2 Block Diagram Figure 6-1 shows a block diagram of the PC break controller. BARA BCRA Output control Mask control Comparator Match signal Internal address Access status Control logic PC break interrupt Comparator Match signal Control logic Output control Mask control BARB BCRB Figure 6-1 Block Diagram of PC Break Controller Rev. 6.00 Feb 22, 2005 page 138 of 1484 REJ09B0103-0600 Section 6 PC Break Controller (PBC) 6.1.3 Register Configuration Table 6-1 shows the PC break controller registers. Table 6-1 PC Break Controller Registers Initial Value Name Break address register A Break address register B Break control register A Break control register B Module stop control register C Abbreviation BARA BARB BCRA BCRB MSTPCRC R/W R/W R/W R/(W)*2 R/(W)*2 R/W Reset H'XX000000 H'XX000000 H'00 H'00 H'FF Address*1 H'FE00 H'FE04 H'FE08 H'FE09 H'FDEA Notes: 1. Lower 16 bits of the address. 2. Only a 0 may be written to this bit to clear the flag. 6.2 6.2.1 Bit Register Descriptions Break Address Register A (BARA) 31 ... ... 24 23 22 21 20 19 18 17 16 ... 7 6 5 4 3 2 1 0 3/4 Read/Write 3/4 3/4 BAA BAA BAA BAA BAA BAA BAA BAA . . . BAA BAA BAA BAA BAA BAA BAA BAA 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 Initial value Unde- . . . Unde- 0 ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fined fined ... R/W R/W R/W R/W R/W R/W R/W R/W . . . R/W R/W R/W R/W R/W R/W R/W R/W 3/4 BARA is a 32-bit readable/writable register that specifies the channel A break address. BAA23 to BAA0 are initialized to H'000000 by a reset and in hardware standby mode. Bits 31 to 24--Reserved: These bits return an undefined value if read, and cannot be modified. Bits 23 to 0--Break Address A23 to A0 (BAA23 to BAA0): These bits hold the channel A PC break address. Rev. 6.00 Feb 22, 2005 page 139 of 1484 REJ09B0103-0600 Section 6 PC Break Controller (PBC) 6.2.2 Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 6.2.3 Bit Break Control Register A (BCRA) 7 CMFA 6 CDA 0 R/W 5 4 3 2 1 0 BIEA 0 R/W BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial value Read/Write 0 R/(W)* Note: * Only a 0 may be written to this bit to clear the flag. BCRA is an 8-bit readable/writable register that controls channel A PC breaks. BCRA (1) selects the break condition bus master, (2) specifies bits subject to address comparison masking, and (3) specifies whether the break condition is applied to an instruction fetch or a data access. It also contains a condition match flag. BCRA is initialized to H'00 by a reset and in hardware standby mode. Bit 7--Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is satisfied. This flag is not cleared to 0. Bit 7 CMFA 0 1 Description [Clearing condition] * * When 0 is written to CMFA after reading CMFA = 1 When a condition set for channel A is satisfied (Initial value) [Setting condition] Rev. 6.00 Feb 22, 2005 page 140 of 1484 REJ09B0103-0600 Section 6 PC Break Controller (PBC) Bit 6--CPU Cycle/DTC Cycle Select A (CDA): Selects the channel A break condition bus master. Bit 6 CDA 0 1 Description PC break is performed when CPU is bus master PC break is performed when CPU or DTC is bus master (Initial value) Bits 5 to 3--Break Address Mask Register A2 to A0 (BAMRA2 to BAMRA0): These bits specify which bits of the break address (BAA23 to BAA0) set in BARA are to be masked. Bit 5 Bit 4 Bit 3 BAMRA2 BAMRA1 BAMRA0 Description 0 0 0 1 1 0 1 1 0 0 1 1 0 1 All BARA bits are unmasked and included in break conditions (Initial value) BAA0 (lowest bit) is masked, and not included in break conditions BAA1, BAA0 (lower 2 bits) are masked, and not included in break conditions BAA2 to BAA0 (lower 3 bits) are masked, and not included in break conditions BAA3 to BAA0 (lower 4 bits) are masked, and not included in break conditions BAA7 to BAA0 (lower 8 bits) are masked, and not included in break conditions BAA11 to BAA0 (lower 12 bits) are masked, and not included in break conditions BAA15 to BAA0 (lower 16 bits) are masked, and not included in break conditions Rev. 6.00 Feb 22, 2005 page 141 of 1484 REJ09B0103-0600 Section 6 PC Break Controller (PBC) Bits 2 and 1--Break Condition Select A (CSELA1, CSELA0): These bits selection an instruction fetch, data read, data write, or data read/write cycle as the channel A break condition. Bit 2 CSELA1 0 1 Bit 1 CSELA0 0 1 0 1 Description Instruction fetch is used as break condition Data read cycle is used as break condition Data write cycle is used as break condition Data read/write cycle is used as break condition (Initial value) Bit 0--Break Interrupt Enable A (BIEA): Enables or disables channel A PC break interrupts. Bit 0 BIEA 0 1 Description PC break interrupts are disabled PC break interrupts are enabled (Initial value) 6.2.4 Break Control Register B (BCRB) BCRB is the channel B break control register. The bit configuration is the same as for BCRA. 6.2.5 Bit Initial value Read/Write Module Stop Control Register C (MSTPCRC) 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 MSTPCRC is an 8-bit readable/writable register that performs module stop mode control. When the MSTPC4 bit is set to 1, PC break controller operation is stopped at the end of the bus cycle, and module stop mode is entered. Register read/write accesses are not possible in module stop mode. For details, see section 23A.5, 23B.5, Module Stop Mode. MSTPCRC is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Rev. 6.00 Feb 22, 2005 page 142 of 1484 REJ09B0103-0600 Section 6 PC Break Controller (PBC) Bit 4--Module Stop (MSTPC4): Specifies the PC break controller module stop mode. Bit 4 MSTPC4 0 1 Description PC break controller module stop mode is cleared PC break controller module stop mode is set (Initial value) 6.3 Operation The operation flow from break condition setting to PC break interrupt exception handling is shown in section 6.3.1, PC Break Interrupt Due to Instruction Fetch, and 6.3.2, PC Break Interrupt Due to Data Access, taking the example of channel A. 6.3.1 PC Break Interrupt Due to Instruction Fetch (1) Initial settings Set the break address in BARA. For a PC break caused by an instruction fetch, set the address of the first instruction byte as the break address. Set the break conditions in BCRA. BCRA bit 6 (CDA): With a PC break caused by an instruction fetch, the bus master must be the CPU. Set 0 to select the CPU. BCRA bits 5 to 3 (BAMA2 to BAMA0): Set the address bits to be masked. BCRA bits 2, 1 (CSELA1, CSELA0): Set 00 to specify an instruction fetch as the break condition. BCRA bit 0 (BIEA): Set to 1 to enable break interrupts. (2) Satisfaction of break condition When the instruction at the set address is fetched, a PC break request is generated immediately before execution of the fetched instruction, and the condition match flag (CMFA) is set. (3) Interrupt handling After priority determination by the interrupt controller, PC break interrupt exception handling is started. Rev. 6.00 Feb 22, 2005 page 143 of 1484 REJ09B0103-0600 Section 6 PC Break Controller (PBC) 6.3.2 PC Break Interrupt Due to Data Access (1) Initial settings Set the break address in BARA. For a PC break caused by a data access, set the target ROM, RAM, I/O, or external address space address as the break address. Stack operations and branch address reads are included in data accesses. Set the break conditions in BCRA. BCRA bit 6 (CDA): Select the bus master. BCRA bits 5 to 3 (BAMA2 to BAMA0): Set the address bits to be masked. BCRA bits 2, 1 (CSELA1, CSELA0): Set 01, 10, or 11 to specify data access as the break condition. BCRA bit 0 (BIEA): Set to 1 to enable break interrupts. (2) Satisfaction of break condition After execution of the instruction that performs a data access on the set address, a PC break request is generated and the condition match flag (CMFA) is set. (3) Interrupt handling After priority determination by the interrupt controller, PC break interrupt exception handling is started. 6.3.3 Notes on PC Break Interrupt Handling (1) The PC break interrupt is shared by channels A and B. The channel from which the request was issued must be determined by the interrupt handler. (2) The CMFA and CMFB flags are not cleared to 0, so 0 must be written to CMFA or CMFB after first reading the flag while it is set to 1. If the flag is left set to 1, another interrupt will be requested after interrupt handling ends. (3) A PC break interrupt generated when the DTC is the bus master is accepted after the bus has been transferred to the CPU by the bus controller. Rev. 6.00 Feb 22, 2005 page 144 of 1484 REJ09B0103-0600 Section 6 PC Break Controller (PBC) 6.3.4 Operation in Transitions to Power-Down Modes The operation when a PC break interrupt is set for an instruction fetch at the address after a SLEEP instruction is shown below. (1) When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to sleep mode, or from subactive mode* to subsleep mode*: After execution of the SLEEP instruction, a transition is not made to sleep mode or subsleep mode*, and PC break interrupt handling is executed. After execution of PC break interrupt handling, the instruction at the address after the SLEEP instruction is executed (figure 6-2 (A)). (2) When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to subactive mode*: After execution of the SLEEP instruction, a transition is made to subactive mode* via direct transition exception handling. After the transition, PC break interrupt handling is executed, then the instruction at the address after the SLEEP instruction is executed (figure 6-2 (B)). (3) When the SLEEP instruction causes a transition from subactive mode* to high-speed (medium-speed) mode: After execution of the SLEEP instruction, and following the clock oscillation settling time, a transition is made to high-speed (medium-speed) mode via direct transition exception handling. After the transition, PC break interrupt handling is executed, then the instruction at the address after the SLEEP instruction is executed (figure 6-2 (C)). (4) When the SLEEP instruction causes a transition to software standby mode or watch mode*: After execution of the SLEEP instruction, a transition is made to the respective mode, and PC break interrupt handling is not executed. However, the CMFA or CMFB flag is set (figure 6-2 (D)). Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions only. Rev. 6.00 Feb 22, 2005 page 145 of 1484 REJ09B0103-0600 Section 6 PC Break Controller (PBC) SLEEP instruction execution SLEEP instruction execution SLEEP instruction execution SLEEP instruction execution PC break exception handling System clock subclock* Subclock* system clock, oscillation settling time Transition to respective mode (D) Execution of instruction after sleep instruction (A) Direct transition* exception handling Direct transition* exception handling Subactive* mode PC break exception handling High-speed (medium-speed) mode PC break exception handling Execution of instruction after sleep instruction (B) Execution of instruction after sleep instruction (C) Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions only. Figure 6-2 Operation in Power-Down Mode Transitions 6.3.5 PC Break Operation in Continuous Data Transfer If a PC break interrupt is generated when the following operations are being performed, exception handling is executed on completion of the specified transfer. (1) When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction: PC break exception handling is executed after all data transfers have been completed and the EEPMOV.B instruction has ended. (2) When a PC break interrupt is generated at a DTC transfer address:31 PC break exception handling is executed after the DTC has completed the specified number of data transfers, or after data for which the DISEL bit is set to 1 has been transferred. Rev. 6.00 Feb 22, 2005 page 146 of 1484 REJ09B0103-0600 Section 6 PC Break Controller (PBC) 6.3.6 When Instruction Execution Is Delayed by One State Caution is required in the following cases, as instruction execution is one state later than usual. (1) When the PBC is enabled (i.e. when the break interrupt enable bit is set to 1), execution of a one-word branch instruction (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, or RTS) located in onchip ROM or RAM is always delayed by one state. (2) When break interruption by instruction fetch is set, the set address indicates on-chip ROM or RAM space, and that address is used for data access, the instruction that executes the data access is one state later than in normal operation. (3) When break interruption by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction has one of the addressing modes shown below, and that address indicates on-chip ROM or RAM, and that address is used for data access, the instruction will be one state later than in normal operation. @ERn, @(d:16,ERn), @(d:32,ERn), @-ERn/ERn+, @aa:8, @aa:24, @aa:32, @(d:8,PC), @(d:16,PC), @@aa:8 (4) When break interruption by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction is NOP or SLEEP, or has #xx,Rn as its addressing mode, and that instruction is located in on-chip ROM or RAM, the instruction will be one state later than in normal operation. Rev. 6.00 Feb 22, 2005 page 147 of 1484 REJ09B0103-0600 Section 6 PC Break Controller (PBC) 6.3.7 Additional Notes (1) When a PC break is set for an instruction fetch at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction: Even if the instruction at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction is fetched, it is not executed, and so a PC break interrupt is not generated by the instruction fetch at the next address. (2) When the I bit is set by an LDC, ANDC, ORC, or XORC instruction, a PC break interrupt becomes valid two states after the end of the executing instruction. If a PC break interrupt is set for the instruction following one of these instructions, since interrupts, including NMI, are disabled for a 3-state period in the case of LDC, ANDC, ORC, and XORC, the next instruction is always executed. For details, see section 5, Interrupt Controller. (3) When a PC break is set for an instruction fetch at the address following a Bcc instruction: A PC break interrupt is generated if the instruction at the next address is executed in accordance with the branch condition, but is not generated if the instruction at the next address is not executed. (4) When a PC break is set for an instruction fetch at the branch destination address of a Bcc instruction: A PC break interrupt is generated if the instruction at the branch destination is executed in accordance with the branch condition, but is not generated if the instruction at the branch destination is not executed. Rev. 6.00 Feb 22, 2005 page 148 of 1484 REJ09B0103-0600 Section 7 Bus Controller Section 7 Bus Controller 7.1 Overview The chip has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU, and data transfer controller (DTC). Note: The DTC is not implemented in the H8S/2635 Group. 7.1.1 Features The features of the bus controller are listed below. * Manages external address space in area units Manages the external space as 8 areas of 2-Mbytes Bus specifications can be set independently for each area Burst ROM interface can be set * Basic bus interface 8-bit access or 16-bit access can be selected for each area 2-state access or 3-state access can be selected for each area Program wait states can be inserted for each area * Burst ROM interface Burst ROM interface can be set for area 0 Choice of 1- or 2-state burst access * Idle cycle insertion An idle cycle can be inserted in case of an external read cycle between different areas An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle * Write buffer functions External write cycle and internal access can be executed in parallel * Bus arbitration function Includes a bus arbiter that arbitrates bus mastership among the CPU and DTC Rev. 6.00 Feb 22, 2005 page 149 of 1484 REJ09B0103-0600 Section 7 Bus Controller * Other features External bus release function 7.1.2 Block Diagram Figure 7-1 shows a block diagram of the bus controller. Area decoder Internal address bus ABWCR External bus control signals ASTCR BCRH BCRL Bus controller Internal data bus Internal control signals Bus mode signal Wait controller WCRH WCRL CPU bus request signal DTC bus request signal Bus arbiter CPU bus acknowledge signal DTC bus acknowledge signal Legend: ABWCR: ASTCR: BCRH: BCRL: WCRH: WCRL: Bus width control register Access state control register Bus control register H Bus control register L Wait control register H Wait control register L Figure 7-1 Block Diagram of Bus Controller Rev. 6.00 Feb 22, 2005 page 150 of 1484 REJ09B0103-0600 Section 7 Bus Controller 7.1.3 Pin Configuration Table 7-1 summarizes the pins of the bus controller. Table 7-1 Name Address strobe Read High write Bus Controller Pins Symbol I/O Output Output Output Function Strobe signal indicating that address output on address bus is enabled. Strobe signal indicating that external space is being read. Strobe signal indicating that external space is to be written, and upper half (D15 to D8) of data bus is enabled. Strobe signal indicating that external space is to be written, and lower half (D7 to D0) of data bus is enabled. 7.1.4 Register Configuration Table 7-2 summarizes the registers of the bus controller. Table 7-2 Name Bus width control register Access state control register Wait control register H Wait control register L Bus control register H Bus control register L Pin function control register Bus Controller Registers Abbreviation ABWCR ASTCR WCRH WCRL BCRH BCRL PFCR R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'FF/H'00*2 H'FF H'FF H'FF H'D0 H'08 H'0D/H'00 Address*1 H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FDEB Notes: 1. Lower 16 bits of the address. 2. Determined by the MCU operating mode. RWL Low write RWH DR SA Output Rev. 6.00 Feb 22, 2005 page 151 of 1484 REJ09B0103-0600 Section 7 Bus Controller 7.2 7.2.1 Bit Register Descriptions Bus Width Control Register (ABWCR) : 7 ABW7 6 ABW6 1 R/W 0 R/W 5 ABW5 1 R/W 0 R/W 4 ABW4 1 R/W 0 R/W 3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W 1 ABW1 1 R/W 0 R/W 0 ABW0 1 R/W 0 R/W Modes 5 to 7 Initial value : RW Mode 4 Initial value : RW : : 1 R/W 0 R/W ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access. ABWCR sets the data bus width for the external memory space. The bus width for on-chip memory and internal I/O registers is fixed regardless of the settings in ABWCR. After a reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 5, 6, 7, and to H'00 in mode 4. It is not initialized in software standby mode. Bits 7 to 0--Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the corresponding area is to be designated for 8-bit access or 16-bit access. Bit n ABWn 0 1 Description Area n is designated for 16-bit access Area n is designated for 8-bit access (n = 7 to 0) Rev. 6.00 Feb 22, 2005 page 152 of 1484 REJ09B0103-0600 Section 7 Bus Controller 7.2.2 Bit Access State Control Register (ASTCR) : 7 AST7 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W 3 AST3 1 R/W 2 AST2 1 R/W 1 AST1 1 R/W 0 AST0 1 R/W Initial value : R/W : ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR. ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0--Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the corresponding area is to be designated as a 2-state access space or a 3-state access space. Wait state insertion is enabled or disabled at the same time. Bit n ASTn 0 1 Description Area n is designated for 2-state access Wait state insertion in area n external space is disabled Area n is designated for 3-state access Wait state insertion in area n external space is enabled (Initial value) (n = 7 to 0) Rev. 6.00 Feb 22, 2005 page 153 of 1484 REJ09B0103-0600 Section 7 Bus Controller 7.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode. They are not initialized in software standby mode. WCRH Bit : 7 W71 Initial value : R/W : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3 W51 1 R/W 2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W Bits 7 and 6--Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1. Bit 7 W71 0 1 Bit 6 W70 0 1 0 1 Description Program wait not inserted when external space area 7 is accessed 1 program wait state inserted when external space area 7 is accessed 2 program wait states inserted when external space area 7 is accessed 3 program wait states inserted when external space area 7 is accessed (Initial value) Rev. 6.00 Feb 22, 2005 page 154 of 1484 REJ09B0103-0600 Section 7 Bus Controller Bits 5 and 4--Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit 5 W61 0 1 Bit 4 W60 0 1 0 1 Description Program wait not inserted when external space area 6 is accessed 1 program wait state inserted when external space area 6 is accessed 2 program wait states inserted when external space area 6 is accessed 3 program wait states inserted when external space area 6 is accessed (Initial value) Bits 3 and 2--Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit 3 W51 0 1 Bit 2 W50 0 1 0 1 Description Program wait not inserted when external space area 5 is accessed 1 program wait state inserted when external space area 5 is accessed 2 program wait states inserted when external space area 5 is accessed 3 program wait states inserted when external space area 5 is accessed (Initial value) Bits 1 and 0--Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set to 1. Bit 1 W41 0 1 Bit 0 W40 0 1 0 1 Description Program wait not inserted when external space area 4 is accessed 1 program wait state inserted when external space area 4 is accessed 2 program wait states inserted when external space area 4 is accessed 3 program wait states inserted when external space area 4 is accessed (Initial value) Rev. 6.00 Feb 22, 2005 page 155 of 1484 REJ09B0103-0600 Section 7 Bus Controller WCRL Bit : 7 W31 Initial value : R/W : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3 W11 1 R/W 2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W Bits 7 and 6--Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1. Bit 7 W31 0 1 Bit 6 W30 0 1 0 1 Description Program wait not inserted when external space area 3 is accessed 1 program wait state inserted when external space area 3 is accessed 2 program wait states inserted when external space area 3 is accessed 3 program wait states inserted when external space area 3 is accessed (Initial value) Bits 5 and 4--Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1. Bit 5 W21 0 1 Bit 4 W20 0 1 0 1 Description Program wait not inserted when external space area 2 is accessed 1 program wait state inserted when external space area 2 is accessed 2 program wait states inserted when external space area 2 is accessed 3 program wait states inserted when external space area 2 is accessed (Initial value) Rev. 6.00 Feb 22, 2005 page 156 of 1484 REJ09B0103-0600 Section 7 Bus Controller Bits 3 and 2--Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 W11 0 1 Bit 2 W10 0 1 0 1 Description Program wait not inserted when external space area 1 is accessed 1 program wait state inserted when external space area 1 is accessed 2 program wait states inserted when external space area 1 is accessed 3 program wait states inserted when external space area 1 is accessed (Initial value) Bits 1 and 0--Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1. Bit 1 W01 0 1 Bit 0 W00 0 1 0 1 Description Program wait not inserted when external space area 0 is accessed 1 program wait state inserted when external space area 0 is accessed 2 program wait states inserted when external space area 0 is accessed 3 program wait states inserted when external space area 0 is accessed (Initial value) Rev. 6.00 Feb 22, 2005 page 157 of 1484 REJ09B0103-0600 Section 7 Bus Controller 7.2.4 Bit Bus Control Register H (BCRH) : 7 ICIS1 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W 3 0 R/W BRSTRM BRSTS1 BRSTS0 3/4 0 R/W 2 3/4 0 R/W 1 3/4 0 R/W 0 Initial value : R/W : BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for area 2 to 5, and 0. BCRH is initialized to H'D0 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas. Bit 7 ICIS1 0 1 Description Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas (Initial value) Bit 6--Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed . Bit 6 ICIS0 0 1 Description Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles (Initial value) Rev. 6.00 Feb 22, 2005 page 158 of 1484 REJ09B0103-0600 Section 7 Bus Controller Bit 5--Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface. Bit 5 BRSTRM 0 1 Description Area 0 is basic bus interface Area 0 is burst ROM interface (Initial value) Bit 4--Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 0 1 Description Burst cycle comprises 1 state Burst cycle comprises 2 states (Initial value) Bit 3--Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 0 1 Description Max. 4 words in burst access Max. 8 words in burst access (Initial value) Bits 2 to 0--Reserved: Only 0 should be written to these bits. Rev. 6.00 Feb 22, 2005 page 159 of 1484 REJ09B0103-0600 Section 7 Bus Controller 7.2.5 Bit Bus Control Register L (BCRL) : 3/4 0 R/W 7 3/4 0 R/W 6 3/4 3/4 0 5 3/4 0 R/W 4 3/4 1 R/W 3 3/4 0 R/W 2 1 WDBE 0 R/W 3/4 0 R/W 0 Initial value : R/W : BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, enabling or disabling of the write data buffer function. BCRL is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 and 6--Reserved: Only 0 should be written to these bits. Bit 5--Reserved: It is always read as 0. Cannot be written to. Bit 4--Reserved: Only 0 should be written to this bit. Bit 3--Reserved: Only 1 should be written to this bit. Bit 2--Reserved: Only 0 should be written to this bit. Bit 1--Write Data Buffer Enable (WDBE): This bit selects whether or not to use the write buffer function in the external write cycle. Bit 1 WDBE 0 1 Description Write data buffer function not used Write data buffer function used (Initial value) Bit 0--Reserved: Only 0 should be written to these bits. Rev. 6.00 Feb 22, 2005 page 160 of 1484 REJ09B0103-0600 Section 7 Bus Controller 7.2.6 Bit Pin Function Control Register (PFCR) : 3/4 0 R/W 7 3/4 0 R/W 6 3/4 0 R/W 5 3/4 0 R/W 4 3 AE3 1/0 R/W 2 AE2 1/0 R/W 1 AE1 0 R/W 0 AE0 1/0 R/W Initial value : R/W : PFCR is an 8-bit read/write register that controls the address output in on-chip ROM-enabled expansion mode. PFCR is initialized to H'0D/H'00 by a reset and in hardware standby mode. It retains its previous state in software standby mode. Bits 7 to 4--Reserved: Only 0 should be written to these bits. Bits 3 to 0--Address Output Enable 3 to 0 (AE3 to AE0): These bits select enabling or disabling of address outputs A8 to A23 in on-chip ROM-disabled expansion mode and on-chip ROM-enabled expansion mode. When a pin is enabled for address output, the address is output regardless of the corresponding DDR setting. When a pin is disabled for address output, it becomes an output port when the corresponding DDR bit is set to 1. Rev. 6.00 Feb 22, 2005 page 161 of 1484 REJ09B0103-0600 Section 7 Bus Controller Bit 3 AE3 0 Bit 2 AE2 0 Bit 1 AE1 0 1 Bit 0 AE0 0 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Description A8 to A23 address output disabled (Initial value*) A8 address output enabled; A9 to A23 address output disabled A8, A9 address output enabled; A10 to A23 address output disabled A8 to A10 address output enabled; A11 to A23 address output disabled A8 to A11 address output enabled; A12 to A23 address output disabled A8 to A12 address output enabled; A13 to A23 address output disabled A8 to A13 address output enabled; A14 to A23 address output disabled A8 to A14 address output enabled; A15 to A23 address output disabled A8 to A15 address output enabled; A16 to A23 address output disabled A8 to A16 address output enabled; A17 to A23 address output disabled A8 to A17 address output enabled; A18 to A23 address output disabled A8 to A18 address output enabled; A19 to A23 address output disabled A8 to A19 address output enabled; A20 to A23 address output disabled A8 to A20 address output enabled; A21 to A23 address output disabled (Initial value*) A8 to A21 address output enabled; A22, A23 address output disabled A8 to A23 address output enabled Note: * In on-chip ROM-enabled expansion mode, bits AE3 to AE0 are initialized to B'0000. In on-chip ROM-disabled expansion mode, bits AE3 to AE0 are initialized to B'1101. Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to 1. Rev. 6.00 Feb 22, 2005 page 162 of 1484 REJ09B0103-0600 Section 7 Bus Controller 7.3 7.3.1 Overview of Bus Control Area Partitioning In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. In normal mode*, it controls a 64-kbyte address space comprising part of area 0. Figure 7-2 shows an outline of the memory map. Note: * Not available in the chip. H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7 (2 Mbytes) H'FFFFFF (1) Advanced mode H'0000 H'FFFF (2) Normal mode* Note: * Not available in the chip. Figure 7-2 Overview of Area Partitioning Rev. 6.00 Feb 22, 2005 page 163 of 1484 REJ09B0103-0600 Section 7 Bus Controller 7.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. Bus Width: A bus width of 8 or 16 bits can be selected with ADWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is always set. Number of Access States: Two or three access states can be selected with ASTCR. An area for which 2-state access is selected functions as a 2-state access space, and an area for which 3-state access is selected functions as a 3-state access space. With the burst ROM interface, the number of access states may be determined without regard to ASTCR. When 2-state access space is designated, wait insertion is disabled. Number of Program Wait States: When 3-state access space is designated by ASTCR, the number of program wait states to be inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be selected. Table 7-3 shows the bus specifications for each basic bus interface area. Rev. 6.00 Feb 22, 2005 page 164 of 1484 REJ09B0103-0600 Section 7 Bus Controller Table 7-3 ABWCR ABWn 0 Bus Specifications for Each Area (Basic Bus Interface) ASTCR ASTn 0 1 WCRH, WCRL Wn1 -- 0 1 Wn0 -- 0 1 0 1 -- 0 1 1 0 1 8 2 3 Bus Specifications (Basic Bus Interface) Bus Width 16 Program Wait Access States States 2 3 0 0 1 2 3 0 0 1 2 3 1 0 1 -- 0 7.3.3 Memory Interfaces The chip's memory interfaces comprise a basic bus interface that allows direct connection or ROM, SRAM, and so on, and a burst ROM interface that allows direct connection of burst ROM. The memory interface can be selected independently for each area. An area for which the basic bus interface is designated functions as normal space, and an area for which the burst ROM interface is designated functions as burst ROM space. Rev. 6.00 Feb 22, 2005 page 165 of 1484 REJ09B0103-0600 Section 7 Bus Controller 7.3.4 Interface Specifications for Each Area The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (7.4, Basic Bus Interface, and 7.5, Burst ROM Interface) should be referred to for further details. Area 0: Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external space. Either basic bus interface or burst ROM interface can be selected for area 0. Areas 1 to 6: In external expansion mode, all of areas 1 to 6 is external space. Only the basic bus interface can be used for areas 1 to 6. Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space. Only the basic bus interface can be used for the area 7. Rev. 6.00 Feb 22, 2005 page 166 of 1484 REJ09B0103-0600 Section 7 Bus Controller 7.4 7.4.1 Basic Bus Interface Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 7-3). 7.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-Bit Access Space: Figure 7-3 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word transfer instruction is performed as two byte accesses, and a longword transfer instruction, as four byte accesses. Upper data bus Lower data bus D15 D8 D7 D0 Byte size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Word size Figure 7-3 Access Sizes and Data Alignment Control (8-Bit Access Space) Rev. 6.00 Feb 22, 2005 page 167 of 1484 REJ09B0103-0600 Section 7 Bus Controller 16-Bit Access Space: Figure 7-4 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Lower data bus Upper data bus D15 D8 D7 D0 Byte size Byte size Word size Longword size 1st bus cycle 2nd bus cycle * Even address * Odd address Figure 7-4 Access Sizes and Data Alignment Control (16-Bit Access Space) Rev. 6.00 Feb 22, 2005 page 168 of 1484 REJ09B0103-0600 Section 7 Bus Controller 7.4.3 Valid Strobes Table 7-4 shows the data buses used and valid strobes for the access spaces. Table 7-4 Area 8-bit access space Data Buses Used and Valid Strobes Access Read/ Size Write Byte Read Write Read Write Word Read Write Address -- -- Even Odd Even Odd -- -- Valid Strobe Upper Data Bus (D15 to D8) Valid Valid Invalid Valid Hi-Z Valid Valid Lower data bus (D7 to D0) Invalid Hi-Z Invalid Valid Hi-Z Valid Valid Valid 16-bit access Byte space , Note: Hi-Z: High impedance. Invalid: Input state; input value is ignored. Rev. 6.00 Feb 22, 2005 page 169 of 1484 REJ09B0103-0600 RWL RWL RWH DR RWL RWH DR RWH DR RWH In a write, the lower half. DR In a read, the data bus. signal is valid without discrimination between the upper and lower halves of the signal is valid for the upper half of the data bus, and the signal for the Section 7 Bus Controller 7.4.4 Basic Timing 8-Bit 2-State Access Space: Figure 7-5 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Rev. 6.00 Feb 22, 2005 page 170 of 1484 REJ09B0103-0600 RWL The pin is fixed high. Wait states cannot be inserted. Bus cycle T1 T2 B Address bus AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 Valid High D7 to D0 High impedance Figure 7-5 Bus Timing for 8-Bit 2-State Access Space Section 7 Bus Controller 8-Bit 3-State Access Space: Figure 7-6 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. RWL The pin is fixed high. Wait states can be inserted. Bus cycle T1 T2 T3 B Address bus AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 Valid High impedance High D7 to D0 Figure 7-6 Bus Timing for 8-Bit 3-State Access Space Rev. 6.00 Feb 22, 2005 page 171 of 1484 REJ09B0103-0600 Section 7 Bus Controller 16-Bit 2-State Access Space: Figures 7-7 to 7-9 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted. Bus cycle T1 T2 B Address bus AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Figure 7-7 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access) Rev. 6.00 Feb 22, 2005 page 172 of 1484 REJ09B0103-0600 Section 7 Bus Controller Bus cycle T1 T2 B Address bus AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR LWR Write D15 to D8 High High impedance D7 to D0 Valid Figure 7-8 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) Rev. 6.00 Feb 22, 2005 page 173 of 1484 REJ09B0103-0600 Section 7 Bus Controller Bus cycle T1 T2 B Address bus AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Figure 7-9 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) Rev. 6.00 Feb 22, 2005 page 174 of 1484 REJ09B0103-0600 Section 7 Bus Controller 16-Bit 3-State Access Space: Figures 7-10 to 7-12 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted. Bus cycle T1 T2 T3 B Address bus AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 Valid High impedance High D7 to D0 Figure 7-10 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access) Rev. 6.00 Feb 22, 2005 page 175 of 1484 REJ09B0103-0600 Section 7 Bus Controller Bus cycle T1 T2 T3 B Address bus AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR LWR Write D15 to D8 High High impedance D7 to D0 Valid Figure 7-11 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) Rev. 6.00 Feb 22, 2005 page 176 of 1484 REJ09B0103-0600 Section 7 Bus Controller Bus cycle T1 T2 T3 B Address bus AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Note: n = 0 to 7 Valid Figure 7-12 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access) Rev. 6.00 Feb 22, 2005 page 177 of 1484 REJ09B0103-0600 Section 7 Bus Controller 7.4.5 Wait Control When accessing external space, the chip can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion. Program Wait Insertion From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings of WCRH and WCRL. Figure 7-13 shows an example of wait state insertion timing. By program wait T1 T2 Tw Tw Tw T3 B Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Write data Figure 7-13 Example of Wait State Insertion Timing The settings after a reset are: 3-state access, 3 program wait state insertion. Rev. 6.00 Feb 22, 2005 page 178 of 1484 REJ09B0103-0600 Section 7 Bus Controller 7.5 7.5.1 Burst ROM Interface Overview In this LSI, the area 0 external space can be set as burst ROM space and burst ROM interfacing performed. Burst ROM space interfacing allows 16-bit ROM capable of burst access to be accessed at high-speed. The BRSTRM bit of BCRH sets area 0 as burst ROM space. CPU instruction fetches (only) can be performed using a maximum of 4-word or 8-word continuous burst access. 1 state or 2 states can be selected in the case of burst access. 7.5.2 Basic Timing The AST0 bit of ASTCR sets the number of access states in the initial cycle (full access) of the burst ROM interface. Wait states can be inserted when the AST0 bit is set to 1. The burst cycle can be set for 1 state or 2 sttes by setting the BRSTS1 bit of BCRH. Wait states cannot be inserted. When area 0 is set as burst ROM space, area 0 is a 16-bit access space regardless of the ABW0 bit of ABWCR. When the BRSTS0 bit of BCRH is cleared to 0, 4-word max. burst access is performed. When the BRSTS0 bit is set to 1, 8-word max. burst access is performed. Figures 7-14 (a) and (b) show the basic access timing for the burst ROM space. Figure 7-14 (a) is an example when both the AST0 and BRSTS1 bits are set to 1. Figure 7-14 (b) is an example when both the AST0 and BRSTS1 bits are set to 0. Rev. 6.00 Feb 22, 2005 page 179 of 1484 REJ09B0103-0600 Section 7 Bus Controller Full access T1 T2 T3 T1 Burst access T2 T1 T2 B Address bus Low address only changes )5 4, Data bus Read data Read data Read data Figure 7-14 (a) Example Burst ROM Access Timing (AST0 = BRSTS1 = 1) Full access T1 T2 Burst access T1 T1 B Address bus Low address only changes )5 4, Data bus Read data Read data Read data Figure 7-14 (b) Example Burst ROM Access Timing (AST0 = BRSTS1 = 0) Rev. 6.00 Feb 22, 2005 page 180 of 1484 REJ09B0103-0600 Section 7 Bus Controller 7.5.3 Wait Control As with the basic bus interface, program waits can be inserted in the burst ROM interface initial cycle (full access). See section 7.4.5, Wait Control. Wait states cannot be inserted in the burst cycle. 7.6 7.6.1 Idle Cycle Operation When the chip accesses external space, it can insert a 1-state idle cycle (TI) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on. Rev. 6.00 Feb 22, 2005 page 181 of 1484 REJ09B0103-0600 Section 7 Bus Controller (1) Consecutive Reads between Different Areas If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the start of the second read cycle. Figure 7-15 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A Bus cycle B T1 T2 Bus cycle A Bus cycle B TI T1 T2 B Address bus T1 T2 T3 B Address bus T1 T2 T3 +5* +5* (area A) (area B) +5* (area A) +5* (area B) 4, Data bus Data collision (b) Idle cycle inserted (Initial value ICIS1 = 1) 4, Data bus Long output floating time (a) Idle cycle not inserted (ICIS1 = 0) Note: * The +5 signal is generated externally rather than inside the LSI device. Figure 7-15 Example of Idle Cycle Operation (1) Rev. 6.00 Feb 22, 2005 page 182 of 1484 REJ09B0103-0600 Section 7 Bus Controller (2) Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 7-16 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A Bus cycle B T1 T2 Bus cycle A Bus cycle B TI T1 T2 B Address bus T1 T2 T3 B Address bus T1 T2 T3 +5* (area A) +5* (area B) 4, Possibility of overlap between +5 (area B) and 4, (a) Idle cycle not inserted (ICIS1 = 0) +5* (area A) +5* (area B) 4, (b) Idle cycle inserted (Initial value ICIS1 = 1) Note: * The +5 signal is generated externally rather than inside the LSI device. Figure 7-16 Example of Idle Cycle Operation (2) Rev. 6.00 Feb 22, 2005 page 183 of 1484 REJ09B0103-0600 Section 7 Bus Controller (3) Relationship between Chip Select (CS*) Signal and Read (RD) Signal In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap signal and the bus cycle B signal. between the bus cycle A In the initial state after reset release, idle cycle insertion (b) is set. B Address bus +5* (area A) +5* (area B) 4, 094 Data bus Note: * The +5 signal is generated externally rather than inside the LSI device. Rev. 6.00 Feb 22, 2005 page 184 of 1484 REJ09B0103-0600 SC Note: * The signal is generated externally rather than inside the LSI device. Bus cycle A T1 T2 T3 Bus cycle B T1 T2 Bus cycle A Bus cycle B TI T1 T2 B Address bus T1 T2 T3 +5* (area A) +5* (area B) 4, 094 Data bus Data collision (b) Idle cycle inserted (Initial value ICIS0 = 1) Long output floating time (a) Idle cycle not inserted (ICIS0 = 0) Figure 7-17 Relationship between Chip Select (CS)* and Read (RD) SC DR Setting idle cycle insertion, as in (b), however, will prevent any overlap between the signals. SC SC DR Depending on the system's load conditions, the example is shown in figure 7-17. signal may lag behind the signal*. An DR and Section 7 Bus Controller 7.6.2 Pin States During Idle Cycles Table 7-5 shows the pin states during idle cycles. Table 7-5 Pin States During Idle Cycles Pins A23 to A0 D15 to D0 Pin State Content identical to immediately following bus cycle High impedance High level High level High level High level RWL RWH DR SA Rev. 6.00 Feb 22, 2005 page 185 of 1484 REJ09B0103-0600 Section 7 Bus Controller 7.7 Write Data Buffer Function The chip has a write data buffer function in the external data bus. Using this function enables the write data buffer to be accessed in parallel. The write data buffer function is made available by setting the WDBE bit in BCRL to 1. Figure 7-18 shows an example of the timing when the write data buffer function is used. When this function is used, if an external write continues for 2 states or longer, and there is an internal access next, only an external write is executed in the first state, but from the next state onward an internal access (on-chip memory or internal I/O register read/write) is executed in parallel with the external write rather than waiting until it ends. On-chip memory read Internal I/O register read External write cycle T1 T2 TW TW T3 B Internal address bus Internal memory Internal read signal Internal I/O register address A23 to A0 External space write External address HWR, LWR D15 to D0 Figure 7-18 Example of Timing when Write Data Buffer Function Is Used Rev. 6.00 Feb 22, 2005 page 186 of 1484 REJ09B0103-0600 Section 7 Bus Controller 7.8 Bus Arbitration Note: The H8S/2635 Group is not equipped with a DTC. 7.8.1 Overview The chip has a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU and DTC which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes possession of the bus and begins its operation. 7.8.2 Operation The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus masters is as follows: (High) 7.8.3 DTC > CPU (Low) Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus. CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows: * The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. See Appendix A.5, Bus States during Instruction Execution, for timings at which the bus is not transferred. * If the CPU is in sleep mode, it transfers the bus immediately. Rev. 6.00 Feb 22, 2005 page 187 of 1484 REJ09B0103-0600 Section 7 Bus Controller DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). 7.9 Resets and the Bus Controller In a reset, the chip, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued. Rev. 6.00 Feb 22, 2005 page 188 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) Section 8 Data Transfer Controller (DTC) Note: The H8S/2635 Group is not equipped with a DTC. 8.1 Overview The chip includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 8.1.1 Features * Transfer possible over any number of channels Transfer information is stored in memory One activation source can trigger a number of data transfers (chain transfer) * Wide range of transfer modes Normal, repeat, and block transfer modes available Incrementing, decrementing, and fixing of source and destination addresses can be selected * Direct specification of 16-Mbyte address space possible 24-bit transfer source and destination addresses can be specified * Transfer can be set in byte or word units * A CPU interrupt can be requested for the interrupt that activated the DTC An interrupt request can be issued to the CPU after one data transfer ends An interrupt request can be issued to the CPU after the specified data transfers have completely ended * Activation by software is possible * Module stop mode can be set The initial setting enables DTC registers to be accessed. DTC operation is halted by setting module stop mode. Rev. 6.00 Feb 22, 2005 page 189 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) 8.1.2 Block Diagram Figure 8-1 shows a block diagram of the DTC. The DTC's register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1. Internal address bus Interrupt controller DTC On-chip RAM CPU interrupt request Legend: MRA, MRB: CRA, CRB: SAR: DAR: DTCERA to DTCERG: DTVECR: DTC service request DTC mode registers A and B DTC transfer count registers A and B DTC source address register DTC destination address register DTC enable registers A to G DTC vector register Figure 8-1 Block Diagram of DTC Rev. 6.00 Feb 22, 2005 page 190 of 1484 REJ09B0103-0600 MRA MRB CRA CRB DAR SAR Interrupt request Internal data bus Register information DTCERA to DTCERG Control logic DTVECR Section 8 Data Transfer Controller (DTC) 8.1.3 Register Configuration Table 8-1 summarizes the DTC registers. Table 8-1 Name DTC mode register A DTC mode register B DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B DTC enable registers DTC vector register Module stop control register A DTC Registers Abbreviation MRA MRB SAR DAR CRA CRB DTCER DTVECR MSTPCRA R/W --*2 --*2 --*2 --*2 -- --*2 R/W R/W R/W *2 Initial Value Undefined Undefined Undefined Undefined Undefined Undefined H'00 H'00 H'3F Address*1 --*3 --*3 --*3 --*3 --*3 --*3 H'FE16 to H'FE1C H'FE1F H'FDE8 Notes: 1. Lower 16 bits of the address. 2. Registers within the DTC cannot be read or written to directly. 3. Register information is located in on-chip RAM addresses H'EBC0 to H'EFBF. It cannot be located in external memory space. When the DTC is used, do not clear the RAME bit in SYSCR to 0. Rev. 6.00 Feb 22, 2005 page 191 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) 8.2 8.2.1 Bit Register Descriptions DTC Mode Register A (MRA) : 7 SM1 6 SM0 * 5 DM1 * 4 DM0 * 3 MD1 * 2 MD0 * 1 DTS * 0 Sz * Initial value : R/W : * 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 *: Undefined MRA is an 8-bit register that controls the DTC operating mode. Bits 7 and 6--Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer. Bit 7 SM1 0 1 Bit 6 SM0 -- 0 1 Description SAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) Bits 5 and 4--Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether DAR is to be incremented, decremented, or left fixed after a data transfer. Bit 5 DM1 0 1 Bit 4 DM0 -- 0 1 Description DAR is fixed DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) Rev. 6.00 Feb 22, 2005 page 192 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) Bits 3 and 2--DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 MD1 0 1 Bit 2 MD0 0 1 0 1 Description Normal mode Repeat mode Block transfer mode -- Bit 1--DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. Bit 1 DTS 0 1 Description Destination side is repeat area or block area Source side is repeat area or block area Bit 0--DTC Data Transfer Size (Sz): Specifies the size of data to be transferred. Bit 0 Sz 0 1 Description Byte-size transfer Word-size transfer Rev. 6.00 Feb 22, 2005 page 193 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) 8.2.2 Bit DTC Mode Register B (MRB) : 7 CHNE 6 DISEL * 3/4 * 5 3/4 * 4 3/4 * 3 3/4 * 2 3/4 * 1 3/4 * 0 Initial value: R/W : * 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 *: Undefined MRB is an 8-bit register that controls the DTC operating mode. Bit 7--DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of DTCER is not performed. Bit 7 CHNE 0 1 Description End of DTC data transfer (activation waiting state is entered) DTC chain transfer (new register information is read, then data is transferred) Bit 6--DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are disabled or enabled after a data transfer. Bit 6 DISEL 0 1 Description After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 (the DTC clears the interrupt source flag of the activating interrupt to 0) After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the interrupt source flag of the activating interrupt to 0) Bits 5 to 0--Reserved: These bits have no effect on DTC operation in the chip, and should always be written with 0. Rev. 6.00 Feb 22, 2005 page 194 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) 8.2.3 Bit DTC Source Address Register (SAR) : 23 22 21 20 19 4 3 2 1 0 Initial value: R/W : * * * * * * * * * * 3/43/43/43/43/4 3/43/43/43/43/4 *: Undefined SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 8.2.4 Bit DTC Destination Address Register (DAR) : 23 22 21 20 19 4 3 2 1 0 Initial value : R/W : * * * * * * * * * * 3/43/43/43/43/4 3/43/43/43/43/4 *: Undefined DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. 8.2.5 Bit DTC Transfer Count Register A (CRA) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W : * * * * * * * * * * * * * * * * 3/43/43/43/43/43/43/43/43/43/43/43/43/43/43/43/4 CRAH CRAL *: Undefined CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. Rev. 6.00 Feb 22, 2005 page 195 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is repeated. 8.2.6 Bit DTC Transfer Count Register B (CRB) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W : * * * * * * * * * * * * * * * * 3/43/43/43/43/43/43/43/43/43/43/43/43/43/43/43/4 *: Undefined CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. 8.2.7 Bit DTC Enable Registers (DTCER) : 7 DTCE7 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 DTCE4 0 R/W 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTCE0 0 R/W Initial value: R/W : The DTC enable registers comprise seven 8-bit readable/writable registers, DTCERA to DTCERG with bits corresponding to the interrupt sources that can control enabling and disabling of DTC activation. These bits enable or disable DTC service for the corresponding interrupt sources. The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode. Rev. 6.00 Feb 22, 2005 page 196 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) Bit n--DTC Activation Enable (DTCEn) Bit n DTCEn 0 Description DTC activation by this interrupt is disabled [Clearing conditions] * * 1 When the DISEL bit is 1 and the data transfer has ended When the specified number of transfers have ended (Initial value) DTC activation by this interrupt is enabled [Holding condition] * When the DISEL bit is 0 and the specified number of transfers have not ended (n = 7 to 0) A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence between interrupt sources and DTCE bits is shown in table 8-4, together with the vector number generated for each interrupt controller. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register. 8.2.8 Bit DTC Vector Register (DTVECR) : 7 0 R/(W)*1 6 0 R/W*2 5 0 R/W*2 4 0 R/W*2 3 0 R/W*2 2 0 R/W*2 1 0 R/W*2 0 0 R/W*2 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value: R/W : Notes: 1. Only 1 can be written to the SWDTE bit. 2. Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0. DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. DTVECR is initialized to H'00 by a reset and in hardware standby mode. Rev. 6.00 Feb 22, 2005 page 197 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) Bit 7--DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by software. Bit 7 SWDTE 0 Description DTC software activation is disabled [Clearing conditions] * * 1 When the DISEL bit is 0 and the specified number of transfers have not ended When 0 is written to the DISEL bit after a software-activated data transfer end interrupt (SWDTEND) request has been sent to the CPU (Initial value) DTC software activation is enabled [Holding conditions] * * * When the DISEL bit is 1 and data transfer has ended When the specified number of transfers have ended During data transfer due to software activation Bits 6 to 0--DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + ((vector number) << 1). <<1 indicates a one-bit leftshift. For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420. Rev. 6.00 Feb 22, 2005 page 198 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) 8.2.9 Bit Module Stop Control Register A (MSTPCRA) 7 MSTPA7 0 R/W 6 MSTPA6 0 R/W 5 MSTPA5 1 R/W 4 MSTPA4 1 R/W 3 MSTPA3 1 R/W 2 MSTPA2 1 R/W 1 MSTPA1 1 R/W 0 MSTPA0 1 R/W Initial value Read/Write MSTPCRA is a 8-bit readable/writable register that performs module stop mode control. When the MSTPA6 bit in MSTPCRA is set to 1, the DTC operation stops at the end of the bus cycle and a transition is made to module stop mode. However, 1 cannot be written in the MSTPA6 bit while the DTC is operating. For details, see section 23A.5, 23B.5, Module Stop Mode. MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 6--Module Stop (MSTPA6): Specifies the DTC module stop mode. Bit 6 MSTPA6 0 1 Description DTC module stop mode cleared DTC module stop mode set (Initial value) Rev. 6.00 Feb 22, 2005 page 199 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) 8.3 8.3.1 Operation Overview When activated, the DTC reads register information that is already stored in memory and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to memory. Pre-storage of register information in memory makes it possible to transfer data over any required number of channels. Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single activation. Figure 8-2 shows a flowchart of DTC operation. Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE =1 No Yes Transfer Counter= 0 or DISEL = 1 No Clear an activation flag Yes Clear DTCER End Interrupt exception handling Figure 8-2 Flowchart of DTC Operation Rev. 6.00 Feb 22, 2005 page 200 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) The DTC transfer mode can be normal mode, repeat mode, or block transfer mode. The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed. Table 8-2 outlines the functions of the DTC. Table 8-2 DTC Functions Address Registers Transfer Mode * Normal mode One transfer request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 Up to 65,536 transfers possible * Repeat mode One transfer request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 After the specified number of transfers (1 to 256), the initial state resumes and operation continues * Block transfer mode One transfer request transfers a block of the specified size Block size is from 1 to 256 bytes or words Up to 65,536 transfers possible A block area can be designated at either the source or destination Activation Source * * * * * * * IRQ TPU TGI SCI TXI or RXI A/D converter ADI Motor control PWM CMI HCAN RM0 (mail box 0) Software Transfer Source 24 bits Transfer Destination 24 bits Rev. 6.00 Feb 22, 2005 page 201 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) 8.3.2 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a CPU interrupt source when the bit is cleared to 0. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared. Table 8-3 shows activation source and DTCER clearance. The activation source flag, in the case of RXI0, for example, is the RDRF flag of SCI0. Table 8-3 Activation Source and DTCER Clearance When the DISEL Bit Is 1, or when the Specified Number of Transfers Have Ended The SWDTE bit remains set to 1 An interrupt is issued to the CPU Interrupt activation The corresponding DTCER bit remains set to 1 The activation source flag is cleared to 0 The corresponding DTCER bit is cleared to 0 The activation source flag remains set to 1 A request is issued to the CPU for the activation source interrupt When the DISEL Bit Is 0 and the Specified Number of Activation Source Transfers Have not Ended Software activation The SWDTE bit is cleared to 0 Rev. 6.00 Feb 22, 2005 page 202 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) Figure 8-3 shows a block diagram of activation source control. For details see section 5, Interrupt Controller. Source flag cleared Clear controller Clear DTCER Clear request Select On-chip supporting module IRQ interrupt Interrupt request Selection circuit DTC DTVECR Interrupt controller Interrupt mask CPU Figure 8-3 Block Diagram of DTC Activation Source Control When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the default priorities. Rev. 6.00 Feb 22, 2005 page 203 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) 8.3.3 DTC Vector Table Figure 8-4 shows the correspondence between DTC vector addresses and register information. Table 8-4 shows the correspondence between activation and vector addresses. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] << 1) (where << 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the vector address is H'0420. The DTC reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. The register information can be placed at predetermined addresses in the on-chip RAM. The start address of the register information should be an integral multiple of four. The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte unit being used in both cases. These two bytes specify the lower bits of the address in the on-chip RAM. Note: * Not available in the chip. DTC vector address Register information start address Register information Chain transfer Figure 8-4 Correspondence between DTC Vector Address and Register Information Rev. 6.00 Feb 22, 2005 page 204 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) Table 8-4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Origin of Interrupt Source Software Vector Number DTVECR Vector Address H'0400+ (DTVECR [6:0] <<1) H'0420 H'0422 H'0424 H'0426 H'0428 H'042A H'042C to H'0436 H'0438 H'043A to H'043E H'0440 H'0442 H'0444 H'0446 H'0448 to H'044E H'0450 H'0452 H'0458 H'045A Interrupt Source Write to DTVECR DTCE*1 -- Priority High IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Reserved ADI (A/D conversion end) Reserved TGI0A (GR0A compare match/ input capture) TGI0B (GR0B compare match/ input capture) TGI0C (GR0C compare match/ input capture) TGI0D (GR0D compare match/ input capture) Reserved TGI1A (GR1A compare match/ input capture) TGI1B (GR1B compare match/ input capture) TGI2A (GR2A compare match/ input capture) TGI2B (GR2B compare match/ input capture) External pin 16 17 18 19 20 21 DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 -- DTCEB6 -- DTCEB5 DTCEB4 DTCEB3 DTCEB2 -- DTCEB1 DTCEB0 DTCEC7 DTCEC6 Low -- A/D -- TPU channel 0 22 to 27 28 29 to 31 32 33 34 35 -- TPU channel 1 36 to 39 40 41 TPU channel 2 44 45 Rev. 6.00 Feb 22, 2005 page 205 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) Origin of Interrupt Source TPU channel 3 Interrupt Source TGI3A (GR3A compare match/ input capture) TGI3B (GR3B compare match/ input capture) TGI3C (GR3C compare match/ input capture) TGI3D (GR3D compare match/ input capture) Reserved TGI4A (GR4A compare match/ input capture) TGI4B (GR4B compare match/ input capture) Reserved TGI5A (GR5A compare match/ input capture) TGI5B (GR5B compare match/ input capture) Reserved RXI0 (reception complete 0) TXI0 (transmit data empty 0) Reserved RXI1 (reception complete 1) TXI1 (transmit data empty 1) Reserved RXI2 (reception complete 2) TXI2 (transmit data empty 2) Reserved Vector Number 48 49 50 51 Vector Address H'0460 H'0462 H'0464 H'0466 H'0468 to H'046E H'0470 H'0472 H'0474 to H'0476 H'0478 H'047A H'047C to H'04A0 H'04A2 H'04A4 H'04A6 to H'04A8 H'04AA H'04AC H'04AE to H'04B0 H'04B2 H'04B4 H'04B6 to H'04C2 DTCE*1 DTCEC5 DTCEC4 DTCEC3 DTCEC2 -- DTCEC1 DTCEC0 -- DTCED5 DTCED4 -- DTCEE3 DTCEE2 -- DTCEE1 DTCEE0 -- DTCEF7 DTCEF6 -- Priority High -- TPU channel 4 52 to 55 56 57 -- TPU channel 5 58, 59 60 61 -- SCI channel 0 -- SCI channel 1 -- SCI channel 2 -- 62 to 80 81 82 83, 84 85 86 87, 88 89 90 91 to 97 Low Rev. 6.00 Feb 22, 2005 page 206 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) Origin of Interrupt Source I C channel 0 (option) I2C channel 1 (option) PWM -- HCAN1 -- HCAN0 -- 2 Interrupt Source I CI0 (1-byte transmission/ reception completed)*2 I2CI1 (1-byte transmission/ reception completed)*2 CMI1 (PWCYR1 compare match) CMI2 (PWCYR2 compare match) Reserved RM0 (HCAN1 mail box 0) Reserved RM0 (HCAN0 mail box 0) Reserved 2 Vector Number 100 102 104 105 106 107 108 109 Vector Address H'04C8 H'04CC H'04D0 H'04D2 H'04D4 H'04D6 H'04D8 H'04DA DTCE*1 DTCEF1 DTCEF0 DTCEG7 DTCEG6 -- DTCEG4 -- DTCEG2 -- Priority High 110 to 124 H'04DC to H'04F8 Low Notes: 1. DTCE bits with no corresponding interrupt are reserved, and should be written with 0. 2. I2C bus interface is available as an option in the H8S/2638, H8S/2639, and H8S/2630. These bits become reserved bits when this optional feature is not used or in the H8S/2636. Rev. 6.00 Feb 22, 2005 page 207 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) 8.3.4 Location of Register Information in Address Space Figure 8-5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (contents of the vector address). In the case of chain transfer, register information should be located in consecutive areas. Locate the register information in the on-chip RAM (addresses: H'FFEBC0 to H'FFEFBF). Lower address Register information start address 0 MRA MRB CRA MRA MRB CRA 4 bytes SAR DAR CRB Register information for 2nd transfer in chain transfer 1 2 SAR DAR CRB Register information 3 Chain transfer Figure 8-5 Location of Register Information in Address Space Rev. 6.00 Feb 22, 2005 page 208 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) 8.3.5 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 8-5 lists the register information in normal mode and figure 8-6 shows memory mapping in normal mode. Table 8-5 Name DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B Register Information in Normal Mode Abbreviation SAR DAR CRA CRB Function Designates source address Designates destination address Designates transfer count Not used SAR Transfer DAR Figure 8-6 Memory Mapping in Normal Mode Rev. 6.00 Feb 22, 2005 page 209 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) 8.3.6 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. Table 8-6 lists the register information in repeat mode and figure 8-7 shows memory mapping in repeat mode. Table 8-6 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Information in Repeat Mode Abbreviation SAR DAR CRAH CRAL CRB Function Designates source address Designates destination address Holds number of transfers Designates transfer count Not used SAR or DAR Repeat area Transfer DAR or SAR Figure 8-7 Memory Mapping in Repeat Mode Rev. 6.00 Feb 22, 2005 page 210 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) 8.3.7 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt is requested. Table 8-7 lists the register information in block transfer mode and figure 8-8 shows memory mapping in block transfer mode. Table 8-7 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Information in Block Transfer Mode Abbreviation SAR DAR CRAH CRAL CRB Function Designates source address Designates destination address Holds block size Designates block size count Transfer count Rev. 6.00 Feb 22, 2005 page 211 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) 1st block SAR or DAR * * * Block area Transfer DAR or SAR Nth block Figure 8-8 Memory Mapping in Block Transfer Mode Rev. 6.00 Feb 22, 2005 page 212 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) 8.3.8 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8-9 shows the memory map for chain transfer. Source Destination Register information CHNE = 1 DTC vector address Register information start address Register information CHNE = 0 Source Destination Figure 8-9 Chain Transfer Memory Map In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected. Rev. 6.00 Feb 22, 2005 page 213 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) 8.3.9 Operation Timing Figures 8-10 to 8-12 show an example of DTC operation timing. B DTC activation request DTC request Data transfer Vector read Address Transfer information read Read Write Transfer information write Figure 8-10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) B DTC activation request DTC request Vector read Address Transfer information read Data transfer Read Write Read Write Transfer information write Figure 8-11 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) Rev. 6.00 Feb 22, 2005 page 214 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) B DTC activation request DTC request Data transfer Vector read Address Transfer information read Read Write Read Write Data transfer Transfer Transfer information information write read Transfer information write Figure 8-12 DTC Operation Timing (Example of Chain Transfer) 8.3.10 Number of DTC Execution States Table 8-8 lists execution statuses for a single DTC data transfer, and table 8-9 shows the number of states required for each execution status. Table 8-8 DTC Execution Statuses Vector Read I 1 1 1 Register Information Read/Write Data Read J K 6 6 6 1 1 N Data Write L 1 1 N Internal Operations M 3 3 3 Mode Normal Repeat Block transfer N: Block size (initial setting of CRAH and CRAL) Rev. 6.00 Feb 22, 2005 page 215 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) Table 8-9 Number of States Required for Each Execution Status OnChip RAM 32 1 SI SJ -- 1 Vector read Register information read/write Byte data read Word data read Byte data write Word data write OnChip On-Chip I/O ROM Registers External Devices 16 1 1 -- 8 2 -- -- 16 2 -- -- 8 2 4 -- 8 3 6 + 2m -- 16 2 2 -- 16 3 3+m -- Object to be Accessed Bus width Access states Execution status SK SK SL SL 1 1 1 1 1 1 1 1 1 1 2 4 2 4 1 2 2 2 2 1 2 4 2 4 1 3+m 6 + 2m 3+m 6 + 2m 1 2 2 2 2 1 3+m 3+m 3+m 3+m 1 Internal operation SM The number of execution states is calculated from the formula below. Note that means the sum of all transfers activated by one activation event (the number in which the CHNE bit is set to 1, plus 1). Number of execution states = I * (SI + 1) + (J * SJ + K * SK + L * SL) + M * SM For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred from the on-chip ROM to an internal I/O register, the time required for the DTC operation is 14 states. The time from activation to the end of the data write is 11 states. Rev. 6.00 Feb 22, 2005 page 216 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) 8.3.11 Procedures for Using DTC Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Set the corresponding bit in DTCER to 1. [4] Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. [5] After the end of one data transfer, or after the specified number of data transfers have ended, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1. Activation by Software: The procedure for using the DTC with software activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Check that the SWDTE bit is 0. [4] Write 1 to SWDTE bit and the vector number to DTVECR. [5] Check the vector number written to DTVECR. [6] After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the SWDTE bit is held at 1 and a CPU interrupt is requested. Rev. 6.00 Feb 22, 2005 page 217 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) 8.3.12 Examples of Use of the DTC (1) Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. [1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the SCI RDR address in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. [2] Set the start address of the register information at the DTC vector address. [3] Set the corresponding bit in DTCER to 1. [4] Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. [5] Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. [6] When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine should perform wrap-up processing. Rev. 6.00 Feb 22, 2005 page 218 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) (2) Chain Transfer An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to the PPG's NDR is performed in the first half of the chain transfer, and normal mode transfer to the TPU's TGR in the second half. This is because clearing of the activation source and interrupt generation at the end of the specified number of transfers are restricted to the second half of the chain transfer (transfer when CHNE = 0). [1] Perform settings for transfer to the PPG's NDR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0, MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value. [2] Perform settings for transfer to the TPU's TGR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0 = 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address in DAR, and the data table size in CRA. CRB can be set to any value. [3] Locate the TPU transfer register information consecutively after the NDR transfer register information. [4] Set the start address of the NDR transfer register information to the DTC vector address. [5] Set the bit corresponding to TGIA in DTCER to 1. [6] Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA interrupt with TIER. [7] Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to be used as the output trigger. [8] Set the CST bit in TSTR to 1, and start the TCNT count operation. [9] Each time a TGRA compare match occurs, the next output value is transferred to NDR and the set value of the next output trigger period is transferred to TGRA. The activation source TGFA flag is cleared. Rev. 6.00 Feb 22, 2005 page 219 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) [10] When the specified number of transfers are completed (the TPU transfer CRA value is 0), the TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the CPU. Termination processing should be performed in the interrupt handling routine. (3) Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. [1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. [2] Set the start address of the register information at the DTC vector address (H'04C0). [3] Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated by software. [4] Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. [5] Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. [6] If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. [7] After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform other wrap-up processing. Rev. 6.00 Feb 22, 2005 page 220 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) 8.4 Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control. In the case of activation by software, a software activated data transfer end interrupt (SWDTEND) is generated. When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers have ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine should clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1. 8.5 Usage Notes Module Stop: When the MSTPA6 bit in MSTPCRA is set to 1, the DTC clock stops, and the DTC enters the module stop state. However, 1 cannot be written in the MSTPA6 bit while the DTC is operating. On-Chip RAM: The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0. DTCE Bit Setting: For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register. Rev. 6.00 Feb 22, 2005 page 221 of 1484 REJ09B0103-0600 Section 8 Data Transfer Controller (DTC) Rev. 6.00 Feb 22, 2005 page 222 of 1484 REJ09B0103-0600 Section 9 I/O Ports Section 9 I/O Ports 9.1 Overview The chip has 10 I/O ports (ports 1, 3 and A to F, H, J), and two input-only port (ports 4 and 9). Table 9-1 summarizes the port functions. The pins of each port also have other functions. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port register (PORT) used to read the pin states. The input-only ports do not have a DR or DDR register. Ports A to E have an on-chip pull-up MOS function, and in addition to DR and DDR, have a MOS input pull-up control register (PCR) to control the on/off state of MOS input pull-up. Ports 3, and A to C include an open-drain control register (ODR) that controls the on/off state of the output buffer PMOS. When ports 10 to 13 and A to F are used as the output pins for expanded bus control signals, they can drive one TTL load plus a 90pF capacitance load. Those ports in other cases and ports 14 to 17 and 3 can drive one TTL load and a 30pF capacitance load. All I/O ports can drive Darlington transistors when set to output. Port 1 pins (P16 and P14) and port 3 pins (P35 and P32) and port F (PF3 and PF0) are Schmitttrigger inputs. See appendix C, I/O Port Block Diagrams, for a block diagram of each port. Rev. 6.00 Feb 22, 2005 page 223 of 1484 REJ09B0103-0600 Section 9 I/O Ports Table 9-1 Port Port Functions Pins P17/PO15/TIOCB2/ TCLKD P16/PO14/TIOCA2/ 1 QRI Description Mode 4 Mode 5 Mode 6 Mode 7 8-bit I/O port also functioning as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, TIOCB2), PPG output pins (PO15 to PO8), interrupt input pins (IRQ0, ) 1 QRI Port 1 * 8-bit I/O *2 port * Schmitttriggered input (P16, P14) P15/PO13/TIOCB1/ TCLKC P14/PO12/TIOCA1/ 0 QRI 8 bit I/O port also functioning as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, TIOCB2), PPG output pins (PO15 to PO8), interrupt input pins (IRQ0, ), and address outputs (A20 to A23) 1Q RI P13/PO11/TIOCD0/ TCLKB/A23 P12/PO10/TIOCC0/ TCLKA/A22 P11/PO9/TIOCB0/A21 P10/PO8/TIOCA0/A20 Port 4 * 8-bit input *3 port P47/AN7/DA1 P46/AN6/DA0 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 8-bit input port also functioning as A/D converter analog inputs (AN7 to AN0) and D/A converter analog outputs (DA1, DA0) Rev. 6.00 Feb 22, 2005 page 224 of 1484 REJ09B0103-0600 5 QRI 1 * Open-drain P34/RxD1/SDA0* output *1 P33/TxD1/SCL1 capability 1 P32/SCK0/SDA1* / * Schmitttriggered P31/RxD0 input (P35, P30/TxD0 P32) 4 QRI 5 QRI Port 3 * 6-bit I/O port P35/SCK1/SCL0*1/ 6-bit I/O port also functioning as SCI (channel 0, 1) I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1), interrupt input pins (IRQ4, ), IIC (channel 0, 1) I/O pins (SCL0, SDA0, SCL1, SDA1) *1 Section 9 I/O Ports Port Description Pins P93/AN11 P92/AN10 P91/AN9 P90/AN8 Port A * 4-bit I/O port * On-chip MOS input pull-up * Open-drain output capability Port B * 8-bit I/O port * On-chip MOS input pull-up PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 8-bit I/O port also functioning as TPU I/O pins (TIOCB5, TIOCA5, TIOCB4, TIOCA4, TIOCD3, TIOCC3, TIOCB3, TIIOCA3) and address outputs (A15 to A8) 8-bit I/O port also functioning as TPU I/O pins (TIOCB5, TIOCA5, TIOCB4, TIOCA4, TIOCD3, TIOCC3, TIOCB3, TIIOCA3) I/O port PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 4-bit I/O port also functioning as SCI (channel 2) I/O pins (TxD2, RxD2, SCK2) and address outputs (A19 to A16) 4-bit I/O port also functioning as SCI (channel 2) I/O pins (TxD2, RxD2, SCK2) Mode 4 Mode 5 Mode 6 Mode 7 Port 9 * 4-bit input port 4-bit input port also functioning as A/D converter analog inputs (AN11 to AN8) * Open-drain PB3/A11/TIOCD3 output PB2/A10/TIOCC3 capability PB1/A9/TIOCB3 PB0/A8/TIOCA3 Port C * 8-bit I/O port * On-chip MOS input pull-up PC7/A7 PC6/A6 PC5/A5 PC4/A4 8-bit I/O port also functioning as address outputs (A7 to A0) * Open-drain PC3/A3 output PC2/A2 capability PC1/A1 PC0/A0 Port D * 8-bit I/O port * On-chip MOS input pull-up PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8 Data bus input/output I/O port Rev. 6.00 Feb 22, 2005 page 225 of 1484 REJ09B0103-0600 Section 9 I/O Ports Port Description PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 Port F * 6-bit I/O port * Schmitttriggered input (PF3, PF0) PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/ 3 QRI Pins Mode 4 Mode 5 Mode 6 Mode 7 I/O port Port E * 8-bit I/O port * On-chip MOS input pull-up In 8-bit-bus mode: I/O port In 16-bit-bus mode: data bus input/output PF7/ When DDR = 0: input port When DDR = 1 (after reset): output When DDR = 0 (after reset): input port When DDR = 1: output input Port H * 8-bit I/O port PH7/PWM1H PH6/PWM1G PH5/PWM1F PH4/PWM1E PH3/PWM1D PH2/PWM1C PH1/PWM1B PH0/PWM1A PJ7/PWM2H PJ6/PWM2G PJ5/PWM2F PJ4/PWM2E PJ3/PWM2D PJ2/PWM2C PJ1/PWM2B PJ0/PWM2A Function as both Motor Control PWM Timer output pins and 8bit I/O port. Port J * 8-bit I/O port Function as both Motor Control PWM Timer output pins and 8bit I/O port. Notes: 1. Pins for I2C bus interface. I2C bus interface is available as an option in the H8S/2638, H8S/2639, and H8S/2630. 2. The PPG output is not implemented in the H8S/2635 Group. 3. The DA output is not implemented in the H8S/2635 Group. Rev. 6.00 Feb 22, 2005 page 226 of 1484 REJ09B0103-0600 2 QRI PF0/IRQ2 input, I/O port 3 QRI G RTDA 3 QRI , RWL RWH DR G RTDA , , outputs I/O port , input Section 9 I/O Ports 9.2 Port 1 Note: The PPG output is not implemented in the H8S/2635 Group. 9.2.1 Overview Port 1 is an 8-bit I/O port. Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), external interrupt pins (IRQ0 and ), and address bus output pins (A23 to A20). Port 1 pin functions change according to the operating mode. Figure 9-1 shows the port 1 pin configuration. Port 1 pins Pin functions in modes 4 to 6 P17 (I/O) / PO15 (output) / TIOCB2 (I/O) / TCLKD (input) P16 (I/O) / PO14 (output) / TIOCA2 (I/O) / IRQ1 (input) P15 (I/O) / PO13 (output) / TIOCB1 (I/O) / TCLKC (input) Port 1 P14 (I/O) / PO12 (output) / TIOCA1 (I/O) / IRQ0 (input) P13 (I/O) / PO11 (output) / TIOCD0 (I/O) / TCLKB (input) / A23 (output) P12 (I/O) / PO10 (output) / TIOCC0 (I/O) / TCLKA (input) / A22 (output) P11 (I/O) / PO9 (output) / TIOCB0 (I/O) / A21 (output) P10 (I/O) / PO8 (output) / TIOCA0 (I/O) / A20 (output) Pin functions in mode 7 P17 (I/O) / PO15 (output) / TIOCB2 (I/O) / TCLKD (input) P16 (I/O) / PO14 (output) / TIOCA2 (I/O) / IRQ1 (input) P15 (I/O) / PO13 (output) / TIOCB1 (I/O) / TCLKC (input) P14 (I/O) / PO12 (output) / TIOCA1 (I/O) / IRQ0 (input) P13 (I/O) / PO11 (output) / TIOCD0 (I/O) / TCLKB (input) P12 (I/O) / PO10 (output) / TIOCC0 (I/O) / TCLKA (input) P11 (I/O) / PO9 (output) / TIOCB0 (I/O) P10 (I/O) / PO8 (output) / TIOCA0 (I/O) 1QRI Figure 9-1 Port 1 Pin Functions Rev. 6.00 Feb 22, 2005 page 227 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.2.2 Register Configuration Table 9-2 shows the port 1 register configuration. Table 9-2 Name Port 1 data direction register Port 1 data register Port 1 register Port 1 Registers Abbreviation P1DDR P1DR PORT1 R/W W R/W R Initial Value H'00 H'00 Undefined Address* H'FE30 H'FF00 H'FFB0 Note: * Lower 16 bits of the address. Port 1 Data Direction Register (P1DDR) Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : R/W : P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read. Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P1DDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port 1 Data Register (P1DR) Bit : 7 P17DR Initial value : R/W : 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10). P1DR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Rev. 6.00 Feb 22, 2005 page 228 of 1484 REJ09B0103-0600 Section 9 I/O Ports Port 1 Register (PORT1) Bit : 7 P17 --* R 6 P16 --* R 5 P15 --* R 4 P14 --* R 3 P13 --* R 2 P12 --* R 1 P11 --* R 0 P10 --* R Initial value : R/W : Note: * Determined by state of pins P17 to P10. PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 1 pins (P17 to P10) must always be performed on P1DR. If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while P1DDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORT1 contents are determined by the pin states, as P1DDR and P1DR are initialized. PORT1 retains its prior state in software standby mode. 9.2.3 Pin Functions Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and ), and address bus output pins (A23 to TIOCB2), external interrupt input pins (IRQ0 and A20). Port 1 pin functions are shown in table 9-3. Note: The PPG output is not implemented in the H8S/2635 Group. 1QRI Rev. 6.00 Feb 22, 2005 page 229 of 1484 REJ09B0103-0600 Section 9 I/O Ports Table 9-3 Pin P17/PO15/ TIOCB2/ TCLKD Port 1 Pin Functions Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0 in TIOR2, and bits CCLR1 and CCLR0 in TCR2), bits TPSC2 to TPSC0 in TCR0 and TCR5, bit NDER15 in NDERH, and bit P17DDR. TPU Channel 2 Setting P17DDR NDER15 Pin function Table Below (1) -- -- TIOCB2 output 0 -- P17 input Table Below (2) 1 0 P17 output 1 1 PO15 output TIOCB2 input *1 TCLKD input *2 Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 = 1. 2. TCLKD input when the setting for either TCR0 or TCR5 is: TPSC2 to TPSC0 = B'111. TCLKD input when channels 2 and 4 are set to phase counting mode. TPU Channel 2 Setting MD3 to MD0 IOB3 to IOB0 (2) B'0000 B'0100 B'1xxx CCLR1, CCLR0 Output function -- -- (1) B'0001 to B'0011 B'0101 to B'0111 -- Output compare output -- -- -- -- Other than B'10 PWM mode 2 output B'10 -- (2) B'0010 -- B'xx00 (2) (1) B'0011 Other than B'xx00 (2) B'0000, B'01xx x: Don't care Rev. 6.00 Feb 22, 2005 page 230 of 1484 REJ09B0103-0600 Section 9 I/O Ports Pin P16/PO14/ TIOCA2/ 1QRI Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0 in TIOR2, and bits CCLR1 and CCLR0 in TCR2), bit NDER14 in NDERH, and bit P16DDR. TPU Channel 2 Setting P16DDR NDER14 Pin function Table Below (1) -- -- TIOCA2 output 0 -- P16 input Table Below (2) 1 0 P16 output 1 1 PO14 output TIOCA2 input *1 input 1QRI TPU Channel 2 Setting MD3 to MD0 IOA3 to IOA0 (2) B'0000 B'0100 B'1xxx (1) B'0001 to B'0011 B'0101 to B'0111 -- Output compare output (2) B'001x B'xx00 (1) B'0010 (1) B'0011 Other than B'xx00 (2) B'0000, B'01xx CCLR1, CCLR0 Output function -- -- -- -- -- Other than B'01 B'01 -- PWM PWM mode 1 mode 2 output *2 output x: Don't care Notes: 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 = 1. 2. TIOCB2 output is disabled. Rev. 6.00 Feb 22, 2005 page 231 of 1484 REJ09B0103-0600 Section 9 I/O Ports Pin P15/PO13/ TIOCB1/TCLKC Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bits TPSC2 to TPSC0 in TCR0, TCR2, TCR4, and TCR5, bit NDER13 in NDERH, and bit P15DDR. TPU Channel 1 Setting P15DDR NDER13 Pin function Table Below (1) -- -- TIOCB1 output 0 -- P15 input Table Below (2) 1 0 P15 output 1 1 PO13 output TIOCB1 input *1 TCLKC input *2 Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 to IOB0 = B'10xx. 2. TCLKC input when the setting for either TCR0 or TCR2 is: TPSC2 to TPSC0 = B'110; or when the setting for either TCR4 or TCR5 is TPSC2 to TPSC0 = B'101. TCLKC input when channels 2 and 4 are set to phase counting mode. TPU Channel 1 Setting MD3 to MD0 IOB3 to IOB0 (2) B'0000 B'0100 B'1xxx CCLR1, CCLR0 Output function -- (1) B'0001 to B'0011 B'0101 to B'0111 -- -- -- Other than B'10 PWM mode 2 output B'10 (2) B'0010 -- B'xx00 (2) (1) B'0011 Other than B'xx00 (2) B'0000, B'01xx -- Output compare output -- -- -- x: Don't care Rev. 6.00 Feb 22, 2005 page 232 of 1484 REJ09B0103-0600 Section 9 I/O Ports Pin P14/PO12/ TIOCA1/IRQ0 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bit NDER12 in NDERH, and bit P14DDR. TPU Channel 1 Setting P14DDR NDER12 Pin function Table Below (1) -- -- TIOCA1 output 0 -- P14 input input Table Below (2) 1 0 P14 output 1 1 PO12 output TIOCA1 input *1 TPU Channel 1 Setting MD3 to MD0 IOA3 to IOA0 (2) B'0000 B'0100 B'1xxx (1) B'0001 to B'0011 B'0101 to B'0111 -- Output compare output (2) B'001x B'xx00 B'0000, B'01xx CCLR1, CCLR0 Output function -- -- -- -- Notes: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 to IOA0 = B'10xx. 2. TIOCB1 output is disabled. Rev. 6.00 Feb 22, 2005 page 233 of 1484 REJ09B0103-0600 0QRI (1) B'0010 (1) B'0011 Other than B'xx00 (2) -- PWM mode 1 output*2 Other than B'01 PWM mode 2 output B'01 -- x: Don't care Section 9 I/O Ports Pin P13/PO11/ TIOCD0/TCLKB/ A23 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR2, bits AE3 to AE0 in PFCR, bit NDER11 in NDERH, and bit P13DDR. Operating mode AE3 to AE0 TPU Channel 0 Setting P13DDR NDER11 Pin function Table Below (1) -- -- TIOCD0 output 0 -- P13 input Modes 4 to 6 B'0000 to B'1110 Table Below (2) 1 0 P13 output 1 1 PO11 output B'1111 -- -- -- A23 output TIOCD0 input *1 TCLKB input *2 Operating mode AE3 to AE0 TPU Channel 0 Setting P13DDR NDER11 Pin function Table Below (1) -- -- TIOCD0 output 0 -- P13 input Mode 7 -- Table Below (2) 1 0 P13 output 1 1 PO11 output TIOCD0 input *1 TCLKB input *2 Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000, and IOD3 to IOD0 = B'10xx. 2. TCLKB input when the setting for TCR0 to TCR2 is: TPSC2 to TPSC0 = B'101. TCLKB input when channels 1 and 5 are set to phase counting mode. Rev. 6.00 Feb 22, 2005 page 234 of 1484 REJ09B0103-0600 Section 9 I/O Ports Pin P13/PO11/ TIOCD0/TCLKB/ A23 Selection Method and Pin Functions TPU Channel 0 Setting MD3 to MD0 IOD3 to IOD0 (2) B'0000 B'0000 B'0100 B'1xxx (1) B'0001 to B'0011 B'0101 to B'0111 -- (2) B'0010 -- (2) B'xx00 (1) B'0011 (2) Other than B'xx00 CCLR2 to CCLR0 Output function -- -- -- Other than B'110 PWM mode 2 output B'110 -- Output compare output -- -- -- x: Don't care Rev. 6.00 Feb 22, 2005 page 235 of 1484 REJ09B0103-0600 Section 9 I/O Ports Pin P12/PO10/ TIOCC0/TCLKA/ A22 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR5, bits AE3 to AE0 in PFCR, bit NDER10 in NDERH, and bit P12DDR. Operating mode AE3 to AE0 TPU Channel 0 Setting P12DDR NDER10 Pin function Table Below (1) -- -- TIOCC0 output 0 -- P12 input Modes 4 to 6 B'0000 to B'1110 Table Below (2) 1 0 P12 output 1 1 PO10 output B'1111 -- -- -- A22 output TIOCC0 input *1 TCLKA input *2 Operating mode AE3 to AE0 TPU Channel 0 Setting P12DDR NDER10 Pin function Table Below (1) -- -- TIOCC0 output 0 -- P12 input Mode 7 -- Table Below (2) 1 0 P12 output 1 1 PO10 output TIOCC0 input *1 TCLKA input *2 Rev. 6.00 Feb 22, 2005 page 236 of 1484 REJ09B0103-0600 Section 9 I/O Ports Pin P12/PO10/ TIOCC0/TCLKA/ A22 Selection Method and Pin Functions TPU Channel 0 Setting MD3 to MD0 IOC3 to IOC0 (2) B'0000 B'0000 B'0100 B'1xxx (1) B'0001 to B'0011 B'0101 to B'0111 -- (2) B'001x B'xx00 (1) B'0010 (1) B'0011 Other than B'xx00 (2) CCLR2 to CCLR0 Output function -- -- -- Other than B'101 PWM mode 2 output B'101 -- Output compare output -- PWM mode 1 output*3 -- x: Don't care Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000, and IOC3 to IOC0 = B'10xx. 2. TCLKA input when the setting for TCR0 to TCR5 is: TPSC2 to TPSC0 = B'100. TCLKA input when channels 1 and 5 are set to phase counting mode. 3. TIOCD0 output is disabled. When BFA = 1 or BFB = 1 in TMDR0, output is disabled and setting (2) applies. Rev. 6.00 Feb 22, 2005 page 237 of 1484 REJ09B0103-0600 Section 9 I/O Ports Pin Selection Method and Pin Functions P11/PO9/TIOCB0/ The pin function is switched as shown below according to the combination of A21 the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, and bits IOB3 to IOB0 in TIOR0H), bits AE3 to AE0 in PFCR, bit NDER9 in NDERH, and bit P11DDR. Operating mode AE3 to AE0 TPU Channel 0 Setting P11DDR NDER9 Pin function Table Below (1) -- -- TIOCB0 output 0 -- P11 input Modes 4 to 6 B'0000 to B'1101 Table Below (2) 1 0 P11 output TIOCB0 input * Operating mode AE3 to AE0 TPU Channel 0 Setting P11DDR NDER9 Pin function Table Below (1) -- -- TIOCB0 output 0 -- P11 input Mode 7 -- Table Below (2) 1 0 P11 output TIOCB0 input * Note: * TIOCB0 input when MD3 to MD0 = B'0000, and IOB3 to IOB0 = B'10xx. 1 1 PO9 output 1 1 PO9 output B'1110 to B'1111 -- -- -- A21 output Rev. 6.00 Feb 22, 2005 page 238 of 1484 REJ09B0103-0600 Section 9 I/O Ports Pin Selection Method and Pin Functions P11/PO9/TIOCB0/ TPU Channel A21 0 Setting MD3 to MD0 IOB3 to IOB0 (2) B'0000 B'0000 B'0100 B'1xxx (1) B'0001 to B'0011 B'0101 to B'0111 -- (2) B'0010 -- (2) B'xx00 (1) B'0011 (2) Other than B'xx00 CCLR2 to CCLR0 Output function -- -- -- Other than B'010 PWM mode 2 output B'010 -- Output compare output -- -- -- x: Don't care Rev. 6.00 Feb 22, 2005 page 239 of 1484 REJ09B0103-0600 Section 9 I/O Ports Pin Selection Method and Pin Functions P10/PO8/TIOCA0/ The pin function is switched as shown below according to the combination of A20 the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bits AE3 to AE0 in PFCR, bit NDER8 in NDERH, SAE0 bit in DMABCRH, and bit P10DDR. Operating mode AE3 to AE0 TPU Channel 0 Setting P10DDR NDER8 Pin function Table Below (1) -- -- TIOCA0 output 0 -- P10 input Modes 4 to 6 B'0000 to B'1110 Table Below (2) 1 0 P10 output TIOCA0 input *1 Operating mode AE3 to AE0 TPU Channel 0 Setting P10DDR NDER8 Pin function Table Below (1) -- -- TIOCA0 output 0 -- P10 input Mode 7 -- Table Below (2) 1 0 P10 output TIOCA0 input *1 1 1 PO8 output 1 1 PO8 output B'1101 to B'1111 -- -- -- A20 output Rev. 6.00 Feb 22, 2005 page 240 of 1484 REJ09B0103-0600 Section 9 I/O Ports Pin Selection Method and Pin Functions P10/PO8/TIOCA0/ TPU Channel A20 0 Setting MD3 to MD0 IOA3 to IOA0 (2) B'0000 B'0000 B'0100 B'1xxx (1) B'0001 to B'0011 B'0101 to B'0111 -- (2) B'001x B'xx00 (1) B'0010 (1) B'0011 Other than B'xx00 (2) CCLR2 to CCLR0 Output function -- -- -- Other than B'001 PWM mode 2 output B'001 -- Output compare output -- PWM mode 1 output*2 -- x: Don't care Notes: 1. TIOCA0 input when MD3 to MD0 = B'0000, and IOA3 to IOA0 = B'10xx. 2. TIOCB0 output is disabled. Rev. 6.00 Feb 22, 2005 page 241 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.3 9.3.1 Port 3 Overview Port 3 is an 6-bit I/O port. Port 3 is a multi-purpose port for SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1), external interrupt input pins (IRQ4, ), and IIC I/O pins* (SCL0, SDA0, SCL1, SDA1). All of the port 3 pin functions have the same operating mode. The configuration for each of the port 3 pins is shown in figure. 9-2. Note: * Available when using I2C bus interface as an option in the H8S/2638, H8S/2639, and H8S/2630 (the product equipped with the I2C bus interface is the W-mask version). Port 3 pins P35 (I/O) / SCK1 (I/O) / SCL0* (I/O) / IRQ5 (input) P34 (I/O) / RxD1 (input) / SDA0* (I/O) P33 (I/O) / TxD1 (input) / SCL1* (I/O) Port 3 P32 (I/O) / SCK0 (I/O) / SDA1* (I/O) / IRQ4 (input) P31 (I/O) / RxD0 (input) P30 (I/O) / TxD0 (output) 5QRI Note: * Available when using I2C bus interface as an option in the H8S/2638, H8S/2639, and H8S/2630 (the product equipped with the I2C bus interface is the W-mask version). Figure 9-2 Port 3 Pin Functions Rev. 6.00 Feb 22, 2005 page 242 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.3.2 Register Configuration Table 9-4 shows the configuration of port 3 registers. Table 9-4 Name Port 3 data direction register Port 3 data register Port 3 register Port 3 open drain control register Notes: 1. Lower 16 bits of the address. 2. Value of bits 5 to 0. Port 3 Register Configuration Abbreviation P3DDR P3DR PORT3 P3ODR R/W W R/W R R/W Initial Value*2 B'**000000 B'**000000 Undefined B'**000000 Address*1 H'FE32 H'FF02 H'FFB2 H'FE46 Port 3 Data Direction Register (P3DDR) Bit Initial value Read/Write 3/4 3/4 7 3/4 3/4 6 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Undefined Undefined P3DDR is an 8-bit write-dedicated register, which specifies the I/O for each port 3 pin by bit. Read is disenabled. If a read is carried out, undefined values are read out. By setting P3DDR to 1, the corresponding port 3 pins become output, and be clearing to 0 they become input. P3DDR is initialized to B'**000000 by a reset and in hardware standby mode. The previous state is maintained in software standby mode. The pin state is determined by specifying SCI, IIC*, P3DDR, and P3DR. Note: * Available when using I2C bus interface as an option in the H8S/2638, H8S/2639, and H8S/2630 (the product equipped with the I2C bus interface is the W-mask version). Rev. 6.00 Feb 22, 2005 page 243 of 1484 REJ09B0103-0600 Section 9 I/O Ports Port 3 Data Register (P3DR) Bit Initial value Read/Write 3/4 3/4 7 3/4 3/4 6 5 P35DR 0 R/W 4 P34DR 0 R/W 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 P30DR 0 R/W Undefined Undefined P3DR is an 8-bit readable/writable register, which stores the output data of port 3 pins (P35 to P30). P3DR is initialized to B'**000000 by a reset and in hardware standby mode. The previous state is maintained in software standby mode. Port 3 Register (PORT3) Bit Initial value Read/Write 3/4 3/4 7 3/4 3/4 6 5 P35 4 P34 3 P33 2 P32 1 P31 0 P30 Undefined Undefined 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R Note: * Determined by the state of pins P35 to P30. PORT3 is an 8-bit read-dedicated register, which reflects the state of pins. Write is disenabled. Always carry out writing off output data of port 3 pins (P35 to P30) to P3DR without fail. When P3DDR is set to 1, if port 3 is read, the values of P3DR are read. When P3DDR is cleared to 0, if port 3 is read, the states of pins are read out. P3DDR and P3DR are initialized by a reset and in hardware standby mode, so PORT3 is determined by the state of the pins. The previous state is maintained in software standby mode. Rev. 6.00 Feb 22, 2005 page 244 of 1484 REJ09B0103-0600 Section 9 I/O Ports Port 3 Open Drain Control Register (P3ODR) Bit Initial value Read/Write 3/4 3/4 7 3/4 3/4 6 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR Undefined Undefined P3ODR is an 8-bit readable/writable register, which controls the on/off of port 3 pins (P35 to P30). By setting P3ODR to 1, the port 3 pins become an open drain out, and when cleared to 0 they become CMOS output. P3ODR is initialized to B'**000000 by a reset and in hardware standby mode. The previous state is maintained in software standby mode. 9.3.3 Pin Functions The port 3 pins double as SCI I/O input pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1) ), and IIC I/O pins* (SCL0, SDA0, SCL1, and external interrupt input pins (IRQ4 and SDA1). The functions of port 3 pins are shown in table 9-5. Note: * Available when using I2C bus interface as an option in the H8S/2638, H8S/2639, and H8S/2630 (the product equipped with the I2C bus interface is the W-mask version). 5QRI Rev. 6.00 Feb 22, 2005 page 245 of 1484 REJ09B0103-0600 Section 9 I/O Ports Table 9-5 Pin Port 3 Pin Functions Selection Method and Pin Functions P35/SCK1/ Switches as follows according to combinations of ICCR0 ICE bit*1 of IIC0, bit C/A of *1/IRQ5 SMR1, bits CKE0 and CKE1 of SCR1, and bit P35DDR. SCL0 When used as a SCL0 I/O pin, always be sure to clear the following bits to 0: bit C/A of SMR1, and bits CKE0 and CKE1 of SCR1. The SCL0 output format is NMOS open drain output, enabling direct bus driving. ICE*1 0 1 CKE1 C/A CKE0 P35DDR Pin function 0 P35 input 0 1 P35 output* 0 1 -- SCK1 output* 5QRI 0 1 -- -- SCK1 output* input 1 -- -- -- SCK1 input 0 0 0 -- SCL0 I/O P34/RxD1/ 1 SDA0* Note: * When P35ODR = 1, it becomes NMOS open drain output. In W mask-ROM versions, the output format is NMOS push-pull. However, it becomes NMOS open drain output when P35ODR = 1. Switches as follows according to combinations of ICCR0 ICE bit*1 of IIC0, bit RE of SCR1 and bit P34DDR. The SDA0 output format is NMOS open drain output, enabling direct bus driving. ICE*1 0 1 RE P34DDR Pin function 0 P34 input 0 1 P34 output* 1 -- RxD1 input -- -- SDA0 I/O Note: * When P34ODR = 1, it becomes NMOS open drain output. In W mask-ROM versions, the output format is NMOS push-pull. However, it becomes NMOS open drain output when P34ODR = 1. Rev. 6.00 Feb 22, 2005 page 246 of 1484 REJ09B0103-0600 Section 9 I/O Ports Pin P33/TxD1/ SCL1*1 Selection Method and Pin Functions Switches as follows according to combinations of ICCR1 ICE bit*1 of IIC1, bit TE of SCR1 and bit P33DDR. The SCL1 output format is NMOS open drain output, enabling direct bus driving. ICE*1 0 1 TE P33DDR Pin function 0 P33 input 0 1 P33 output* 1 -- TxD1 output* -- -- SCL1 I/O Note: * When P33ODR = 1, it becomes NMOS open drain output. P32/SCK0/ Switches as follows according to combinations of ICCR1 ICE bit*1 of IIC1, bit C/A of *1/IRQ4 SMR0, bits CKE0 and CKE1 of SCR0, and bit P32DDR. When used as a SDA1 I/O SDA1 pin, always be sure to clear the following bits to 0: SMR0 C/A bit, SCR0 CKE0 and CKE1 bits. The SDA1 output format is NMOS open drain output, enabling direct bus driving. ICE*1 0 1 CKE1 C/A CKE0 P32DDR Pin function 0 P32 input 0 1 P32 output 0 1 -- SCK0 output* 4QRI 0 1 -- -- SCK0 output* input 1 -- -- -- SCK0 input 0 0 0 -- SDA1 I/O Note: * When P32ODR = 1, it becomes NMOS open drain output. P31/RxD0/ IrRxD Switches as follows according to combinations of bit RE of SCR0 and bit P31DDR. RE P31DDR Pin function P30/TxD0/ IrTxD 0 P31 input 0 1 P31 output* 1 -- RxD0 input Note: * When P31ODR = 1, it becomes NMOS open drain output. Switches as follows according to combinations of bit TE of SCR0 and bit P30DDR. TE P30DDR Pin function 0 P30 input 0 1 P30 output* 1 -- TxD0 output* Note: * When P30ODR = 1, it becomes NMOS open drain output. Note: 1. Available when using I2C bus interface (the W-mask version of the H8S/2638, H8S/2639, and H8S/2630 only). In W mask-ROM versions, the output format is NMOS push-pull. However, it becomes NMOS open drain output when P34ODR = 1 and P35ODR = 1. Rev. 6.00 Feb 22, 2005 page 247 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.4 Port 4 Note: The DA output is not implemented in the H8S/2635 Group. 9.4.1 Overview Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0, DA1). Port 4 pin functions are the same in all operating modes. Figure 9-3 shows the port 4 pin configuration. Port 4 pins P47 (input) / AN7 (input) / DA1 (output) P46 (input) / AN6 (input) / DA0 (output) P45 (input) / AN5 (input) Port 4 P44 (input) / AN4 (input) P43 (input) / AN3 (input) P42 (input) / AN2 (input) P41 (input) / AN1 (input) P40 (input) / AN0 (input) Figure 9-3 Port 4 Pin Functions Rev. 6.00 Feb 22, 2005 page 248 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.4.2 Register Configuration Table 9-6 shows the port 4 register configuration. Port 4 is an input-only port, and does not have a data direction register or data register. Table 9-6 Name Port 4 register Port 4 Registers Abbreviation PORT4 R/W R Initial Value Undefined Address* H'FFB3 Note: * Lower 16 bits of the address. Port 4 Register (PORT4): The pin states are always read when a port 4 read is performed. Bit : 7 P47 --* R 6 P46 --* R 5 P45 --* R 4 P44 --* R 3 P43 --* R 2 P42 --* R 1 P41 --* R 0 P40 --* R Initial value : R/W : Note: * Determined by state of pins P47 to P40. 9.4.3 Pin Functions Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0 and DA1). Rev. 6.00 Feb 22, 2005 page 249 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.5 9.5.1 Port 9 Overview Port 9 is a 4-bit input-only port. Port 9 pins also function as A/D converter analog input pins (AN8 to AN11). Port 9 pin functions are the same in all operating modes. Figure 9-4 shows the port 9 pin configuration. Port 9 pins P93 (input) / AN11 (input) Port 9 P92 (input) / AN10 (input) P91 (input) / AN9 (input) P90 (input) / AN8 (input) Figure 9-4 Port 9 Pin Functions Rev. 6.00 Feb 22, 2005 page 250 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.5.2 Register Configuration Table 9-7 shows the port 9 register configuration. Port 9 is an input-only port, and does not have a data direction register or data register. Table 9-7 Name Port 9 register Port 9 Registers Abbreviation PORT9 R/W R Initial Value Undefined Address* H'FFB8 Note: * Lower 16 bits of the address. Port 9 Register (PORT9): The pin states are always read when a port 9 read is performed. Bit : 7 -- Initial value : R/W : --* -- 6 -- --* -- 5 -- --* -- 4 -- --* -- 3 P93 --* R 2 P92 --* R 1 P91 --* R 0 P90 --* R Note: * Determined by state of pins P93 to P90. 9.5.3 Pin Functions Port 9 pins also function as A/D converter analog input pins (AN8 to AN11) are multipurpose pins which function as A/D converter analog input pins (AN8 to AN11). Rev. 6.00 Feb 22, 2005 page 251 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.6 9.6.1 Port A Overview Port A is a 4-bit I/O port. Port A pins also function as address bus outputs and SCI2 I/O pins (SCK2, RxD2, and TxD2). The pin functions change according to the operating mode. Port A has an on-chip MOS input pull-up function that can be controlled by software. Figure 9-5 shows the port A pin configuration. Port A pins PA3/A19/SCK2 Port A PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 Pin functions in modes 4 to 6 PA3 (I/O) / A19 (output) / SCK2 (I/O) PA2 (I/O) / A18 (output) / RxD2 (input) PA1 (I/O) / A17 (output) / TxD2 (output) PA0 (I/O) / A16 (output) Pin functions in mode 7 PA3 (I/O) / SCK2 (output) PA2 (I/O) / RxD2 (input) PA1 (I/O) / TxD2 (output) PA0 (I/O) Figure 9-5 Port A Pin Functions Rev. 6.00 Feb 22, 2005 page 252 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.6.2 Register Configuration Table 9-8 shows the port A register configuration. Table 9-8 Name Port A data direction register Port A data register Port A register Port A MOS pull-up control register Port A open-drain control register Port A Registers Abbreviation PADDR PADR PORTA PAPCR PAODR R/W W R/W R R/W R/W Initial Value*2 H'0 H'0 Undefined H'0 H'0 Address*1 H'FE39 H'FF09 H'FFB9 H'FF40 H'FF47 Notes: 1. Lower 16 bits of the address. 2. Value of bits 3 to 0. Port A Data Direction Register (PADDR) Bit : 7 -- R/W : -- 6 -- -- 5 -- -- 4 -- -- 3 0 W 2 0 W 1 0 W 0 0 W PA3DDR PA2DDR PA1DDR PA0DDR Initial value : Undefined Undefined Undefined Undefined PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port A. PADDR cannot be read; if it is, an undefined value will be read. Bits 7 to 4 are reserved; they return an undetermined value if read. PADDR is initialized to H'0 (bits 3 to 0) by a reset, and in hardware standby mode. It retains its prior state in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 4 to 6 The corresponding port A pins become address outputs in accordance with the setting of bits AE3 to AE0 in PFCR, irrespective of the value of bits PA3DDR to PA0DDR. When pins are not used as address outputs, setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the pin an input port. Rev. 6.00 Feb 22, 2005 page 253 of 1484 REJ09B0103-0600 Section 9 I/O Ports * Mode 7 Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the pin an input port. Port A Data Register (PADR) Bit : 7 -- R/W : -- 6 -- -- 5 -- -- 4 -- -- 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W 0 PA0DR 0 R/W Initial value : Undefined Undefined Undefined Undefined PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA3 to PA0). Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. PADR is initialized to H'0 (bits 3 to 0) by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port A Register (PORTA) Bit : 7 -- R/W : -- 6 -- -- 5 -- -- 4 -- -- 3 PA3 --* R 2 PA2 --* R 1 PA1 --* R 0 PA0 --* R Initial value : Undefined Undefined Undefined Undefined Note: * Determined by state of pins PA3 to PA0. PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port A pins (PA3 to PA0) must always be performed on PADR. Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A read is performed while PADDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTA contents are determined by the pin states, as PADDR and PADR are initialized. PORTA retains its prior state in software standby mode. Rev. 6.00 Feb 22, 2005 page 254 of 1484 REJ09B0103-0600 Section 9 I/O Ports Port A MOS Pull-Up Control Register (PAPCR) Bit : 7 -- R/W : -- 6 -- -- 5 -- -- 4 -- -- 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PA3PCR PA2PCR PA1PCR PA0PCR Initial value : Undefined Undefined Undefined Undefined PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port A on an individual bit basis. Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the SCI's SCMR, SMR, and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin. In mode 7, if a pin is in the input state in accordance with the settings in the SCI's SCMR, SMR, and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin. PAPCR is initialized by a reset or to H'0 (bits 3 to 0), and in hardware standby mode. It retains its prior state in software standby mode. Port A Open Drain Control Register (PAODR) Bit : 7 -- R/W : -- 6 -- -- 5 -- -- 4 -- -- 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PA3ODR PA2ODR PA1ODR PA0ODR Initial value : Undefined Undefined Undefined Undefined PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each port A pin (PA3 to PA0). Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. When pins are not address outputs in accordance with the setting of bits AE3 to AE0 in PFCR, setting a PAODR bit makes the corresponding port A pin an NMOS open-drain output, while clearing the bit to 0 makes the pin a CMOS output. PAODR is initialized to H'0 (bits 3 to 0) by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Rev. 6.00 Feb 22, 2005 page 255 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.6.3 Pin Functions Port A pins also function as SCI input/output pins (TxD2, RxD2, SCK2) and address bus output pins (A19 to A16). Port A pin functions are shown in table 9-9. Table 9-9 Pin PA3/A19/SCK2 Port A Pin Functions Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, bits AE3 to AE0 in PFCR, bit C/A in SMR and bits CKE0 and CKE1 in SCR of SCI2, and bit PA3DDR. Operating mode AE3 to AE0 CKE1 C/A CKE0 PA3DDR Pin function 0 PA3 input 0 1 PA3 output 0 1 -- SCK2 output 0 1 -- -- SCK2 output Mode 7 0 0 0 0 PA3 input 1 PA3 output 1 -- SCK2 output 1 -- -- SCK2 output 1 -- -- -- SCK2 input Modes 4 to 6 B'0000 to B'1011 1 -- -- -- SCK2 input B'1100 to B'1111 -- -- -- -- A19 output Operating mode CKE1 C/A CKE0 PA3DDR Pin function Rev. 6.00 Feb 22, 2005 page 256 of 1484 REJ09B0103-0600 Section 9 I/O Ports Pin PA2/A18/RxD2 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, bits AE3 to AE0 in PFCR, bit RE in SCR of SCI2, and bit PA2DDR. Operating mode AE3 to AE0 RE PA2DDR Pin function Operating mode RE PA2DDR Pin function PA1/A17/TxD2 0 PA2 input 0 1 PA2 output 0 PA2 input 0 1 PA2 output Modes 4 to 6 B'0000 to B'1011 1 -- RxD2 input Mode 7 1 -- RxD2 input B'1011 to B'1111 -- -- A18 output The pin function is switched as shown below according to the operating mode, bits AE3 to AE0 in PFCR, bit TE in SCR of SCI2, and bit PA1DDR. Operating mode AE3 to AE0 TE PA1DDR Pin function Operating mode TE PA1DDR Pin function 0 PA1 input 0 1 PA1 output 0 PA1 input 0 1 PA1 output Modes 4 to 6 B'0000 to B'1001 1 -- TxD2 output Mode 7 1 -- TxD2 output B'1010 to B'1111 -- -- A17 output Rev. 6.00 Feb 22, 2005 page 257 of 1484 REJ09B0103-0600 Section 9 I/O Ports Pin PA0/A16 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, bits AE3 to AE0 in PFCR, and bit PA0DDR. Operating mode AE3 to AE0 PA0DDR Pin function Operating mode PA0DDR Pin function 0 PA0 input 0 PA0 input Modes 4 to 6 B'0000 to B'1000 1 PA0 output Mode 7 1 PA0 output B'1001 to B'1111 -- A16 output 9.6.4 Pin Functions Modes 4 to 6: In modes 4 to 6, port A pins function as address outputs according to the setting of AE3 to AE0 in PFCR; when they do not function as address outputs, the pins function as SCI I/O pins and I/O ports. Port A pin functions in modes 4 to 6 are shown in figure 9-6. PA3 (I/O) / A19 (output) / SCK2 (I/O) Port A PA2 (I/O) / A18 (output) / RxD2 (input) PA1 (I/O) / A17 (output) / TxD2 (output) PA0 (I/O) / A16 (output) Figure 9-6 Port A Pin Functions (Modes 4 to 6) Mode 7: In mode 7, port A pins function as I/O ports and SCI2 I/O pins (SCK2, TxD2, RxD2). Input or output can be specified for each pin on an individual bit basis. Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the pin an input port. Port A pin functions are shown in figure 9-7. Rev. 6.00 Feb 22, 2005 page 258 of 1484 REJ09B0103-0600 Section 9 I/O Ports PA3 (I/O) / SCK2 (I/O) Port A PA2 (I/O) / RxD2 (input) PA1 (I/O) / TxD2 (output) PA0 (I/O) Figure 9-7 Port A Pin Functions (Mode 7) 9.6.5 MOS Input Pull-Up Function Port A has an on-chip MOS input pull-up function that can be controlled by software. MOS input pull-up can be specified as on or off on an individual bit basis. In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the SCI's SCMR, SMR, and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin. In mode 7, if a pin is in the input state in accordance with the settings in the SCI's SCMR, SMR, and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode. The prior state is retained in software standby mode. Table 9-10summarizes the MOS input pull-up states. Table 9-10 MOS Input Pull-Up States (Port A) Pin States Address output or SCI output Other than above Reset OFF Hardware Standby Mode OFF Software Standby Mode OFF ON/OFF In Other Operations OFF ON/OFF Legend: OFF: MOS input pull-up is always off. ON/OFF: On when PADDR = 0 and PAPCR = 1; otherwise off. Rev. 6.00 Feb 22, 2005 page 259 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.7 9.7.1 Port B Overview Port B is an 8-bit I/O port. Port B pins also function as TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, TIOCB5) and as address outputs; the pin functions change according to the operating mode. Port B has an on-chip MOS input pull-up function that can be controlled by software. Figure 9-8 shows the port B pin configuration. Port B pins PB7 / A15/TIOCB5 PB6 / A14/TIOCA5 PB5 / A13/TIOCB4 PB4 / A12/TIOCA4 Port B PB3 / A11/TIOCD3 PB2 / A10/TIOCC3 PB1 / A9 /TIODB3 PB0 / A8 /TIOCA3 Pin functions in modes 4 to 6 PB7 (input) / A15 (output) / TIOCB5 (I/O) PB6 (input) / A14 (output) / TIOCA5 (I/O) PB5 (input) / A13 (output) / TIOCB4 (I/O) PB4 (input) / A12 (output) / TIOCA4 (I/O) PB3 (input) / A11 (output) / TIOCD3 (I/O) PB2 (input) / A10 (output) / TIOCC3 (I/O) PB1 (input) / A9 (output) / TIOCB3 (I/O) PB0 (input) / A8 (output) / TIOCA3 (I/O) Pin functions in mode 7 PB7 (I/O) / TIOCB5 (I/O) PB6 (I/O) / TIOCA5 (I/O) PB5 (I/O) / TIOCB4 (I/O) PB4 (I/O) / TIOCA4 (I/O) PB3 (I/O) / TIOCD3 (I/O) PB2 (I/O) / TIOCC3 (I/O) PB1 (I/O) / TIOCB3 (I/O) PB0 (I/O) / TIOCA3 (I/O) Figure 9-8 Port B Pin Functions Rev. 6.00 Feb 22, 2005 page 260 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.7.2 Register Configuration Table 9-11 shows the port B register configuration. Table 9-11 Port B Registers Name Port B data direction register Port B data register Port B register Port B MOS pull-up control register Port B open-drain control register Note: * Lower 16 bits of the address. Abbreviation PBDDR PBDR PORTB PBPCR PBODR R/W W R/W R R/W R/W Initial Value H'00 H'00 Undefined H'00 H'00 Address* H'FE3A H'FF0A H'FFBA H'FF41 H'FE48 Port B Data Direction Register (PBDDR) Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial value : R/W : PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port B. PBDDR cannot be read; if it is, an undefined value will be read. PBDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 4 to 6 The corresponding port B pins become address outputs in accordance with the setting of bits AE3 to AE0 in PFCR, irrespective of the value of the PBDDR bits. When pins are not used as address outputs, setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin an input port. * Mode 7 Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin an input port. Rev. 6.00 Feb 22, 2005 page 261 of 1484 REJ09B0103-0600 Section 9 I/O Ports Port B Data Register (PBDR) Bit : 7 PB7DR Initial value : R/W : 0 R/W 6 PB6DR 0 R/W 5 PB5DR 0 R/W 4 PB4DR 0 R/W 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W 0 PB0DR 0 R/W PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to PB0). PBDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port B Register (PORTB) Bit : 7 PB7 --* R 6 PB6 --* R 5 PB5 --* R 4 PB4 --* R 3 PB3 --* R 2 PB2 --* R 1 PB1 --* R 0 PB0 --* R Initial value : R/W : Note: * Determined by state of pins PB7 to PB0. PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port B pins (PB7 to PB0) must always be performed on PBDR. If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B read is performed while PBDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTB contents are determined by the pin states, as PBDDR and PBDR are initialized. PORTB retains its prior state in software standby mode. Rev. 6.00 Feb 22, 2005 page 262 of 1484 REJ09B0103-0600 Section 9 I/O Ports Port B MOS Pull-Up Control Register (PBPCR) Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : R/W : PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port B on an individual bit basis. In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the TPU's TIOR, and in DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin. In mode 7, if a pin is in the input state in accordance with the settings in the TPU's TIOR and in DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin. PBPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port B Open Drain Control Register (PBODR) Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR Initial value : R/W : PBODR is an 8-bit readable/writable register that controls the PMOS on/off state for each port B pin (PB7 to PB0). When pins are not address outputs in accordance with the setting of bits AE3 to AE0 in PFCR, setting a PBODR bit makes the corresponding port B pin an NMOS open-drain output, while clearing the bit to 0 makes the pin a CMOS output. PBODR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Rev. 6.00 Feb 22, 2005 page 263 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.7.3 Pin Functions Modes 4 to 6: In modes 4 to 6, the corresponding port B pins become address outputs in accordance with the setting of bits AE3 to AE0 in PFCR. When pins are not used as address outputs, they function as TPU I/O pins and I/O ports. Port B pin functions in modes 4 to 6 are shown in figure 9-9. PB7 (I/O) / A15 (output) / TIOCB5 (I/O) PB6 (I/O) / A14 (output) / TIOCA5 (I/O) PB5 (I/O) / A13 (output) / TIOCB4 (I/O) Port B PB4 (I/O) / A12 (output) / TIOCA4 (I/O) PB3 (I/O) / A11 (output) / TIOCD3 (I/O) PB2 (I/O) / A10 (output) / TIOCC3 (I/O) PB1 (I/O) / A9 (output) / TIOCB3 (I/O) PB0 (I/O) / A8 (output) / TIOCA3 (I/O) Figure 9-9 Port B Pin Functions (Modes 4 to 6) Mode 7: In mode 7, port B pins function as I/O ports and TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5). Input or output can be specified for each pin on an individual bit basis. Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin an input port. Port B pin functions in mode 7 are shown in figure 9-10. PB7 (I/O) / TIOCB5 (I/O) PB6 (I/O) / TIOCA5 (I/O) PB5 (I/O) / TIOCB4 (I/O) Port B PB4 (I/O) / TIOCA4 (I/O) PB3 (I/O) / TIOCD3 (I/O) PB2 (I/O) / TIOCC3 (I/O) PB1 (I/O) / TIOCB3 (I/O) PB0 (I/O) / TIOCA3 (I/O) Figure 9-10 Port B Pin Functions (Mode 7) Rev. 6.00 Feb 22, 2005 page 264 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.7.4 MOS Input Pull-Up Function Port B has an on-chip MOS input pull-up function that can be controlled by software. MOS input pull-up can be specified as on or off on an individual bit basis. In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the TPU's TIOR, and in DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin. In mode 7, if a pin is in the input state in accordance with the settings in the TPU's TIOR and in DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode. The prior state is retained by a manual reset or in software standby mode. Table 9-12 summarizes the MOS input pull-up states. Table 9-12 MOS Input Pull-Up States (Port B) Pin States Address output or TPU output Other than above Reset OFF Hardware Standby Mode OFF Software Standby Mode OFF ON/OFF In Other Operations OFF ON/OFF Legend: OFF: MOS input pull-up is always off. ON/OFF: On when PBDDR = 0 and PBPCR = 1; otherwise off. Rev. 6.00 Feb 22, 2005 page 265 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.8 9.8.1 Port C Overview Port C is an 8-bit I/O port. Port C has an address bus output function. The pin functions change according to the operating mode. Port C has an on-chip MOS input pull-up function that can be controlled by software. Figure 9-11 shows the port C pin configuration. Pin functions in modes 4 and 5 A7 (output) A6 (output) A5 (output) A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) Port C pins PC7/A7 PC6/A6 PC5/A5 Port C PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 Pin functions in mode 6 PCDDR = 1 A7 (output) A6 (output) A5 (output) A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) PCDDR = 0 PC7 (input) PC6 (input) PC5 (input) PC4 (input) PC3 (input) PC2 (input) PC1 (input) PC0 (input) Pin functions in mode 7 PC7 (I/O) PC6 (I/O) PC5 (I/O) PC4 (I/O) PC3 (I/O) PC2 (I/O) PC1 (I/O) PC0 (I/O) Figure 9-11 Port C Pin Functions Rev. 6.00 Feb 22, 2005 page 266 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.8.2 Register Configuration Table 9-13 shows the port C register configuration. Table 9-13 Port C Registers Name Port C data direction register Port C data register Port C register Port C MOS pull-up control register Port C open-drain control register Note: * Lower 16 bits of the address. Abbreviation PCDDR PCDR PORTC PCPCR PCODR R/W W R/W R R/W R/W Initial Value H'00 H'00 Undefined H'00 H'00 Address* H'FE3B H'FF0B H'FFBB H'FF42 H'FE49 Port C Data Direction Register (PCDDR) Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Initial value : R/W : PCDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port C. PCDDR cannot be read; if it is, an undefined value will be read. PCDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when the mode is changed to software standby mode. * Modes 4 and 5 The corresponding port C pins are address outputs irrespective of the value of the PCDDR bits. * Mode 6 Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while clearing the bit to 0 makes the pin an input port. * Mode 7 Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing the bit to 0 makes the pin an input port. Rev. 6.00 Feb 22, 2005 page 267 of 1484 REJ09B0103-0600 Section 9 I/O Ports Port C Data Register (PCDR) Bit : 7 PC7DR Initial value : R/W : 0 R/W 6 PC6DR 0 R/W 5 PC5DR 0 R/W 4 PC4DR 0 R/W 3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W 0 PC0DR 0 R/W PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to PC0). PCDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port C Register (PORTC) Bit : 7 PC7 --* R 6 PC6 --* R 5 PC5 --* R 4 PC4 --* R 3 PC3 --* R 2 PC2 --* R 1 PC1 --* R 0 PC0 --* R Initial value : R/W : Note: * Determined by state of pins PC7 to PC0. PORTC is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port C pins (PC7 to PC0) must always be performed on PCDR. If a port C read is performed while PCDDR bits are set to 1, the PCDR values are read. If a port C read is performed while PCDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTC contents are determined by the pin states, as PCDDR and PCDR are initialized. PORTC retains its prior state in software standby mode. Rev. 6.00 Feb 22, 2005 page 268 of 1484 REJ09B0103-0600 Section 9 I/O Ports Port C MOS Pull-Up Control Register (PCPCR) Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : R/W : PCPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port C on an individual bit basis. In modes 6 and 7, if PCPCR is set to 1 when the port is in the input state in accordance with the settings of PCDDR, the MOS input pull-up is set to ON. PCPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state by a manual reset or in software standby mode. Port C Open Drain Control Register (PCODR) Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR PCDDR is an 8-bit Read/Write register and controls PMOS On/Off of each pin (PC7 to PC0) of port C. If PCODR is set to 1 by setting AE3 to AE0 in PFCR in mode other than address output mode, port C pins function as NMOS open drain outputs and when the setting is cleared to 0, the pins function as CMOS outputs. PCODR is initialized to H'00 in reset mode or hardware standby mode. PCODR retains the last state in software standby mode. Rev. 6.00 Feb 22, 2005 page 269 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.8.3 Pin Functions for Each Mode Modes 4 and 5: In modes 4 and 5, port C pins function as address outputs automatically. Figure 9-12 shows the port C pin functions. A7 (output) A6 (output) A5 (output) Port C A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) Figure 9-12 Port C Pin Functions (Modes 4 and 5) Mode 6: In mode 6, port C pints function as address outputs or input ports and I/O can be specified in bit units. When each bit in PCDDR is set to 1, the corresponding pin functions as an address output and when the bit cleared to 0, the pin functions as an input port. Figure 9-13 shows the port C pin functions. PCDDR = 1 A7 (output) A6 (output) A5 (output) Port C A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) PCDDR = 0 PC7 (input) PC6 (input) PC5 (input) PC4 (input) PC3 (input) PC2 (input) PC1 (input) PC0 (input) Figure 9-13 Port C Pin Functions (Mode 6) Rev. 6.00 Feb 22, 2005 page 270 of 1484 REJ09B0103-0600 Section 9 I/O Ports Mode 7: In mode 7, port C pins function as I/O ports and I/O can be specified for each pin in bit units. When each bit in PCDDR is set to 1, the corresponding pin functions as an output port and when the bit is cleared to 0, the pin functions as an input port. Figure 9-14 shows the port C pin functions. PC7 (I/O) PC6 (I/O) PC5 (I/O) Port C PC4 (I/O) PC3 (I/O) PC2 (I/O) PC1 (I/O) PC0 (I/O) Figure 9-14 Port C Pin Functions (Mode 7) Rev. 6.00 Feb 22, 2005 page 271 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.8.4 MOS Input Pull-Up Function Port C has an on-chip MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an individual bit basis. In modes 6 and 7, when PCPCR is set to 1 in the input state by setting of PCDDR, the MOS input pull-up is set to ON. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode. The prior state is retained by a manual reset or in software standby mode. Table 9-14 summarizes the MOS input pull-up states. Table 9-14 MOS Input Pull-Up States (Port C) Pin States Address output Other than above Reset OFF Hardware Standby Mode OFF Software Standby Mode OFF ON/OFF In Other Operations OFF ON/OFF Legend: OFF: MOS input pull-up is always off. ON/OFF: On when PCDDR = 0 and PCPCR = 1; otherwise off. Rev. 6.00 Feb 22, 2005 page 272 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.9 9.9.1 Port D Overview Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change according to the operating mode. Port D has an on-chip MOS input pull-up function that can be controlled by software. Figure 9-15 shows the port D pin configuration. Port D pins PD7/D15 PD6/D14 PD5/D13 Port D PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8 Pin functions in modes 4 to 6 D15 (I/O) D14 (I/O) D13 (I/O) D12 (I/O) D11 (I/O) D10 (I/O) D9 D8 (I/O) (I/O) Pin functions in mode 7 PD7 (I/O) PD6 (I/O) PD5 (I/O) PD4 (I/O) PD3 (I/O) PD2 (I/O) PD1 (I/O) PD0 (I/O) Figure 9-15 Port D Pin Functions Rev. 6.00 Feb 22, 2005 page 273 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.9.2 Register Configuration Table 9-15 shows the port D register configuration. Table 9-15 Port D Registers Name Port D data direction register Port D data register Port D register Port D MOS pull-up control register Note: * Lower 16 bits of the address. Abbreviation PDDDR PDDR PORTD PDPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address* H'FE3C H'FF0C H'FFBC H'FE43 Port D Data Direction Register (PDDDR) Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : R/W : PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port D. PDDDR cannot be read; if it is, an undefined value will be read. PDDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. * Modes 4 to 6 The input/output direction specification by PDDDR is ignored, and port D is automatically designated for data I/O. * Mode 7 Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin an input port. Rev. 6.00 Feb 22, 2005 page 274 of 1484 REJ09B0103-0600 Section 9 I/O Ports Port D Data Register (PDDR) Bit : 7 PD7DR Initial value : R/W : 0 R/W 6 PD6DR 0 R/W 5 PD5DR 0 R/W 4 PD4DR 0 R/W 3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W 0 PD0DR 0 R/W PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to PD0). PDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port D Register (PORTD) Bit : 7 PD7 --* R 6 PD6 --* R 5 PD5 --* R 4 PD4 --* R 3 PD3 --* R 2 PD2 --* R 1 PD1 --* R 0 PD0 --* R Initial value : R/W : Note: * Determined by state of pins PD7 to PD0. PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port D pins (PD7 to PD0) must always be performed on PDDR. If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D read is performed while PDDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTD contents are determined by the pin states, as PDDDR and PDDR are initialized. PORTD retains its prior state in software standby mode. Rev. 6.00 Feb 22, 2005 page 275 of 1484 REJ09B0103-0600 Section 9 I/O Ports Port D MOS Pull-Up Control Register (PDPCR) Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : R/W : PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port D on an individual bit basis. When a PDDDR bit is cleared to 0 (input port setting) in mode 7, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PDPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. 9.9.3 Pin Functions Modes 4 to 6: In modes 4 to 6, port D pins are automatically designated as data I/O pins. Port D pin functions in modes 4 to 6 are shown in figure 9-16. D15 (I/O) D14 (I/O) D13 (I/O) Port D D12 (I/O) D11 (I/O) D10 (I/O) D9 D8 (I/O) (I/O) Figure 9-16 Port D Pin Functions (Modes 4 to 6) Mode 7: In mode 7, port D pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin an input port. Rev. 6.00 Feb 22, 2005 page 276 of 1484 REJ09B0103-0600 Section 9 I/O Ports Port D pin functions in mode 7 are shown in figure 9-17. PD7 (I/O) PD6 (I/O) PD5 (I/O) Port D PD4 (I/O) PD3 (I/O) PD2 (I/O) PD1 (I/O) PD0 (I/O) Figure 9-17 Port D Pin Functions (Mode 7) 9.9.4 MOS Input Pull-Up Function Port D has an on-chip MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in mode 7, and can be specified as on or off on an individual bit basis. When a PDDDR bit is cleared to 0 in mode 7, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode. The prior state is retained in software standby mode. Table 9-16 summarizes the MOS input pull-up states. Table 9-16 MOS Input Pull-Up States (Port D) Modes 4 to 6 7 Reset OFF Hardware Standby Mode OFF Software Standby Mode OFF ON/OFF In Other Operations OFF ON/OFF Legend: OFF: MOS input pull-up is always off. ON/OFF: On when PDDDR = 0 and PDPCR = 1; otherwise off. Rev. 6.00 Feb 22, 2005 page 277 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.10 9.10.1 Port E Overview Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. Port E has an on-chip MOS input pull-up function that can be controlled by software. Figure 9-18 shows the port E pin configuration. Port E pins PE7/D7 PE6/D6 PE5/D5 Port E PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 Pin functions in modes 4 to 6 PE7 (I/O) / D7 (I/O) PE6 (I/O) / D6 (I/O) PE5 (I/O) / D5 (I/O) PE4 (I/O) / D4 (I/O) PE3 (I/O) / D3 (I/O) PE2 (I/O) / D2 (I/O) PE1 (I/O) / D1 (I/O) PE0 (I/O) / D0 (I/O) Pin functions in mode 7 PE7 (I/O) PE6 (I/O) PE5 (I/O) PE4 (I/O) PE3 (I/O) PE2 (I/O) PE1 (I/O) PE0 (I/O) Figure 9-18 Port E Pin Functions Rev. 6.00 Feb 22, 2005 page 278 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.10.2 Register Configuration Table 9-17 shows the port E register configuration. Table 9-17 Port E Registers Name Port E data direction register Port E data register Port E register Port E MOS pull-up control register Note: * Lower 16 bits of the address. Abbreviation PEDDR PEDR PORTE PEPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address* H'FE3D H'FF0D H'FFBD H'FE44 Port E Data Direction Register (PEDDR) Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : R/W : PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port E. PEDDR cannot be read; if it is, an undefined value will be read. PEDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state by a manual reset or in software standby mode. * Modes 4 to 6 When 8-bit bus mode has been selected, port E pins function as I/O ports. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. When 16-bit bus mode has been selected, the input/output direction specification by PEDDR is ignored, and port E is designated for data I/O. For details of 8-bit and 16-bit bus modes, see section 7, Bus Controller. * Mode 7 Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. Rev. 6.00 Feb 22, 2005 page 279 of 1484 REJ09B0103-0600 Section 9 I/O Ports Port E Data Register (PEDR) Bit : 7 PE7DR Initial value : R/W : 0 R/W 6 PE6DR 0 R/W 5 PE5DR 0 R/W 4 PE4DR 0 R/W 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W 0 PE0DR 0 R/W PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to PE0). PEDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port E Register (PORTE) Bit : 7 PE7 --* R 6 PE6 --* R 5 PE5 --* R 4 PE4 --* R 3 PE3 --* R 2 PE2 --* R 1 PE1 --* R 0 PE0 --* R Initial value : R/W : Note: * Determined by state of pins PE7 to PE0. PORTE is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port E pins (PE7 to PE0) must always be performed on PEDR. If a port E read is performed while PEDDR bits are set to 1, the PEDR values are read. If a port E read is performed while PEDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTE contents are determined by the pin states, as PEDDR and PEDR are initialized. PORTE retains its prior state in software standby mode. Rev. 6.00 Feb 22, 2005 page 280 of 1484 REJ09B0103-0600 Section 9 I/O Ports Port E MOS Pull-Up Control Register (PEPCR) Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : R/W : PEPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port E on an individual bit basis. When a PEDDR bit is cleared to 0 (input port setting) with 8-bit bus mode selected in mode 4, 5, or 6, or in mode 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PEPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. 9.10.3 Pin Functions Modes 4 to 6: In modes 4 to 6, when 8-bit access is designated and 8-bit bus mode is selected, port E pins are automatically designated as I/O ports. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. When 16-bit bus mode is selected, the input/output direction specification by PEDDR is ignored, and port E is designated for data I/O. Port E pin functions in modes 4 to 6 are shown in figure 9-19. Rev. 6.00 Feb 22, 2005 page 281 of 1484 REJ09B0103-0600 Section 9 I/O Ports 8-bit bus mode PE7 (I/O) PE6 (I/O) PE5 (I/O) Port E PE4 (I/O) PE3 (I/O) PE2 (I/O) PE1 (I/O) PE0 (I/O) 16-bit bus mode D7 (I/O) D6 (I/O) D5 (I/O) D4 (I/O) D3 (I/O) D2 (I/O) D1 (I/O) D0 (I/O) Figure 9-19 Port E Pin Functions (Modes 4 to 6) Mode 7: In mode 7, port E pins function as I/O ports. Input or output can be specified for each pin on a bit-by-bit basis. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. Port E pin functions in mode 7 are shown in figure 9-20. PE7 (I/O) PE6 (I/O) PE5 (I/O) Port E PE4 (I/O) PE3 (I/O) PE2 (I/O) PE1 (I/O) PE0 (I/O) Figure 9-20 Port E Pin Functions (Mode 7) Rev. 6.00 Feb 22, 2005 page 282 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.10.4 MOS Input Pull-Up Function Port E has an on-chip MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 4 to 6 when 8-bit bus mode is selected, or in mode 7, and can be specified as on or off on an individual bit basis. When a PEDDR bit is cleared to 0 in modes 4 to 6 when 8-bit bus mode is selected, or in mode 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode. The prior state is retained in software standby mode. Table 9-18 summarizes the MOS input pull-up states. Table 9-18 MOS Input Pull-Up States (Port E) Modes 7 4 to 6 8-bit bus 16-bit bus OFF OFF Reset OFF Hardware Standby Mode OFF Software Standby Mode ON/OFF In Other Operations ON/OFF Legend: OFF: MOS input pull-up is always off. ON/OFF: On when PEDDR = 0 and PEPCR = 1; otherwise off. Rev. 6.00 Feb 22, 2005 page 283 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.11 9.11.1 Port F Overview Port F is a 6-bit I/O port. Port F pins also function as external interrupt input pins (IRQ2 and ), A/D trigger input pin (ADTRG), bus control signal input/output pins (AS, , , and ), and the system clock () output pin. Figure 9-21 shows the port F pin configuration. Port F pins Pin functions in modes 4 to 6 RWH DR 3QRI RWL PF7 / PF6 / AS/LCAS Port F PF5 / RD PF4 / HWR PF3 / LWR/ADTRG/IRQ3 PF0 / IRQ2 PF7 (input) / (output) AS (output) RD (output) HWR (output) PF3 (I/O) / LWR (output) / ADTRG (input) / IRQ3 (input) PF0 (I/O) / IRQ2 (input) Pin functions in mode 7 PF7 (input) / (output) PF6 (I/O) PF5 (I/O) PF4 (I/O) PF3 (I/O) / ADTRG (input) / IRQ3 (input) PF0 (I/O) / IRQ2 (input) Figure 9-21 Port F Pin Functions Rev. 6.00 Feb 22, 2005 page 284 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.11.2 Register Configuration Table 9-19 shows the port F register configuration. Table 9-19 Port F Registers Name Port F data direction register Port F data register Port F register Abbreviation R/W PFDDR PFDR PORTF W R/W R Initial Value B'10000**0*2/ B'00000**0*2 B'00000**0 Undefined Address*1 H'FE3E H'FF0E H'FFBE Notes: 1. Lower 16 bits of the address. 2. Initial value depends on the mode. Port F Data Direction Register (PFDDR) Bit Modes 4 to 6 Initial value : R/W Mode 7 Initial value : R/W : 0 W 0 W 0 W 0 W 0 W undefined undefined : 7 6 5 4 3 2 -- 1 -- 0 PF0DDR 0 W 0 W PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR 1 W 0 W 0 W 0 W 0 W undefined undefined : -- -- -- -- PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port F. PFDDR cannot be read; if it is, an undefined value will be read. PFDDR is initialized by a reset, and in hardware standby mode, to B'10000**0 in modes 4 to 6, and to B'00000**0 in mode 7. It retains its prior state in software standby mode. The OPE bit in SBYCR is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 4 to 6 Pin PF7 functions as the output pin when the corresponding PFDDR bit is set to 1, and as an input port when the bit is cleared to 0. The input/output direction specified by PFDDR is ignored for pins PF6 to PF3, which are automatically designated as bus control outputs (AS, , , and ) (in the 8-bit mode, pin PF3 is designated by PFDDR). Rev. 6.00 Feb 22, 2005 page 285 of 1484 REJ09B0103-0600 RWL RWH DR Section 9 I/O Ports Pin PF0 is setting a PFDDR bit to 1 makes the corresponding port F pin an output port, while clearing the bit to 0 makes the pin an input port. * Mode 7 Setting a PFDDR bit to 1 makes the corresponding port F pin PF6 to PF3, PF0 an output port, or in the case of pin PF7, the output pin. Clearing the bit to 0 makes the pin an input port. Port F Data Register (PFDR) Bit : 7 PF7DR Initial value : R/W : 0 R/W 6 PF6DR 0 R/W 5 PF5DR 0 R/W 4 PF4DR 0 R/W 3 PF3DR 0 R/W 2 -- -- 1 -- -- 0 PF0DR 0 R/W undefined undefined PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF3, PF0). PFDR is initialized to B'00000**0 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port F Register (PORTF) Bit : 7 PF7 --* R 6 PF6 --* R 5 PF5 --* R 4 PF4 --* R 3 PF3 --* R 2 -- -- 1 -- -- 0 PF0 --* R Initial value : R/W : undefined undefined Note: * Determined by state of pins PF7 to PF3, PF0. PORTF is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port F pins (PF7 to PF3, PF0) must always be performed on PFDR. If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F read is performed while PFDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTF contents are determined by the pin states, as PFDDR and PFDR are initialized. PORTF retains its prior state in software standby mode. Rev. 6.00 Feb 22, 2005 page 286 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.11.3 Pin Functions Port F pins also function as external interrupt input pins (IRQ2 and IRQ3), A/D trigger input pin (ADTRG), bus control signal input/output pins (AS, , , ), and the system clock () output pin. The pin functions differ between modes 4 to 6, and mode 7. Port F pin functions are shown in table 9-20. Table 9-20 Port F Pin Functions Pin PF7/ Selection Method and Pin Functions The pin function is switched as shown below according to bit PF7DDR. PF7DDR Pin function PF6/AS 0 PF7 input 1 output RWL RWH DR The pin function is switched as shown below according to bit PF6DDR. Operating Mode PF6DDR SA Modes 4 to 6 -- output 0 Mode 7 1 PF6 output Pin function PF5/RD PF6 input The pin function is switched as shown below according to the operating mode and bit PF5DDR. Operating Mode PF5DDR DR Modes 4 to 6 -- output 0 PF5 input Mode 7 1 PF5 output Pin function PF4/HWR The pin function is switched as shown below according to the operating mode and bit PF4DDR. Operating Mode PF4DDR Pin function Modes 4 to 6 -- output RWH Mode 7 0 PF4 input 1 PF4 output Rev. 6.00 Feb 22, 2005 page 287 of 1484 REJ09B0103-0600 Section 9 I/O Ports Pin PF3/LWR/ / Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, the bus mode, A/D converter bits TRGS1 and TRGS0, and bit PF3DDR. Operating mode Bus mode PF3DDR Pin function 16-bit bus mode -- RWL Notes: 1. input when TRGS0 = TRGS1 = 1. 2. When used as an external interrupt input pin, do not use as an I/O pin for another function. PF0/IRQ2 The pin function is switched as shown below according to the bit PF0DDR. PF0DDR Pin function 0 PF0 input input 2QRI GRTDA Rev. 6.00 Feb 22, 2005 page 288 of 1484 REJ09B0103-0600 GRTDA 3QRI 3QRI GRTDA Modes 4 to 6 8-bit bus mode 0 1 0 Mode 7 -- 1 output PF3 input PF3 output PF3 input PF3 output pin pin pin pin pin *1 input pin input pin*2 1 PF0 output Section 9 I/O Ports 9.12 9.12.1 Port H Overview Port H is an 8-bit I/O port. Port H pins also function as motor control PWM timer output pins (PWM1A to PWM1H). Figure 9-22 shows the port H pin configuration. Port H pin PH7 / PWM1H PH6 / PWM1G PH5 / PWM1F Port H PH4 / PWM1E PH3 / PWM1D PH2 / PWM1C PH1 / PWM1B PH0 / PWM1A Figure 9-22 Port H Pin Functions Rev. 6.00 Feb 22, 2005 page 289 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.12.2 Register Configuration Table 9-21 shows the port H register configuration. Table 9-21 Port H Registers Name Port H data direction register Port H data register Port H register Note: * Lower 16 bits of the address. Abbreviation PHDDR PHDR PORTH R/W W RW R Initial Value H'00 H'00 Undefined Address* H'FC20 H'FC24 H'FC28 Port H Data Direction Register (PHDDR) Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PH7DDR PH6DDR PH5DDR PH4DDR PH3DDR PH2DDR PH1DDR PH0DDR Initial value : R/W : PHDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port H. PHDDR cannot be read. If it is, an undefined value will be read. PHDDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Port H Data Register (PHDR) Bit : 7 PH7DR Initial value : R/W : 0 R/W 6 PH6DR 0 R/W 5 PH5DR 0 R/W 4 PH4DR 0 R/W 3 PH3DR 0 R/W 2 PH2DR 0 R/W 1 PH1DR 0 R/W 0 PH0DR 0 R/W PHDR is an 8-bit readable/writeable register that stores output data for the port H pins (PH7 to PH0). PHDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Rev. 6.00 Feb 22, 2005 page 290 of 1484 REJ09B0103-0600 Section 9 I/O Ports Port H Register (PORTH) Bit : 7 PH7 --* R 6 PH6 --* R 5 PH5 --* R 4 PH4 --* R 3 PH3 --* R 2 PH2 --* R 1 PH1 --* R 0 PH0 --* R Initial value : R/W : Note: * Determined by the state of PH7 to PH0 PORTH is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port H pins (PH7 to PH0) must always be performed on PHDR. If a port H read is performed while PHDDR bits are set to 1, the PHDR values are read. If a port H read is performed while PHDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTH contents are determined by the pin states, as PHDDR and PHDR are initialized. PORTH retains its prior state in software standby mode. 9.12.3 Pin Functions As shown in table 9-22, the port H pin functions can be switched, bit by bit, by changing the values of OE1A to OE1H of motor control PWM timer PWOCR1 and PHDDR. Table 9-22 Port H Pin Functions 0E1A to 0E1H PHDDR Pin function 1 -- PWM output 0 0 PH7 to PH0 input 1 PH7 to PH0 output Rev. 6.00 Feb 22, 2005 page 291 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.13 9.13.1 Port J Overview Port J is an 8-bit I/O port. Port J pins also function as motor control PWM timer output pins (PWM2A to PWM2H). Figure 9-23 shows the port J pin configuration. Port J pin PJ7 / PWM2H PJ6 / PWM2G PJ5 / PWM2F Port J PJ4 / PWM2E PJ3 / PWM2D PJ2 / PWM2C PJ1 / PWM2B PJ0 / PWM2A Figure 9-23 Port J Pin Functions Rev. 6.00 Feb 22, 2005 page 292 of 1484 REJ09B0103-0600 Section 9 I/O Ports 9.13.2 Register Configuration Table 9-23 shows the port J register configuration. Table 9-23 Port J Registers Name Port J data direction register Port J data register Port J register Note: * Lower 16 bits of the address Abbreviation PJDDR PJDR PORTJ R/W W RW R Initial Value H'00 H'00 Undefined Address* H'FC21 H'FC25 H'FC29 Port J Data Direction Register (PJDDR) Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PJ7DDR PJ6DDR PJ5DDR PJ4DDR PJ3DDR PJ2DDR PJ1DDR PJ0DDR Initial value : R/W : PJDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port J. PJDDR cannot be read. If it is, an undefined value will be read. PJDDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Port J Data Register (PJDR) Bit : 7 PJ7DR Initial value : R/W : 0 R/W 6 PJ6DR 0 R/W 5 PJ5DR 0 R/W 4 PJ4DR 0 R/W 3 PJ3DR 0 R/W 2 PJ2DR 0 R/W 1 PJ1DR 0 R/W 0 PJ0DR 0 R/W PJDR is an 8-bit readable/writeable register that stores output data for the port J pins (PJ7 to PJ0). PJDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Rev. 6.00 Feb 22, 2005 page 293 of 1484 REJ09B0103-0600 Section 9 I/O Ports Port J Register (PORTJ) Bit : 7 PJ7 --* R 6 PJ6 --* R 5 PJ5 --* R 4 PJ4 --* R 3 PJ3 --* R 2 PJ2 --* R 1 PJ1 --* R 0 PJ0 --* R Initial value : R/W : PORTJ is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port J pins (PJ7 to PJ0) must always be performed on PJDR. If a port J read is performed while PJDDR bits are set to 1, the PJDR values are read. If a port J read is performed while PJDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTJ contents are determined by the pin states, as PJDDR and PJDR are initialized. PORTJ retains its prior state in software standby mode. 9.13.3 Pin Functions As shown in table 9-24, the port J pin functions can be switched, bit by bit, by changing the values of OE2A to OE2H of motor control PWM timer PWOCR2 and PJDDR. Table 9-24 Port J Pin Functions OE2A to OE2H PJDDR Pin function 1 -- PWM output 0 0 PJ7 to PJ0 input 1 PJ7 to PJ0 output Rev. 6.00 Feb 22, 2005 page 294 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Section 10 16-Bit Timer Pulse Unit (TPU) Note: The H8S/2635 Group is not equipped with a DTC or a PPG. 10.1 Overview The chip has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. 10.1.1 Features * Maximum 16-pulse input/output A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5), each of which can be set independently as an output compare/input capture register TGRC and TGRD for channels 0 and 3 can also be used as buffer registers * Selection of 8 counter input clocks for each channel * The following operations can be set for each channel: Waveform output at compare match: Selection of 0, 1, or toggle output Input capture function: Selection of rising edge, falling edge, or both edge detection Counter clear operation: Counter clearing possible by compare match or input capture Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture possible Register simultaneous input/output possible by counter synchronous operation PWM mode: Any PWM output duty can be set Maximum of 15-phase PWM output possible by combination with synchronous operation * Buffer operation settable for channels 0 and 3 Input capture register double-buffering possible Automatic rewriting of output compare register possible * Phase counting mode settable independently for each of channels 1, 2, 4, and 5 Two-phase encoder pulse up/down-count possible * Cascaded operation Channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel 4) overflow/underflow * Fast access via internal 16-bit bus Fast access is possible via a 16-bit bus interface Rev. 6.00 Feb 22, 2005 page 295 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) * 26 interrupt sources For channels 0 and 3, four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently For channels 1, 2, 4, and 5, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently * Automatic transfer of register data Block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer controller (DTC) * Programmable pulse generator (PPG) output trigger can be generated Channel 0 to 3 compare match/input capture signals can be used as PPG output trigger * A/D converter conversion start trigger can be generated Channel 0 to 5 compare match A/input capture A signals can be used as A/D converter conversion start trigger * Module stop mode can be set As the initial setting, TPU operation is halted. Register access is enabled by exiting module stop mode. Table 10-1 lists the functions of the TPU. Rev. 6.00 Feb 22, 2005 page 296 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10-1 TPU Functions Item Count clock Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 /1 /4 /16 /64 TCLKA TCLKB TCLKC TCLKD TGR0A TGR0B TGR0C TGR0D TIOCA0 TIOCB0 TIOCC0 TIOCD0 TGR compare match or input capture /1 /4 /16 /64 /256 TCLKA TCLKB TGR1A TGR1B -- TIOCA1 TIOCB1 /1 /4 /16 /64 /1024 TCLKA TCLKB TCLKC TGR2A TGR2B -- TIOCA2 TIOCB2 /1 /4 /16 /64 /256 /1024 /4096 TCLKA TGR3A TGR3B TGR3C TGR3D TIOCA3 TIOCB3 TIOCC3 TIOCD3 TGR compare match or input capture /1 /4 /16 /64 /1024 TCLKA TCLKC TGR4A TGR4B -- TIOCA4 TIOCB4 /1 /4 /16 /64 /256 TCLKA TCLKC TCLKD TGR5A TGR5B -- TIOCA5 TIOCB5 General registers General registers/ buffer registers I/O pins Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture Compare 0 output match 1 output output Toggle output Input capture function Synchronous operation PWM mode Phase counting mode Buffer operation -- -- -- -- -- -- Rev. 6.00 Feb 22, 2005 page 297 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Item Channel 0 Channel 1 TGR compare match or input capture TGR1A compare match or input capture TGR1A/ TGR1B compare match or input capture 4 sources Channel 2 TGR compare match or input capture TGR2A compare match or input capture TGR2A/ TGR2B compare match or input capture 4 sources Channel 3 TGR compare match or input capture TGR3A compare match or input capture Channel 4 TGR compare match or input capture TGR4A compare match or input capture Channel 5 TGR compare match or input capture TGR5A compare match or input capture -- DTC TGR activation compare match or input capture A/D TGR0A converter compare trigger match or input capture PPG trigger TGR0A/ TGR0B compare match or input capture 5 sources TGR3A/ -- TGR3B compare match or input capture 5 sources 4 sources Interrupt sources 4 sources * Compare * Compare * Compare * Compare * Compare * Compare match or match or match or match or match or match or input input input input input input capture 0A capture 1A capture 2A capture 3A capture 4A capture 5A * Compare * Compare * Compare * Compare * Compare * Compare match or match or match or match or match or match or input input input input input input capture 0B capture 1B capture 2B capture 3B capture 4B capture 5B * Compare * Overflow match or * Underflow input capture 0C * Compare match or input capture 0D * Overflow * Overflow * Underflow * Compare * Overflow match or * Underflow input capture 3C * Compare match or input capture 3D * Overflow * Overflow * Underflow Legend: : Possible --: Not possible Rev. 6.00 Feb 22, 2005 page 298 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.1.2 Block Diagram Figure 10-1 shows a block diagram of the TPU. TIORH TIORL TMDR Channel 3 TSR TGRC TGRD TGRA TGRB TCNT Control logic for channels 3 to 5 Input/output pins Channel 3: TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 Channel 4: TIOCB4 TIOCA5 Channel 5: TIOCB5 Channel 5 TGRA TIOR TIORH TIORL TMDR Channel 0 TSR Clock input Internal clock: /1 /4 /16 /64 /256 /1024 /4096 External clock: TCLKA TCLKB TCLKC TCLKD TIER TCR Module data bus TSTR TSYR Bus interface TGRB TCNT Interrupt request signals Channel 3: TGI3A TGI3B TGI3C TGI3D TCI3V Channel 4: TGI4A TGI4B TCI4V TCI4U Channel 5: TGI5A TGI5B TCI5V TCI5U TMDR Channel 4 TSR TIER TCR TGRA TIOR TMDR TSR TIER TCR TGRB TCNT Common Control logic Internal data bus A/D converter conversion start signal PPG output trigger signal TGRC TIER TCR TGRD TGRA TGRB TCNT Control logic for channels 0 to 2 TMDR Input/output pins TIOCA0 Channel 0: TIOCB0 TIOCC0 TIOCD0 TIOCA1 Channel 1: TIOCB1 TIOCA2 Channel 2: TIOCB2 Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U TMDR Channel 1 TSR TGRA TGRA TIOR Channel 2 TSR TIER TCR TIOR Legend: TSTR: Timer start register TSYR: Timer synchro register TCR: Timer control register TMDR: Timer mode register TIOR (H, L): TIER: TSR: TGR (A, B, C, D): Timer I/O control registers (H, L) Timer interrupt enable register Timer status register Timer general registers (A, B, C, D) Figure 10-1 Block Diagram of TPU Rev. 6.00 Feb 22, 2005 page 299 of 1484 REJ09B0103-0600 TIER TCR TGRB TCNT TGRB TCNT Section 10 16-Bit Timer Pulse Unit (TPU) 10.1.3 Pin Configuration Table 10-2 summarizes the TPU pins. Table 10-2 TPU Pins Channel All Name Clock input A Symbol TCLKA I/O Input Function External clock A input pin (Channel 1 and 5 phase counting mode A phase input) External clock B input pin (Channel 1 and 5 phase counting mode B phase input) External clock C input pin (Channel 2 and 4 phase counting mode A phase input) External clock D input pin (Channel 2 and 4 phase counting mode B phase input) TGR0A input capture input/output compare output/PWM output pin TGR0B input capture input/output compare output/PWM output pin TGR0C input capture input/output compare output/PWM output pin TGR0D input capture input/output compare output/PWM output pin TGR1A input capture input/output compare output/PWM output pin TGR1B input capture input/output compare output/PWM output pin TGR2A input capture input/output compare output/PWM output pin TGR2B input capture input/output compare output/PWM output pin Clock input B TCLKB Input Clock input C TCLKC Input Clock input D TCLKD Input 0 Input capture/out TIOCA0 compare match A0 Input capture/out TIOCB0 compare match B0 Input capture/out TIOCC0 compare match C0 Input capture/out TIOCD0 compare match D0 I/O I/O I/O I/O I/O I/O I/O I/O 1 Input capture/out TIOCA1 compare match A1 Input capture/out TIOCB1 compare match B1 2 Input capture/out TIOCA2 compare match A2 Input capture/out TIOCB2 compare match B2 Rev. 6.00 Feb 22, 2005 page 300 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Channel 3 Name Symbol I/O I/O I/O I/O I/O I/O I/O I/O I/O Function TGR3A input capture input/output compare output/PWM output pin TGR3B input capture input/output compare output/PWM output pin TGR3C input capture input/output compare output/PWM output pin TGR3D input capture input/output compare output/PWM output pin TGR4A input capture input/output compare output/PWM output pin TGR4B input capture input/output compare output/PWM output pin TGR5A input capture input/output compare output/PWM output pin TGR5B input capture input/output compare output/PWM output pin Input capture/out TIOCA3 compare match A3 Input capture/out TIOCB3 compare match B3 Input capture/out TIOCC3 compare match C3 Input capture/out TIOCD3 compare match D3 4 Input capture/out TIOCA4 compare match A4 Input capture/out TIOCB4 compare match B4 5 Input capture/out TIOCA5 compare match A5 Input capture/out TIOCB5 compare match B5 Rev. 6.00 Feb 22, 2005 page 301 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.1.4 Register Configuration Table 10-3 summarizes the TPU registers. Table 10-3 TPU Registers Channel Name 0 Timer control register 0 Timer mode register 0 Timer I/O control register 0H Timer I/O control register 0L Timer status register 0 Timer counter 0 Timer general register 0A Timer general register 0B Timer general register 0C Timer general register 0D 1 Timer control register 1 Timer mode register 1 Timer I/O control register 1 Timer status register 1 Timer counter 1 Timer general register 1A Timer general register 1B 2 Timer control register 2 Timer mode register 2 Timer I/O control register 2 Timer status register 2 Timer counter 2 Timer general register 2A Timer general register 2B Abbreviation TCR0 TMDR0 TIOR0H TIOR0L TSR0 TCNT0 TGR0A TGR0B TGR0C TGR0D TCR1 TMDR1 TIOR1 TSR1 TCNT1 TGR1A TGR1B TCR2 TMDR2 TIOR2 TSR2 TCNT2 TGR2A TGR2B R/W R/W R/W R/W R/W Initial Value H'00 H'C0 H'00 H'00 Address *1 H'FF10 H'FF11 H'FF12 H'FF13 H'FF14 H'FF15 H'FF16 H'FF18 H'FF1A H'FF1C H'FF1E H'FF20 H'FF21 H'FF22 H'FF24 H'FF25 H'FF26 H'FF28 H'FF2A H'FF30 H'FF31 H'FF32 H'FF34 H'FF35 H'FF36 H'FF38 H'FF3A Timer interrupt enable register 0 TIER0 R/W H'40 R/(W)*2 H'C0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'00 H'C0 H'00 H'40 H'0000 H'FFFF H'FFFF H'00 H'C0 H'00 Timer interrupt enable register 1 TIER1 R/(W) *2 H'C0 Timer interrupt enable register 2 TIER2 H'40 *2 H'C0 R/(W) R/W R/W R/W H'0000 H'FFFF H'FFFF Rev. 6.00 Feb 22, 2005 page 302 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Channel Name 3 Timer control register 3 Timer mode register 3 Timer I/O control register 3H Timer I/O control register 3L Timer status register 3 Timer counter 3 Timer general register 3A Timer general register 3B Timer general register 3C Timer general register 3D 4 Timer control register 4 Timer mode register 4 Timer I/O control register 4 Timer status register 4 Timer counter 4 Timer general register 4A Timer general register 4B 5 Timer control register 5 Timer mode register 5 Timer I/O control register 5 Timer status register 5 Timer counter 5 Timer general register 5A Timer general register 5B All Timer start register Timer synchro register Module stop control register A Abbreviation TCR3 TMDR3 TIOR3H TIOR3L TSR3 TCNT3 TGR3A TGR3B TGR3C TGR3D TCR4 TMDR4 TIOR4 TSR4 TCNT4 TGR4A TGR4B TCR5 TMDR5 TIOR5 TSR5 TCNT5 TGR5A TGR5B TSTR TSYR MSTPCRA R/W R/W R/W R/W R/W R/W Initial Value H'00 H'C0 H'00 H'00 Address*1 H'FE80 H'FE81 H'FE82 H'FE83 H'FE84 H'FE85 H'FE86 H'FE88 H'FE8A H'FE8C H'FE8E H'FE90 H'FE91 H'FE92 H'FE94 H'FE95 H'FE96 H'FE98 H'FE9A H'FEA0 H'FEA1 H'FEA2 H'FEA4 H'FEA5 H'FEA6 H'FEA8 H'FEAA H'FEB0 H'FEB1 H'FDE8 Timer interrupt enable register 3 TIER3 H'40 *2 H'C0 R/(W) R/W R/W R/W R/W R/W R/W R/W R/W R/W H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'00 H'C0 H'00 Timer interrupt enable register 4 TIER4 H'40 *2 H'C0 R/(W) R/W R/W R/W R/W R/W R/W R/W R/(W) R/W R/W R/W R/W R/W R/W *2 H'0000 H'FFFF H'FFFF H'00 H'C0 H'00 H'40 H'C0 H'0000 H'FFFF H'FFFF H'00 H'00 H'3F Timer interrupt enable register 5 TIER5 Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. Rev. 6.00 Feb 22, 2005 page 303 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.2 10.2.1 Register Descriptions Timer Control Register (TCR) Channel 0: TCR0 Channel 3: TCR3 Bit : 7 CCLR2 Initial value : R/W : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W Channel 1: TCR1 Channel 2: TCR2 Channel 4: TCR4 Channel 5: TCR5 Bit : 7 -- Initial value : R/W : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W The TCR registers are 8-bit registers that control the TCNT channels. The TPU has six TCR registers, one for each of channels 0 to 5. The TCR registers are initialized to H'00 by a reset, and in hardware standby mode. TCR register settings should be made only when TCNT operation is stopped. Rev. 6.00 Feb 22, 2005 page 304 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bits 7 to 5--Counter Clear 2, 1, and 0 (CCLR2, CCLR1, CCLR0): These bits select the TCNT counter clearing source. Channel 0, 3 Bit 7 CCLR2 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled (Initial value) TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation *1 TCNT clearing disabled TCNT cleared by TGRC compare match/input capture *2 TCNT cleared by TGRD compare match/input capture *2 TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation *1 1 0 0 1 1 0 1 Channel 1, 2, 4, 5 Bit 7 Bit 6 Reserved*3 CCLR1 0 0 Bit 5 CCLR0 0 1 Description TCNT clearing disabled (Initial value) TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation * 1 0 1 Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. 3. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be modified. Rev. 6.00 Feb 22, 2005 page 305 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bits 4 and 3--Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. /4 both edges = /2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. Bit 4 CKEG1 0 1 Bit 3 CKEG0 0 1 -- Description Count at rising edge Count at falling edge Count at both edges (Initial value) Note: Internal clock edge selection is valid when the input clock is /4 or slower. This setting is ignored if the input clock is /1, or when overflow/underflow of another channel is selected. Bits 2 to 0--Time Prescaler 2, 1, and 0 (TPSC2 to TPSC0): These bits select the TCNT counter clock. The clock source can be selected independently for each channel. Table 10-4 shows the clock sources that can be set for each channel. Table 10-4 TPU Clock Sources Internal Clock Channel /1 /4 /16 /64 Overflow/ Underflow /256 /1024 /4096 TCLKA TCLKB TCLKC TCLKD on Another Channel External Clock 0 1 2 3 4 5 Legend: : Setting Blank: No setting Rev. 6.00 Feb 22, 2005 page 306 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 2 TPSC2 0 Bit 1 TPSC1 0 1 1 0 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Channel 0 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input (Initial value) Channel 1 Bit 2 TPSC2 0 Bit 1 TPSC1 0 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on /256 Counts on TCNT2 overflow/underflow (Initial value) 1 0 1 Note: This setting is ignored when channel 1 is in phase counting mode. Bit 2 TPSC2 0 Bit 1 TPSC1 0 1 1 0 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Channel 2 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on /1024 (Initial value) Note: This setting is ignored when channel 2 is in phase counting mode. Rev. 6.00 Feb 22, 2005 page 307 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 2 TPSC2 0 Bit 1 TPSC1 0 1 1 0 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Channel 3 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input Internal clock: counts on /1024 Internal clock: counts on /256 Internal clock: counts on /4096 (Initial value) Channel 4 Bit 2 TPSC2 0 Bit 1 TPSC1 0 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on /1024 Counts on TCNT5 overflow/underflow (Initial value) 1 0 1 Note: This setting is ignored when channel 4 is in phase counting mode. Bit 2 TPSC2 0 Bit 1 TPSC1 0 1 1 0 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Channel 5 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on /256 External clock: counts on TCLKD pin input (Initial value) Note: This setting is ignored when channel 5 is in phase counting mode. Rev. 6.00 Feb 22, 2005 page 308 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.2.2 Timer Mode Register (TMDR) Channel 0: TMDR0 Channel 3: TMDR3 Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 BFB 0 R/W 4 BFA 0 R/W 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W Channel 1: TMDR1 Channel 2: TMDR2 Channel 4: TMDR4 Channel 5: TMDR5 Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 -- 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode for each channel. The TPU has six TMDR registers, one for each channel. The TMDR registers are initialized to H'C0 by a reset, and in hardware standby mode. TMDR register settings should be made only when TCNT operation is stopped. Bits 7 and 6--Reserved: These bits are always read as 1 and cannot be modified. Bit 5--Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 BFB 0 1 Description TGRB operates normally TGRB and TGRD used together for buffer operation (Initial value) Rev. 6.00 Feb 22, 2005 page 309 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 4--Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. Bit 4 BFA 0 1 Description TGRA operates normally TGRA and TGRC used together for buffer operation (Initial value) Bits 3 to 0--Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode. Bit 3 MD3*1 0 Bit 2 MD2*2 0 Bit 1 MD1 0 1 1 0 1 1 * * Bit 0 MD0 0 1 0 1 0 1 0 1 * Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 -- (Initial value) *: Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. Rev. 6.00 Feb 22, 2005 page 310 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.2.3 Timer I/O Control Register (TIOR) Channel 0: TIOR0H Channel 1: TIOR1 Channel 2: TIOR2 Channel 3: TIOR3H Channel 4: TIOR4 Channel 5: TIOR5 Bit : 7 IOB3 Initial value : R/W : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W Channel 0: TIOR0L Channel 3: TIOR3L Bit : 7 IOD3 Initial value : R/W : 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W 0 IOC0 0 R/W Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. The TIOR registers are 8-bit registers that control the TGR registers. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. The TIOR registers are initialized to H'00 by a reset, and in hardware standby mode. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. Rev. 6.00 Feb 22, 2005 page 311 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bits 7 to 4-- I/O Control B3 to B0 (IOB3 to IOB0) I/O Control D3 to D0 (IOD3 to IOD0): Bits IOB3 to IOB0 specify the function of TGRB. Bits IOD3 to IOD0 specify the function of TGRD. Channel 0 Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 * * * TGR0B is input capture register Capture input source is TIOCB0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 source is channel count-up/count-down*1 1/count clock TGR0B is output compare register Output disabled Initial output is 0 output (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Note: *: Don't care 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and /1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. Rev. 6.00 Feb 22, 2005 page 312 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 7 Bit 6 Bit 5 Bit 4 IOD3 IOD2 IOD1 IOD0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 * 0 1 * * TGR0D Capture input is input source is capture TIOCD0 pin register*2 Capture input source is channel 1/count clock Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT1 count-up/count-down*1 Output disabled TGR0D is output Initial output is 0 compare output 2 register* (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Channel 0 *: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and /1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 6.00 Feb 22, 2005 page 313 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 * * * TGR1B is input capture register Capture input source is TIOCB1 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation source is TGR0C of TGR0C compare match/ compare match/ input capture input capture *: Don't care TGR1B is output compare register Output disabled Initial output is 0 output (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Channel 1 Rev. 6.00 Feb 22, 2005 page 314 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 * 0 1 0 1 * TGR2B is input capture register Capture input source is TIOCB2 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care TGR2B is output compare register Output disabled Initial output is 0 output (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Channel 2 Rev. 6.00 Feb 22, 2005 page 315 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 * 0 1 * * TGR3B is input capture register Capture input source is TIOCB3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT4 1 source is channel count-up/count-down* 4/count clock TGR3B is output compare register Output disabled Initial output is 0 output (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Channel 3 Note: *: Don't care 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and /1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated. Rev. 6.00 Feb 22, 2005 page 316 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 7 Bit 6 Bit 5 Bit 4 IOD3 IOD2 IOD1 IOD0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 * 0 1 * * TGR3D Capture input is input source is capture TIOCD3 pin register*2 Capture input source is channel 4/count clock Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT4 count-up/count-down*1 TGR3D Output disabled is output Initial output is 0 compare output register*2 (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Channel 3 *: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and /1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 6.00 Feb 22, 2005 page 317 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 * 0 1 * * TGR4B is input capture register Capture input source is TIOCB4 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation source is TGR3C of TGR3C compare match/ compare match/ input capture input capture *: Don't care Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 * 0 0 1 1 * TGR5B is input capture register Capture input source is TIOCB5 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care TGR5B is output compare register Output disabled Initial output is 0 output (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match TGR4B is output compare register Output disabled Initial output is 0 output (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Channel 4 Channel 5 Rev. 6.00 Feb 22, 2005 page 318 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bits 3 to 0-- I/O Control A3 to A0 (IOA3 to IOA0) I/O Control C3 to C0 (IOC3 to IOC0): IOA3 to IOA0 specify the function of TGRA. IOC3 to IOC0 specify the function of TGRC. Channel 0 Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 * 0 1 * * TGR0A is input capture register Capture input source is TIOCA0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 source is channel count-up/count-down 1/ count clock *: Don't care TGR0A is output compare register Output disabled Initial output is 0 output (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Rev. 6.00 Feb 22, 2005 page 319 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit 2 Bit 1 Bit 0 IOC3 IOC2 IOC1 IOC0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 * 0 1 * * TGR0C Capture input is input source is TIOCC0 pin capture register*1 Capture input source is channel 1/count clock Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT1 count-up/count-down TGR0C Output disabled is output Initial output is 0 compare output register*1 (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Channel 0 Note: *: Don't care 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 6.00 Feb 22, 2005 page 320 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 * 0 1 * * TGR1A is Capture input input source is TIOCA1 pin capture register Capture input source is TGR0A compare match/ input capture Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at generation of channel 0/TGR0A compare match/input capture *: Don't care Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 * 0 1 0 1 * TGR2A is input capture register Capture input source is TIOCA2 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care TGR2A is output compare register Output disabled Initial output is 0 output (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match TGR1A is output compare register Output disabled Initial output is 0 output (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Channel 1 Channel 2 Rev. 6.00 Feb 22, 2005 page 321 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 * 0 1 * * TGR3A is input capture register Capture input source is TIOCA3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT4 source is channel count-up/count-down 4/count clock *: Don't care TGR3A is output compare register Output disabled Initial output is 0 output (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Channel 3 Rev. 6.00 Feb 22, 2005 page 322 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit 2 Bit 1 Bit 0 IOC3 IOC2 IOC1 IOC0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 * * * TGR3C Capture input is input source is TIOCC3 pin capture register*1 Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR3C Output disabled is output Initial output is 0 compare output register*1 (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Channel 3 Capture input Input capture at TCNT4 source is channel count-up/count-down 4/count clock Note: *: Don't care 1. When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 6.00 Feb 22, 2005 page 323 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 * 0 1 * * TGR4A is input capture register Capture input source is TIOCA4 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation source is TGR3A of TGR3A compare match/ compare match/ input capture input capture *: Don't care Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 * 0 1 0 1 * TGR5A is input capture register Capture input source is TIOCA5 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care TGR5A is output compare register Output disabled Initial output is 0 output (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match TGR4A is output compare register Output disabled Initial output is 0 output (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Channel 4 Channel 5 Rev. 6.00 Feb 22, 2005 page 324 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.2.4 Timer Interrupt Enable Register (TIER) Channel 0: TIER0 Channel 3: TIER3 Bit : 7 TTGE Initial value : R/W : 0 R/W 6 -- 1 -- 5 -- 0 -- 4 TCIEV 0 R/W 3 TGIED 0 R/W 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W Channel 1: TIER1 Channel 2: TIER2 Channel 4: TIER4 Channel 5: TIER5 Bit : 7 TTGE Initial value : R/W : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 -- 0 -- 2 -- 0 -- 1 TGIEB 0 R/W 0 TGIEA 0 R/W The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. The TIER registers are initialized to H'40 by a reset, and in hardware standby mode. Rev. 6.00 Feb 22, 2005 page 325 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 7--A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. Bit 7 TTGE 0 1 Description A/D conversion start request generation disabled A/D conversion start request generation enabled (Initial value) Bit 6--Reserved: This bit is always read as 1 and cannot be modified. Bit 5--Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 TCIEU 0 1 Description Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled (Initial value) Bit 4--Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. Bit 4 TCIEV 0 1 Description Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled (Initial value) Bit 3--TGR Interrupt Enable D (TGIED): Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. Bit 3 TGIED 0 1 Description Interrupt requests (TGID) by TGFD bit disabled Interrupt requests (TGID) by TGFD bit enabled (Initial value) Rev. 6.00 Feb 22, 2005 page 326 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 2--TGR Interrupt Enable C (TGIEC): Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. Bit 2 TGIEC 0 1 Description Interrupt requests (TGIC) by TGFC bit disabled Interrupt requests (TGIC) by TGFC bit enabled (Initial value) Bit 1--TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. Bit 1 TGIEB 0 1 Description Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled (Initial value) Bit 0--TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. Bit 0 TGIEA 0 1 Description Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled (Initial value) Rev. 6.00 Feb 22, 2005 page 327 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.2.5 Timer Status Register (TSR) Channel 0: TSR0 Channel 3: TSR3 Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 0 -- 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* Note: * Can only be written with 0 for flag clearing. Channel 1: TSR1 Channel 2: TSR2 Channel 4: TSR4 Channel 5: TSR5 Bit : 7 TCFD Initial value : R/W : 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 -- 0 -- 2 -- 0 -- 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* Note: * Can only be written with 0 for flag clearing. The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has six TSR registers, one for each channel. The TSR registers are initialized to H'C0 by a reset, and in hardware standby mode. Rev. 6.00 Feb 22, 2005 page 328 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 7--Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified. Bit 7 TCFD 0 1 Description TCNT counts down TCNT counts up (Initial value) Bit 6--Reserved: This bit is always read as 1 and cannot be modified. Bit 5--Underflow Flag (TCFU): Status flag that indicates that TCNT underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 TCFU 0 1 Description [Clearing condition] * * When 0 is written to TCFU after reading TCFU = 1 When the TCNT value underflows (changes from H'0000 to H'FFFF) [Setting condition] (Initial value) Bit 4--Overflow Flag (TCFV): Status flag that indicates that TCNT overflow has occurred. Bit 4 TCFV 0 1 Description [Clearing condition] * * When 0 is written to TCFV after reading TCFV = 1 When the TCNT value overflows (changes from H'FFFF to H'0000 ) [Setting condition] (Initial value) Rev. 6.00 Feb 22, 2005 page 329 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 3--Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. Bit 3 TGFD 0 Description [Clearing conditions] * * 1 * * When 0 is written to TGFD after reading TGFD = 1 When TCNT = TGRD while TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register (Initial value) When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 [Setting conditions] Bit 2--Input Capture/Output Compare Flag C (TGFC): Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. Bit 2 TGFC 0 Description [Clearing conditions] * * 1 * * When 0 is written to TGFC after reading TGFC = 1 When TCNT = TGRC while TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register (Initial value) When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 [Setting conditions] Rev. 6.00 Feb 22, 2005 page 330 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 1--Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the occurrence of TGRB input capture or compare match. Bit 1 TGFB 0 Description [Clearing conditions] * * 1 * * When 0 is written to TGFB after reading TGFB = 1 When TCNT = TGRB while TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register (Initial value) When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 [Setting conditions] Bit 0--Input Capture/Output Compare Flag A (TGFA): Status flag that indicates the occurrence of TGRA input capture or compare match. Bit 0 TGFA 0 Description [Clearing conditions] * * 1 * * When 0 is written to TGFA after reading TGFA = 1 When TCNT = TGRA while TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register (Initial value) When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 [Setting conditions] Rev. 6.00 Feb 22, 2005 page 331 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.2.6 Timer Counter (TCNT) Channel 0: TCNT0 (up-counter) Channel 1: TCNT1 (up/down-counter*) Channel 2: TCNT2 (up/down-counter*) Channel 3: TCNT3 (up-counter) Channel 4: TCNT4 (up/down-counter*) Channel 5: TCNT5 (up/down-counter*) Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. In other cases they function as upcounters. The TCNT registers are 16-bit counters. The TPU has six TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. Rev. 6.00 Feb 22, 2005 page 332 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.2.7 Bit Timer General Register (TGR) : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The TGR registers are 16-bit registers with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers*. The TGR registers are initialized to H'FFFF by a reset, and in hardware standby mode. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. Note: * TGR buffer register combinations are TGRA--TGRC and TGRB--TGRD. Rev. 6.00 Feb 22, 2005 page 333 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.2.8 Bit Timer Start Register (TSTR) : 7 -- 0 -- 6 -- 0 -- 5 CST5 0 R/W 4 CST4 0 R/W 3 CST3 0 R/W 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W Initial value : R/W : TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5. TSTR is initialized to H'00 by a reset, and in hardware standby mode. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bits 7 and 6--Reserved: Should always be written with 0. Bits 5 to 0--Counter Start 5 to 0 (CST5 to CST0): These bits select operation or stoppage for TCNT. Bit n CSTn 0 1 Description TCNTn count operation is stopped TCNTn performs count operation (Initial value) n = 5 to 0 Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. Rev. 6.00 Feb 22, 2005 page 334 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.2.9 Bit Timer Synchro Register (TSYR) : 7 -- 0 -- 6 -- 0 -- 5 SYNC5 0 R/W 4 SYNC4 0 R/W 3 SYNC3 0 R/W 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W Initial value : R/W : TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. TSYR is initialized to H'00 by a reset, and in hardware standby mode. Bits 7 and 6--Reserved: Should always be written with 0. Bits 5 to 0--Timer Synchro 5 to 0 (SYNC5 to SYNC0): These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels*1, and synchronous clearing through counter clearing on another channel*2 are possible. Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. 2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. Bit n SYNCn 0 1 Description TCNTn operates independently (TCNT presetting/clearing is unrelated to other channels) (Initial value) TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible n = 5 to 0 Rev. 6.00 Feb 22, 2005 page 335 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.2.10 Module Stop Control Register A (MSTPCRA) Bit : 7 0 R/W 6 0 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W : MSTPCRA is an 8-bit readable/writable register that performs module stop mode control. When the MSTPA5 bit in MSTPCRA is set to 1, TPU operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 23A.5, 23B.5, Module Stop Mode. MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 5--Module Stop (MSTPA5): Specifies the TPU module stop mode. Bit 5 MSTPA5 0 1 Description TPU module stop mode cleared TPU module stop mode set (Initial value) Rev. 6.00 Feb 22, 2005 page 336 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3 10.3.1 Interface to Bus Master 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 10-2. Internal data bus H Bus master Module data bus L Bus interface TCNTH TCNTL Figure 10-2 16-Bit Register Access Operation [Bus Master TCNT (16 Bits)] 10.3.2 8-Bit Registers Registers other than TCNT and TGR are 8-bit. As the data bus to the CPU is 16 bits wide, these registers can be read and written to in 16-bit units. They can also be read and written to in 8-bit units. Rev. 6.00 Feb 22, 2005 page 337 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Examples of 8-bit register access operation are shown in figures 10-3, 10-4, and 10-5. Internal data bus H Bus master Module data bus L Bus interface TCR Figure 10-3 8-Bit Register Access Operation [Bus Master TCR (Upper 8 Bits)] Internal data bus H Bus master Module data bus L Bus interface TMDR Figure 10-4 8-Bit Register Access Operation [Bus Master TMDR (Lower 8 Bits)] Internal data bus H Bus master Module data bus L Bus interface TCR TMDR Figure 10-5 8-Bit Register Access Operation [Bus Master TCR and TMDR (16 Bits)] Rev. 6.00 Feb 22, 2005 page 338 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4 10.4.1 Operation Overview Operation in each mode is outlined below. Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Synchronous Operation: When synchronous operation is designated for a channel, TCNT for that channel performs synchronous presetting. That is, when TCNT for a channel designated for synchronous operation is rewritten, the TCNT counters for the other channels are also rewritten at the same time. Synchronous clearing of the TCNT counters is also possible by setting the timer synchronization bits in TSYR for channels designated for synchronous operation. Buffer Operation * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the relevant channel is transferred to TGR. * When TGR is an input capture register When input capture occurs, the value in TCNT is transfer to TGR and the value previously held in TGR is transferred to the buffer register. Cascaded Operation: The channel 1 counter (TCNT1), channel 2 counter (TCNT2), channel 4 counter (TCNT4), and channel 5 counter (TCNT5) can be connected together to operate as a 32bit counter. PWM Mode: In this mode, a PWM waveform is output. The output level can be set by means of TIOR. A PWM waveform with a duty of between 0% and 100% can be output, according to the setting of each TGR register. Phase Counting Mode: In this mode, TCNT is incremented or decremented by detecting the phases of two clocks input from the external clock input pins in channels 1, 2, 4, and 5. When phase counting mode is set, the corresponding TCLK pin functions as the clock pin, and TCNT performs up- or down-counting. This can be used for two-phase encoder pulse input. Rev. 6.00 Feb 22, 2005 page 339 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.2 Basic Functions Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. * Example of count operation setting procedure Figure 10-6 shows an example of the count operation setting procedure. Operation selection [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. Free-running counter [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. Start count operation Select counter clock [1] Periodic counter Select counter clearing source [2] Select output compare register [3] Set period [4] Start count operation [5] Figure 10-6 Example of Counter Operation Setting Procedure Rev. 6.00 Feb 22, 2005 page 340 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) * Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 10-7 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 10-7 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts up-count operation as periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Rev. 6.00 Feb 22, 2005 page 341 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10-8 illustrates periodic counter operation. TCNT value TGR Counter cleared by TGR compare match H'0000 Time CST bit Flag cleared by software or DTC activation TGF Figure 10-8 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. * Example of setting procedure for waveform output by compare match Figure 10-9 shows an example of the setting procedure for waveform output by compare match Output selection Select waveform output mode [1] [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. Set output timing [2] [3] Set the CST bit in TSTR to 1 to start the count operation. Start count operation [3] Figure 10-9 Example of Setting Procedure for Waveform Output by Compare Match Rev. 6.00 Feb 22, 2005 page 342 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) * Examples of waveform output operation Figure 10-10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF TGRA TGRB H'0000 No change TIOCA TIOCB No change No change No change 1 output 0 output Time Figure 10-10 Example of 0 Output/1 Output Operation Figure 10-11 shows an example of toggle output. In this example TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 Time Toggle output Toggle output TIOCB TIOCA Figure 10-11 Example of Toggle Output Operation Rev. 6.00 Feb 22, 2005 page 343 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 3, /1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if /1 is selected. * Example of input capture operation setting procedure Figure 10-12 shows an example of the input capture operation setting procedure. Input selection [1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [1] Select input capture input [2] Set the CST bit in TSTR to 1 to start the count operation. Start count [2] Figure 10-12 Example of Input Capture Operation Setting Procedure Rev. 6.00 Feb 22, 2005 page 344 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) * Example of input capture operation Figure 10-13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. TCNT value H'0180 H'0160 Counter cleared by TIOCB input (falling edge) H'0010 H'0005 H'0000 Time TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 10-13 Example of Input Capture Operation Rev. 6.00 Feb 22, 2005 page 345 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.3 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation. Example of Synchronous Operation Setting Procedure: Figure 10-14 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Synchronous clearing Set TCNT [2] Clearing sourcegeneration channel? Yes Select counter clearing source Start count No [3] [5] Set synchronous counter clearing Start count [4] [5] [1] [2] [3] [4] [5] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Figure 10-14 Example of Synchronous Operation Setting Procedure Rev. 6.00 Feb 22, 2005 page 346 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation: Figure 10-15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGR0B compare match, is performed for channel 0 to 2 TCNT counters, and the data set in TGR0B is used as the PWM cycle. For details of PWM modes, see section 10.4.6, PWM Modes. Synchronous clearing by TGR0B compare match TCNT0 to TCNT2 values TGR0B TGR1B TGR0A TGR2B TGR1A TGR2A H'0000 Time TIOC0A TIOC1A TIOC2A Figure 10-15 Example of Synchronous Operation Rev. 6.00 Feb 22, 2005 page 347 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.4 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 10-5 shows the register combinations used in buffer operation. Table 10-5 Register Combinations in Buffer Operation Channel 0 3 Timer General Register TGR0A TGR0B TGR3A TGR3B Buffer Register TGR0C TGR0D TGR3C TGR3D * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 10-16. Compare match signal Buffer register Timer general register Comparator TCNT Figure 10-16 Compare Match Buffer Operation Rev. 6.00 Feb 22, 2005 page 348 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) * When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 10-17. Input capture signal Timer general register Buffer register TCNT Figure 10-17 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure: Figure 10-18 shows an example of the buffer operation setting procedure. [1] Designate TGR as an input capture register or output compare register by means of TIOR. [1] Buffer operation Select TGR function [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 to start the count operation. Set buffer operation [2] Start count [3] Figure 10-18 Example of Buffer Operation Setting Procedure Rev. 6.00 Feb 22, 2005 page 349 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Examples of Buffer Operation * When TGR is an output compare register Figure 10-19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time compare match A occurs. For details of PWM modes, see section 10.4.6, PWM Modes. TCNT value TGR0B H'0200 TGR0A H'0000 TGR0C H'0200 Transfer TGR0A H'0200 H'0450 H'0450 H'0520 Time H'0520 H'0450 TIOCA Figure 10-19 Example of Buffer Operation (1) Rev. 6.00 Feb 22, 2005 page 350 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) * When TGR is an input capture register Figure 10-20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 H'0F07 H'09FB TGRC H'0532 H'0F07 Figure 10-20 Example of Buffer Operation (2) Rev. 6.00 Feb 22, 2005 page 351 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.5 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 10-6 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. Table 10-6 Cascaded Combinations Combination Channels 1 and 2 Channels 4 and 5 Upper 16 Bits TCNT1 TCNT4 Lower 16 Bits TCNT2 TCNT5 Example of Cascaded Operation Setting Procedure: Figure 10-21 shows an example of the setting procedure for cascaded operation. [1] Set bits TPSC2 to TPSC0 in the channel 1 (channel 4) TCR to B'111 to select TCNT2 (TCNT5) overflow/underflow counting. [1] Cascaded operation Set cascading [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation. Start count [2] Figure 10-21 Cascaded Operation Setting Procedure Rev. 6.00 Feb 22, 2005 page 352 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Examples of Cascaded Operation: Figure 10-22 illustrates the operation when counting upon TCNT2 overflow/underflow has been set for TCNT1, TGR1A, and TGR2A have been designated as input capture registers, and TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A. TCNT1 clock TCNT1 TCNT2 clock TCNT2 TIOCA1, TIOCA2 TGR1A H'03A2 H'FFFF H'0000 H'0001 H'03A1 H'03A2 TGR2A H'0000 Figure 10-22 Example of Cascaded Operation (1) Figure 10-23 illustrates the operation when counting upon TCNT2 overflow/underflow has been set for TCNT1, and phase counting mode has been designated for channel 2. TCNT1 is incremented by TCNT2 overflow and decremented by TCNT2 underflow. TCLKC TCLKD TCNT2 TCNT1 FFFD FFFE FFFF 0000 0001 0002 0001 0001 0000 FFFF 0000 0000 Figure 10-23 Example of Cascaded Operation (2) Rev. 6.00 Feb 22, 2005 page 353 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.6 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. * PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. * PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 10-7. Rev. 6.00 Feb 22, 2005 page 354 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10-7 PWM Output Registers and Output Pins Output Pins Channel 0 Registers TGR0A TGR0B TGR0C TGR0D 1 2 3 TGR1A TGR1B TGR2A TGR2B TGR3A TGR3B TGR3C TGR3D 4 5 TGR4A TGR4B TGR5A TGR5B TIOCA5 TIOCA4 TIOCC3 TIOCA3 TIOCA2 TIOCA1 TIOCC0 PWM Mode 1 TIOCA0 PWM Mode 2 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. Rev. 6.00 Feb 22, 2005 page 355 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Example of PWM Mode Setting Procedure: Figure 10-24 shows an example of the PWM mode setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. Select counter clearing source [2] PWM mode Select counter clock [1] Select waveform output level [3] [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other the TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. Set TGR [4] Set PWM mode [5] [6] Set the CST bit in TSTR to 1 to start the count operation. Start count [6] Figure 10-24 Example of PWM Mode Setting Procedure Rev. 6.00 Feb 22, 2005 page 356 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Examples of PWM Mode Operation: Figure 10-25 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in TGRB registers as the duty. TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 Time TIOCA Figure 10-25 Example of PWM Mode Operation (1) Rev. 6.00 Feb 22, 2005 page 357 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10-26 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGR0A to TGR0D, TGR1A), to output a 5-phase PWM waveform. In this case, the value set in TGR1B is used as the cycle, and the values set in the other TGRs as the duty. Counter cleared by TGR1B compare match TCNT value TGR1B TGR1A TGR0D TGR0C TGR0B TGR0A H'0000 Time TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 Figure 10-26 Example of PWM Mode Operation (2) Rev. 6.00 Feb 22, 2005 page 358 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10-27 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRA TGRB rewritten TGRB H'0000 0% duty TGRB rewritten TGRB rewritten Time TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty TGRB rewritten Time TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty 0% duty TGRB rewritten Time TIOCA Figure 10-27 Example of PWM Mode Operation (3) Rev. 6.00 Feb 22, 2005 page 359 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.7 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 10-8 shows the correspondence between external clock pins and channels. Table 10-8 Phase Counting Mode Clock Input Pins External Clock Pins Channels When channel 1 or 5 is set to phase counting mode When channel 2 or 4 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD Example of Phase Counting Mode Setting Procedure: Figure 10-28 shows an example of the phase counting mode setting procedure. [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Phase counting mode Select phase counting mode [1] Start count [2] Figure 10-28 Example of Phase Counting Mode Setting Procedure Rev. 6.00 Feb 22, 2005 page 360 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. * Phase counting mode 1 Figure 10-29 shows an example of phase counting mode 1 operation, and table 10-9 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10-29 Example of Phase Counting Mode 1 Operation Table 10-9 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Down-count TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count Rev. 6.00 Feb 22, 2005 page 361 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) * Phase counting mode 2 Figure 10-30 shows an example of phase counting mode 2 operation, and table 10-10 summarizes the TCNT up/down-count conditions. TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) TCNT value Up-count Down-count Time Figure 10-30 Example of Phase Counting Mode 2 Operation Table 10-10 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care Don't care Don't care Up-count Don't care Don't care Don't care Down-count Rev. 6.00 Feb 22, 2005 page 362 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) * Phase counting mode 3 Figure 10-31 shows an example of phase counting mode 3 operation, and table 10-11 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10-31 Example of Phase Counting Mode 3 Operation Table 10-11 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care Don't care Don't care Up-count Down-count Don't care Don't care Don't care Rev. 6.00 Feb 22, 2005 page 363 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) * Phase counting mode 4 Figure 10-32 shows an example of phase counting mode 4 operation, and table 10-12 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count Time Figure 10-32 Example of Phase Counting Mode 4 Operation Table 10-12 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Don't care Down-count Don't care TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count Rev. 6.00 Feb 22, 2005 page 364 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Phase Counting Mode Application Example: Figure 10-33 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGR0C compare match; TGR0A and TGR0C are used for the compare match function, and are set with the speed control period and position control period. TGR0B is used for input capture, with TGR0B and TGR0D operating in buffer mode. The channel 1 counter input clock is designated as the TGR0B input capture source, and detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed. TGR1A and TGR1B for channel 1 are designated for input capture, channel 0 TGR0A and TGR0C compare matches are selected as the input capture source, and store the up/down-counter values for the control periods. This procedure enables accurate position/speed detection to be achieved. Rev. 6.00 Feb 22, 2005 page 365 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Channel 1 TCLKA TCLKB Edge detection circuit TCNT1 TGR1A (speed period capture) TGR1B (position period capture) TCNT0 + TGR0A (speed control period) - TGR0C (position control period) + - TGR0B (pulse width capture) TGR0D (buffer operation) Channel 0 Figure 10-33 Phase Counting Mode Application Example Rev. 6.00 Feb 22, 2005 page 366 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.5 10.5.1 Interrupts Interrupt Sources and Priorities There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, but the priority order within a channel is fixed. For details, see section 5, Interrupt Controller. Table 10-13 lists the TPU interrupt sources. Rev. 6.00 Feb 22, 2005 page 367 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10-13 TPU Interrupts Channel 0 Interrupt Source TGI0A TGI0B TGI0C TGI0D TCI0V 1 TGI1A TGI1B TCI1V TCI1U 2 TGI2A TGI2B TCI2V TCI2U 3 TGI3A TGI3B TGI3C TGI3D TCI3V 4 TGI4A TGI4B TCI4V TCI4U 5 TGI5A TGI5B TCI5V TCI5U Description TGR0A input capture/compare match TGR0B input capture/compare match TGR0C input capture/compare match TGR0D input capture/compare match TCNT0 overflow TGR1A input capture/compare match TGR1B input capture/compare match TCNT1 overflow TCNT1 underflow TGR2A input capture/compare match TGR2B input capture/compare match TCNT2 overflow TCNT2 underflow TGR3A input capture/compare match TGR3B input capture/compare match TGR3C input capture/compare match TGR3D input capture/compare match TCNT3 overflow TGR4A input capture/compare match TGR4B input capture/compare match TCNT4 overflow TCNT4 underflow TGR5A input capture/compare match TGR5B input capture/compare match TCNT5 overflow TCNT5 underflow DTC Activation Possible Possible Possible Possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Possible Possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Low Priority High Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. Rev. 6.00 Feb 22, 2005 page 368 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one each for channels 1, 2, 4, and 5. 10.5.2 DTC Activation Note: The DTC is not implemented in the H8S/2635 and H8S/2634. DTC Activation: The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 8, Data Transfer Controller (DTC). A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. 10.5.3 A/D Converter Activation The A/D converter can be activated by the TGRA input capture/compare match for a channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. Rev. 6.00 Feb 22, 2005 page 369 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.6 10.6.1 Operation Timing Input/Output Timing TCNT Count Timing: Figure 10-34 shows TCNT count timing in internal clock operation, and figure 10-35 shows TCNT count timing in external clock operation. Internal clock Falling edge Rising edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 10-34 Count Timing in Internal Clock Operation External clock Falling edge Rising edge Falling edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 10-35 Count Timing in External Clock Operation Rev. 6.00 Feb 22, 2005 page 370 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 10-36 shows output compare output timing. TCNT input clock TCNT N N+1 TGR N Compare match signal TIOC pin Figure 10-36 Output Compare Output Timing Input Capture Signal Timing: Figure 10-37 shows input capture signal timing. Input capture input Input capture signal TCNT N N+1 N+2 TGR N N+2 Figure 10-37 Input Capture Input Signal Timing Rev. 6.00 Feb 22, 2005 page 371 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Timing for Counter Clearing by Compare Match/Input Capture: Figure 10-38 shows the timing when counter clearing by compare match occurrence is specified, and figure 10-39 shows the timing when counter clearing by input capture occurrence is specified. Compare match signal Counter clear signal N H'0000 TCNT TGR N Figure 10-38 Counter Clear Timing (Compare Match) Input capture signal Counter clear signal N H'0000 TCNT TGR N Figure 10-39 Counter Clear Timing (Input Capture) Rev. 6.00 Feb 22, 2005 page 372 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Buffer Operation Timing: Figures 10-40 and 10-41 show the timing in buffer operation. TCNT n n+1 Compare match signal TGRA, TGRB TGRC, TGRD n N N Figure 10-40 Buffer Operation Timing (Compare Match) Input capture signal TCNT TGRA, TGRB TGRC, TGRD N N+1 n N N+1 n N Figure 10-41 Buffer Operation Timing (Input Capture) Rev. 6.00 Feb 22, 2005 page 373 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 10-42 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. TCNT input clock TCNT N N+1 TGR N Compare match signal TGF flag TGI interrupt Figure 10-42 TGI Interrupt Timing (Compare Match) Rev. 6.00 Feb 22, 2005 page 374 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) TGF Flag Setting Timing in Case of Input Capture: Figure 10-43 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing. Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 10-43 TGI Interrupt Timing (Input Capture) Rev. 6.00 Feb 22, 2005 page 375 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) TCFV Flag/TCFU Flag Setting Timing: Figure 10-44 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 10-45 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing. TCNT input clock TCNT (overflow) Overflow signal TCFV flag H'FFFF H'0000 TCIV interrupt Figure 10-44 TCIV Interrupt Setting Timing TCNT input clock TCNT (underflow) Underflow signal H'0000 H'FFFF TCFU flag TCIU interrupt Figure 10-45 TCIU Interrupt Setting Timing Rev. 6.00 Feb 22, 2005 page 376 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC* is activated, the flag is cleared automatically. Figure 10-46 shows the timing for status flag clearing by the CPU, and figure 10-47 shows the timing for status flag clearing by the DTC. Note: * The DTC is not implemented in the H8S/2635 and H8S/2634. TSR write cycle T1 T2 Address TSR address Write signal Status flag Interrupt request signal Figure 10-46 Timing for Status Flag Clearing by CPU DTC read cycle T1 T2 DTC write cycle T1 T2 Address Source address Destination address Status flag Interrupt request signal Figure 10-47 Timing for Status Flag Clearing by DTC Activation Rev. 6.00 Feb 22, 2005 page 377 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) 10.7 Usage Notes Note that the kinds of operation and contention described below occur during TPU operation. Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10-48 shows the input clock conditions in phase counting mode. Phase Phase differdifference Overlap ence Overlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap: 1.5 states or more 2.5 states or more Pulse width: Figure 10-48 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Caution on Period Setting: When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= Where (N + 1) f : Counter frequency : Operating frequency N : TGR set value Rev. 6.00 Feb 22, 2005 page 378 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10-49 shows the timing in this case. TCNT write cycle T2 T1 Address TCNT address Write signal Counter clear signal TCNT N H'0000 Figure 10-49 Contention between TCNT Write and Clear Operations Rev. 6.00 Feb 22, 2005 page 379 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Contention between TCNT Write and Increment Operations: If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 10-50 shows the timing in this case. TCNT write cycle T2 T1 Address TCNT address Write signal TCNT input clock N TCNT write data M TCNT Figure 10-50 Contention between TCNT Write and Increment Operations Rev. 6.00 Feb 22, 2005 page 380 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Contention between TGR Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 10-51 shows the timing in this case. TGR write cycle T2 T1 Address TGR address Write signal Compare match signal TCNT N N+1 Prohibited TGR N TGR write data M Figure 10-51 Contention between TGR Write and Compare Match Rev. 6.00 Feb 22, 2005 page 381 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 10-52 shows the timing in this case. TGR write cycle T2 T1 Address Buffer register address Write signal Compare match signal Buffer register write data Buffer register TGR N M N Figure 10-52 Contention between Buffer Register Write and Compare Match Rev. 6.00 Feb 22, 2005 page 382 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Contention between TGR Read and Input Capture: If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 10-53 shows the timing in this case. TGR read cycle T2 T1 Address TGR address Read signal Input capture signal TGR X M Internal data bus M Figure 10-53 Contention between TGR Read and Input Capture Rev. 6.00 Feb 22, 2005 page 383 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Contention between TGR Write and Input Capture: If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10-54 shows the timing in this case. TGR write cycle T2 T1 Address TGR address Write signal Input capture signal TCNT M TGR M Figure 10-54 Contention between TGR Write and Input Capture Rev. 6.00 Feb 22, 2005 page 384 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T2 state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10-55 shows the timing in this case. Buffer register write cycle T1 T2 Address Buffer register address Write signal Input capture signal TCNT N TGR Buffer register M N M Figure 10-55 Contention between Buffer Register Write and Input Capture Rev. 6.00 Feb 22, 2005 page 385 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10-56 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. TCNT input clock TCNT Counter clear signal TGF Prohibited TCFV H'FFFF H'0000 Figure 10-56 Contention between Overflow and Counter Clearing Rev. 6.00 Feb 22, 2005 page 386 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Contention between TCNT Write and Overflow/Underflow: If there is an up-count or downcount in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 10-57 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T1 T2 Address TCNT address Write signal TCNT write data H'FFFF Prohibited M TCNT TCFV flag Figure 10-57 Contention between TCNT Write and Overflow Multiplexing of I/O Pins: In the chip, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. Interrupts and Module Stop Mode: If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC* activation source. Interrupts should therefore be disabled before entering module stop mode. Note: * The DTC is not implemented in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 387 of 1484 REJ09B0103-0600 Section 10 16-Bit Timer Pulse Unit (TPU) Rev. 6.00 Feb 22, 2005 page 388 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) Section 11 Programmable Pulse Generator (PPG) Note: The H8S/2635 Group is not equipped with a PPG. 11.1 Overview The chip has an on-chip programmable pulse generator (PPG) that provides pulse outputs by using the 16-bit timer-pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (group 3 and group 2) that can operate both simultaneously and independently. 11.1.1 Features PPG features are listed below. * 8-bit output data Maximum 8-bit data can be output, and output can be enabled on a bit-by-bit basis * Two output groups Output trigger signals can be selected in 4-bit groups to provide up to two different 4-bit outputs * Selectable output trigger signals Output trigger signals can be selected for each group from the compare match signals of four TPU channels * Non-overlap mode A non-overlap margin can be provided between pulse outputs * Can operate together with the data transfer controller (DTC) The compare match signals selected as output trigger signals can activate the DTC for sequential output of data without CPU intervention * Settable inverted output Inverted data can be output for each group * Module stop mode can be set As the initial setting, PPG operation is halted. Register access is enabled by exiting module stop mode Rev. 6.00 Feb 22, 2005 page 389 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) 11.1.2 Block Diagram Figure 11-1 shows a block diagram of the PPG. Compare match signals NDERH Control logic PMR NDERL PCR PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Pulse output pins, group 3 PODRH Pulse output pins, group 2 Pulse output pins, group 1 PODRL Pulse output pins, group 0 NDRL NDRH Internal data bus Legend: PMR: PCR: NDERH: NDERL: NDRH: NDRL: PODRH: PODRL: PPG output mode register PPG output control register Next data enable register H Next data enable register L Next data register H Next data register L Output data register H Output data register L Figure 11-1 Block Diagram of PPG Rev. 6.00 Feb 22, 2005 page 390 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) 11.1.3 Pin Configuration Table 11-1 summarizes the PPG pins. Table 11-1 PPG Pins Name Pulse output 8 Pulse output 9 Pulse output 10 Pulse output 11 Pulse output 12 Pulse output 13 Pulse output 14 Pulse output 15 Symbol PO8 PO9 PO10 PO11 PO12 PO13 PO14 PO15 I/O Output Output Output Output Output Output Output Output Group 3 pulse output Function Group 2 pulse output Rev. 6.00 Feb 22, 2005 page 391 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) 11.1.4 Registers Table 11-2 summarizes the PPG registers. Table 11-2 PPG Registers Name PPG output control register PPG output mode register Next data enable register H Next data enable register L*4 Output data register H Output data register L*4 Next data register H Next data register L*4 Port 1 data direction register Module stop control register A Abbreviation PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL P1DDR MSTPCRA R/W R/W R/W R/W R/W R/(W)*2 R/(W)*2 R/W R/W W R/W Initial Value H'FF H'F0 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'3F Address*1 H'FE26 H'FE27 H'FE28 H'FE29 H'FE2A H'FE2B H'FE2C*3 H'FE2E H'FE2D*3 H'FE2F H'FE30 H'FDE8 Notes: 1. Lower 16 bits of the address. 2. Bits used for pulse output cannot be written to. 3. When the same output trigger is selected for pulse output groups 2 and 3 by the PCR setting, the NDRH address is H'FE2C. When the output triggers are different, the NDRH address is H'FE2E for group 2 and H'FE2C for group 3. Similarly, when the same output trigger is selected for pulse output groups 0 and 1 by the PCR setting, the NDRL address is H'FE2D. When the output triggers are different, the NDRL address is H'FE2F for group 0 and H'FE2D for group 1. 4. The chip has no pins corresponding to pulse output groups 0 and 1. Rev. 6.00 Feb 22, 2005 page 392 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) 11.2 11.2.1 Register Descriptions Next Data Enable Registers H and L (NDERH, NDERL) NDERH Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 NDER8 0 R/W NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 Initial value : R/W NDERL Bit : 7 NDER7 Initial value : R/W : 0 R/W 6 NDER6 0 R/W 5 NDER5 0 R/W 4 NDER4 0 R/W 3 NDER3 0 R/W 2 NDER2 0 R/W 1 NDER1 0 R/W : 0 NDER0 0 R/W NDERH and NDERL are 8-bit readable/writable registers that enable or disable pulse output on a bit-by-bit basis. If a bit is enabled for pulse output by NDERH or NDERL, the NDR value is automatically transferred to the corresponding PODR bit when the TPU compare match event specified by PCR occurs, updating the output value. If pulse output is disabled, the bit value is not transferred from NDR to PODR and the output value does not change. NDERH and NDERL are each initialized to H'00 by a reset and in hardware standby mode. They are not initialized in software standby mode. NDERH Bits 7 to 0--Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or disable pulse output on a bit-by-bit basis. Bits 7 to 0 NDER15 to NDER8 0 1 Description Pulse outputs PO15 to PO8 are disabled (NDR15 to NDR8 are not transferred to POD15 to POD8) (Initial value) Pulse outputs PO15 to PO8 are enabled (NDR15 to NDR8 are transferred to POD15 to POD8) Rev. 6.00 Feb 22, 2005 page 393 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) NDERL Bits 7 to 0--Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable pulse output on a bit-by-bit basis. Bits 7 to 0 NDER7 to NDER0 0 1 Description Pulse outputs PO7 to PO0 are disabled (NDR7 to NDR0 are not transferred to POD7 to POD0) (Initial value) Pulse outputs PO7 to PO0 are enabled (NDR7 to NDR0 are transferred to POD7 to POD0) 11.2.2 Output Data Registers H and L (PODRH, PODRL) PODRH Bit : 7 POD15 Initial value : R/W PODRL Bit : 7 POD7 Initial value : R/W : 0 R/(W)* 6 POD6 0 R/(W)* 5 POD5 0 R/(W)* 4 POD4 0 R/(W)* 3 POD3 0 R/(W)* 2 POD2 0 R/(W)* 1 POD1 0 R/(W)* 0 POD0 0 R/(W)* : 0 R/(W)* 6 POD14 0 R/(W)* 5 POD13 0 R/(W)* 4 POD12 0 R/(W)* 3 POD11 0 R/(W)* 2 POD10 0 R/(W)* 1 POD9 0 R/(W)* 0 POD8 0 R/(W)* Note: * A bit that has been set for pulse output by NDER is read-only. PODRH and PODRL are 8-bit readable/writable registers that store output data for use in pulse output. However, the chip has no pins corresponding to PODRL. Rev. 6.00 Feb 22, 2005 page 394 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) 11.2.3 Next Data Registers H and L (NDRH, NDRL) NDRH and NDRL are 8-bit readable/writable registers that store the next data for pulse output. During pulse output, the contents of NDRH and NDRL are transferred to the corresponding bits in PODRH and PODRL when the TPU compare match event specified by PCR occurs. The NDRH and NDRL addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. For details see section 11.2.4, Notes on NDR Access. NDRH and NDRL are each initialized to H'00 by a reset and in hardware standby mode. They are not initialized in software standby mode. 11.2.4 Notes on NDR Access The NDRH and NDRL addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. Same Trigger for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by the same compare match event, the NDRH address is H'FE2C. The upper 4 bits belong to group 3 and the lower 4 bits to group 2. Address H'FE2E consists entirely of reserved bits that cannot be modified and are always read as 1. Address H'FE2C Bit : 7 NDR15 Initial value : R/W : 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Address H'FE2E Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- If pulse output groups 0 and 1 are triggered by the same compare match event, the NDRL address is H'FE2D. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FE2F consists entirely of reserved bits that cannot be modified and are always read as 1. However, the chip has no output pins corresponding to pulse output groups 0 and 1. Rev. 6.00 Feb 22, 2005 page 395 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) Address H'FE2D Bit : 7 NDR7 Initial value : R/W : 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Address H'FE2F Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Different Triggers for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits in NDRH (group 3) is H'FE2C and the address of the lower 4 bits (group 2) is H'FE2E. Bits 3 to 0 of address H'FE2C and bits 7 to 4 of address H'FE2E are reserved bits that cannot be modified and are always read as 1. Address H'FE2C Bit : 7 NDR15 Initial value : R/W : 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Address H'FE2E Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W If pulse output groups 0 and 1 are triggered by different compare match event, the address of the upper 4 bits in NDRL (group 1) is H'FE2D and the address of the lower 4 bits (group 0) is H'FE2F. Bits 3 to 0 of address H'FE2D and bits 7 to 4 of address H'FE2F are reserved bits that cannot be modified and are always read as 1. However, the chip has no output pins corresponding to pulse output groups 0 and 1. Rev. 6.00 Feb 22, 2005 page 396 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) Address H'FE2D Bit : 7 NDR7 Initial value : R/W : 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Address H'FE2F Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W 11.2.5 Bit PPG Output Control Register (PCR) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value : R/W : PCR is an 8-bit readable/writable register that selects output trigger signals for PPG outputs on a group-by-group basis. PCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 and 6--Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits select the compare match that triggers pulse output group 3 (pins PO15 to PO12). Description Bit 7 G3CMS1 0 1 Bit 6 G3CMS0 0 1 0 1 Output Trigger for Pulse Output Group 3 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 (Initial value) Rev. 6.00 Feb 22, 2005 page 397 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) Bits 5 and 4--Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits select the compare match that triggers pulse output group 2 (pins PO11 to PO8). Description Bit 5 G2CMS1 0 1 Bit 4 G2CMS0 0 1 0 1 Output Trigger for Pulse Output Group 2 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 (Initial value) Bits 3 and 2--Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match that triggers pulse output group 1 (pins PO7 to PO4). However, the chip has no output pins corresponding to pulse output group 1. Description Bit 3 G1CMS1 0 1 Bit 2 G1CMS0 0 1 0 1 Output Trigger for Pulse Output Group 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 (Initial value) Bits 1 and 0--Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits select the compare match that triggers pulse output group 0 (pins PO3 to PO0). However, the chip has no output pins corresponding to pulse output group 0. Description Bit 1 G0CMS1 0 1 Bit 0 G0CMS0 0 1 0 1 Output Trigger for Pulse Output Group 0 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 (Initial value) Rev. 6.00 Feb 22, 2005 page 398 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) 11.2.6 Bit PPG Output Mode Register (PMR) : 7 G3INV 1 R/W 6 G2INV 1 R/W 5 G1INV 1 R/W 4 G0INV 1 R/W 3 G3NOV 0 R/W 2 G2NOV 0 R/W 1 G1NOV 0 R/W 0 G0NOV 0 R/W Initial value : R/W : PMR is an 8-bit readable/writable register that selects pulse output inversion and non-overlapping operation for each group. The output trigger period of a non-overlapping operation PPG output waveform is set in TGRB and the non-overlap margin is set in TGRA. The output values change at compare match A and B. For details, see section 11.3.4, Non-Overlapping Pulse Output. PMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Group 3 Inversion (G3INV): Selects direct output or inverted output for pulse output group 3 (pins PO15 to PO12). Bit 7 G3INV 0 1 Description Inverted output for pulse output group 3 (low-level output at pin for a 1 in PODRH) Direct output for pulse output group 3 (high-level output at pin for a 1 in PODRH) (Initial value) Bit 6--Group 2 Inversion (G2INV): Selects direct output or inverted output for pulse output group 2 (pins PO11 to PO8). Bit 6 G2INV 0 1 Description Inverted output for pulse output group 2 (low-level output at pin for a 1 in PODRH) Direct output for pulse output group 2 (high-level output at pin for a 1 in PODRH) (Initial value) Rev. 6.00 Feb 22, 2005 page 399 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) Bit 5--Group 1 Inversion (G1INV): Selects direct output or inverted output for pulse output group 1 (pins PO7 to PO4). However, the chip has no pins corresponding to pulse output group 1. Bit 5 G1INV 0 1 Description Inverted output for pulse output group 1 (low-level output at pin for a 1 in PODRL) Direct output for pulse output group 1 (high-level output at pin for a 1 in PODRL) (Initial value) Bit 4--Group 0 Inversion (G0INV): Selects direct output or inverted output for pulse output group 0 (pins PO3 to PO0). However, the chip has no pins corresponding to pulse output group 0. Bit 4 G0INV 0 1 Description Inverted output for pulse output group 0 (low-level output at pin for a 1 in PODRL) Direct output for pulse output group 0 (high-level output at pin for a 1 in PODRL) (Initial value) Bit 3--Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping operation for pulse output group 3 (pins PO15 to PO12). Bit 3 G3NOV 0 1 Description Normal operation in pulse output group 3 (output values updated at compare match A in the selected TPU channel) (Initial value) Non-overlapping operation in pulse output group 3 (independent 1 and 0 output at compare match A or B in the selected TPU channel) Bit 2--Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping operation for pulse output group 2 (pins PO11 to PO8). Bit 2 G2NOV 0 1 Description Normal operation in pulse output group 2 (output values updated at compare match A in the selected TPU channel) (Initial value) Non-overlapping operation in pulse output group 2 (independent 1 and 0 output at compare match A or B in the selected TPU channel) Rev. 6.00 Feb 22, 2005 page 400 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) Bit 1--Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping operation for pulse output group 1 (pins PO7 to PO4). However, the chip has no pins corresponding to pulse output group 1. Bit 1 G1NOV 0 1 Description Normal operation in pulse output group 1 (output values updated at compare match A in the selected TPU channel) (Initial value) Non-overlapping operation in pulse output group 1 (independent 1 and 0 output at compare match A or B in the selected TPU channel) Bit 0--Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping operation for pulse output group 0 (pins PO3 to PO0). However, the chip has no pins corresponding to pulse output group 0. Bit 0 G0NOV 0 1 Description Normal operation in pulse output group 0 (output values updated at compare match A in the selected TPU channel) (Initial value) Non-overlapping operation in pulse output group 0 (independent 1 and 0 output at compare match A or B in the selected TPU channel) Rev. 6.00 Feb 22, 2005 page 401 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) 11.2.7 Bit Port 1 Data Direction Register (P1DDR) : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : R/W : P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. Port 1 is multiplexed with pins PO15 to PO8. Bits corresponding to pins used for PPG output must be set to 1. For further information about P1DDR, see section 9.2, Port 1. 11.2.8 Bit Module Stop Control Register A (MSTPCRA) : 7 0 R/W 6 0 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W : MSTPCRA is a 16-bit readable/writable register that performs module stop mode control. When the MSTPA3 bit in MSTPCRA is set to 1, PPG operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 23A.5, 23B.5, Module Stop Mode. MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized by a manual reset and in software standby mode. Bit 3--Module Stop (MSTPA3): Specifies the PPG module stop mode. Bit 3 MSTPA3 0 1 Description PPG module stop mode cleared PPG module stop mode set (Initial value) Rev. 6.00 Feb 22, 2005 page 402 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) 11.3 11.3.1 Operation Overview PPG pulse output is enabled when the corresponding bits in P1DDR and NDER are set to 1. In this state the corresponding PODR contents are output. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values. Figure 11-2 illustrates the PPG output operation and table 11-3 summarizes the PPG operating conditions. DDR NDER Q Output trigger signal C Q PODR D Pulse output pin Normal output/inverted output Q NDR D Internal data bus Figure 11-2 PPG Output Operation Table 11-3 PPG Operating Conditions NDER 0 1 DDR 0 1 0 1 Pin Function Generic input port Generic output port Generic input port (but the PODR bit is a read-only bit, and when compare match occurs, the NDR bit value is transferred to the PODR bit) PPG pulse output Sequential output of data of up to 16 bits is possible by writing new output data to NDR before the next compare match. For details of non-overlapping operation, see section 11.3.4, NonOverlapping Pulse Output. Rev. 6.00 Feb 22, 2005 page 403 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) 11.3.2 Output Timing If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 11-3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. TCNT N N+1 TGRA N Compare match A signal NDRH n PODRH m n PO8 to PO15 m n Figure 11-3 Timing of Transfer and Output of NDR Contents (Example) Rev. 6.00 Feb 22, 2005 page 404 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) 11.3.3 Normal Pulse Output Sample Setup Procedure for Normal Pulse Output: Figure 11-4 shows a sample procedure for setting up normal pulse output. [1] Set TIOR to make TGRA an output compare register (with output disabled) [2] Set the PPG output trigger period Set TGRA value TPU setup Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set next pulse output data TPU setup Start counter Compare match? Yes Set next pulse output data [10] [3] [4] [5] [6] [7] [8] [2] Normal PPG output Select TGR functions [1] [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the DDR and NDER bits for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the output trigger in PCR. [8] Set the next pulse output values in NDR. [9] Set the CST bit in TSTR to 1 to start the TCNT counter. [10] At each TGIA interrupt, set the next output values in NDR. Port and PPG setup [9] No Figure 11-4 Setup Procedure for Normal Pulse Output (Example) Rev. 6.00 Feb 22, 2005 page 405 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) Example of Normal Pulse Output (Example of Five-Phase Pulse Output): Figure 11-5 shows an example in which pulse output is used for cyclic five-phase pulse output. TCNT value TGRA TCNT Compare match H'0000 NDRH 80 C0 40 60 20 30 10 18 08 88 80 C0 40 Time PODRH 00 80 C0 40 60 20 30 10 18 08 88 80 C0 PO15 PO14 PO13 PO12 PO11 Figure 11-5 Normal Pulse Output Example (Five-Phase Pulse Output) [1] Set up the TPU channel to be used as the output trigger channel so that TGRA is an output compare register and the counter will be cleared by compare match A. Set the trigger period in TGRA and set the TGIEA bit in TIER to 1 to enable the compare match A (TGIA) interrupt. [2] Write H'F8 in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Write output data H'80 in NDRH. [3] The timer counter in the TPU channel starts. When compare match A occurs, the NDRH contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the next output data (H'C0) in NDRH. [4] Five-phase overlapping pulse output (one or two phases active at a time) can be obtained subsequently by writing H'40, H'60, H'20, H'30. H'10, H'18, H'08, H'88... at successive TGIA Rev. 6.00 Feb 22, 2005 page 406 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) interrupts. If the DTC is set for activation by this interrupt, pulse output can be obtained without imposing a load on the CPU. 11.3.4 Non-Overlapping Pulse Output Sample Setup Procedure for Non-Overlapping Pulse Output: Figure 11-6 shows a sample procedure for setting up non-overlapping pulse output. Non-overlapping PPG output Select TGR functions Set TGR values TPU setup Set counting operation Select interrupt request Set initial output data Enable pulse output PPG setup Select output trigger Set non-overlapping groups Set next pulse output data TPU setup Start counter Compare match? Yes Set next pulse output data [11] [3] [4] [5] [6] [7] [8] [9] [10] No [1] [2] [1] Set TIOR to make TGRA and TGRB an output compare registers (with output disabled) [2] Set the pulse output trigger period in TGRB and the non-overlap margin in TGRA. [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the DDR and NDER bits for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the pulse output trigger in PCR. [8] In PMR, select the groups that will operate in non-overlap mode. [9] Set the next pulse output values in NDR. [10] Set the CST bit in TSTR to 1 to start the TCNT counter. [11] At each TGIA interrupt, set the next output values in NDR. Figure 11-6 Setup Procedure for Non-Overlapping Pulse Output (Example) Rev. 6.00 Feb 22, 2005 page 407 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary NonOverlapping Output): Figure 11-7 shows an example in which pulse output is used for fourphase complementary non-overlapping pulse output. TCNT value TGRB TGRA H'0000 NDRH 95 65 59 56 95 65 Time TCNT PODRH 00 95 05 65 41 59 50 56 14 95 05 65 Non-overlap margin PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 11-7 Non-Overlapping Pulse Output Example (Four-Phase Complementary) Rev. 6.00 Feb 22, 2005 page 408 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) [1] Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt. [2] Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output. Write output data H'95 in NDRH. [3] The timer counter in the TPU channel starts. When a compare match with TGRB occurs, outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt handling routine writes the next output data (H'65) in NDRH. [4] Four-phase complementary non-overlapping pulse output can be obtained subsequently by writing H'59, H'56, H'95... at successive TGIA interrupts. If the DTC is set for activation by this interrupt, pulse output can be obtained without imposing a load on the CPU. Rev. 6.00 Feb 22, 2005 page 409 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) 11.3.5 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 11-8 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 11-7. TCNT value TGRB TGRA H'0000 NDRH 95 65 59 56 95 65 Time TCNT PODRL 00 95 05 65 41 59 50 56 14 95 05 65 PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 11-8 Inverted Pulse Output (Example) Rev. 6.00 Feb 22, 2005 page 410 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) 11.3.6 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 11-9 shows the timing of this output. TIOC pin Input capture signal NDR N PODR M N PO M N Figure 11-9 Pulse Output Triggered by Input Capture (Example) Rev. 6.00 Feb 22, 2005 page 411 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) 11.4 Usage Notes Operation of Pulse Output Pins: Pins PO8 to PO15 are also used for other peripheral functions such as the TPU. When output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins. Pin functions should be changed only under conditions in which the output trigger event will not occur. Note on Non-Overlapping Output: During non-overlapping operation, the transfer of NDR bit values to PODR bits takes place as follows. * NDR bits are always transferred to PODR bits at compare match A. * At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 11-10 illustrates the non-overlapping pulse output operation. DDR NDER Q Compare match A Compare match B Pulse output pin C Q PODR D Q NDR D Internal data bus Normal output/inverted output Figure 11-10 Non-Overlapping Pulse Output Rev. 6.00 Feb 22, 2005 page 412 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the TGIA interrupt handling routine write the next data in NDR, or by having the TGIA interrupt activate the DTC. Note, however, that the next data must be written before the next compare match B occurs. Figure 11-11 shows the timing of this operation. Compare match A Compare match B Write to NDR NDR PODR 0 output 0/1 output Write to NDR Do not write here to NDR here 0 output 0/1 output Write to NDR Do not write here to NDR here Write to NDR Figure 11-11 Non-Overlapping Operation and NDR Write Timing Rev. 6.00 Feb 22, 2005 page 413 of 1484 REJ09B0103-0600 Section 11 Programmable Pulse Generator (PPG) Rev. 6.00 Feb 22, 2005 page 414 of 1484 REJ09B0103-0600 Section 12 Watchdog Timer Section 12 Watchdog Timer 12.1 Overview The chip has two channel inbuilt watchdog timers (WDT0/WDT1). The WDT can also generate an internal reset signal for the chip if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. 12.1.1 Features WDT features are listed below. * Switchable between watchdog timer mode and interval timer mode * An internal reset can be issued if the timer counter overflows In the watchdog timer mode, the WDT can generate an internal reset * Interrupt generation when in interval timer mode If the counter overflows, the WDT generates an interval timer interrupt * WDT0 and WDT1 respectively allow eight and sixteen types*1 of counter input clock to be selected The maximum interval of the WDT is given as a system clock cycle x 131072 x 256 A subclock*2 may be selected for the input counter of WDT1 Where a subclock is selected, the maximum interval is given as a subclock cycle x 256 x 256 Notes: 1. Other than the U-mask and W-mask versions, and H8S/2635 Group have eight types of counter input clock as well as WDT0. 2. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. See section 22A.7, Subclock Oscillator, for the method of fixing pins when OSC1 and OSC2 are not used. The H8S/2639 and H8S/2635 Groups have no OSC1 and OSC2 pins. Rev. 6.00 Feb 22, 2005 page 415 of 1484 REJ09B0103-0600 Section 12 Watchdog Timer 12.1.2 Block Diagram Figures 12-1 (a) and 12-1 (b) show block diagrams of the WDT. Overflow WOVI 0 (interrupt request signal) Interrupt control Clock Clock select Internal reset signal*1 Reset control /2*2 /64*2 /128*2 /512*2 /2048*2 /8192*2 /32768*2 /131072*2 Internal clock sources RSTCSR TCNT TSCR Module bus Bus interface WDT Legend: Timer control/status register TCSR: Timer counter TCNT: RSTCSR: Reset control/status register Notes: 1. The type of internal reset signal depends on a register setting. 2. In the U-mask and W-mask versions, and H8S/2635 Group, in subactive and subsleep modes operates as SUB. Figure 12-1 (a) Block Diagram of WDT0 Rev. 6.00 Feb 22, 2005 page 416 of 1484 REJ09B0103-0600 Internal bus Section 12 Watchdog Timer WOVI1 (Interrupt request signal) Internal NMI Interrupt request signal Internal reset signal*1 Interrupt control Reset control Overflow Clock Clock select /2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock SUB/2*2 SUB/4*2 SUB/8*2 SUB/16*2 SUB/32*2 SUB/64*2 SUB/128*2 SUB/256*2 TCNT TCSR Module bus WDT Legend: TCSR : Timer control/status register TCNT : Timer counter Bus interface Notes: 1. An internal reset signal can be generated by setting the register The reset thus generated is a reset 2. Subclock functions (subactive mode, subsleep mode, and watch mode) are available only in the U-mask and W-mask versions, and H8S/2635 Group only. Figure 12-1 (b) Block Diagram of WDT1 Rev. 6.00 Feb 22, 2005 page 417 of 1484 REJ09B0103-0600 Internal bus Section 12 Watchdog Timer 12.1.3 Pin Configuration There are no pins related to the WDT. 12.1.4 Register Configuration The WDT has five registers, as summarized in table 12-1. These registers control clock selection, WDT mode switching, and the reset signal. Table 12-1 WDT Registers Address*1 Channel Name 0 Abbreviation R/W Initial Value Write*2 Read H'FF74 H'FF74 H'FF74 H'FF75 H'FF76 H'FF77 H'FFA2 H'FFA2 H'FFA2 H'FFA3 R/(W)*3 H'18 H'00 *3 H'1F R/(W) R/(W)*3 H'00 R/W H'00 R/W Timer control/status register 0 TCSR0 Timer counter 0 Reset control/status register TCNT0 RSTCSR0 TCNT1 1 Timer control/status register 1 TCSR1 Timer counter 1 Notes: 1. Lower 16 bits of the address. 2. For details of write operations, see section 12.2.4, Notes on Register Access. 3. Only a write of 0 is permitted to bit 7, to clear the flag. Rev. 6.00 Feb 22, 2005 page 418 of 1484 REJ09B0103-0600 Section 12 Watchdog Timer 12.2 12.2.1 Bit Register Descriptions Timer Counter (TCNT) : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Initial value : R/W : TCNT is an 8-bit readable/writable* up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), an interval timer interrupt (WOVI) is generated, depending on the mode selected by the WT/IT bit in TCSR. TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared to 0. It is not initialized in software standby mode. Note: * TCNT is write-protected by a password to prevent accidental overwriting. For details see section 12.2.4, Notes on Register Access. Rev. 6.00 Feb 22, 2005 page 419 of 1484 REJ09B0103-0600 Section 12 Watchdog Timer 12.2.2 TCSR0 Bit Timer Control/Status Register (TCSR) : 7 OVF 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 -- 3 -- 1 -- 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : Note: * Only a 0 may be written to this bit to clear the flag. TCSR1 Bit : 7 OVF Initial value : R/W : 0 R/(W) *1 6 WT/IT 0 R/W 5 TME 0 R/W 4 PSS*2 0 R/W 3 RST/NMI 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Notes: 1. Only a 0 may be written to this bit to clear the flag. 2. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be input to TCNT, and the timer mode. TCSR0 (TCSR1) is initialized to H'18 (H'00) by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see section 12.2.4, Notes on Register Access. Rev. 6.00 Feb 22, 2005 page 420 of 1484 REJ09B0103-0600 Section 12 Watchdog Timer Bit 7--Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00. Bit 7 OVF 0 Description [Clearing conditions] * * 1 * Cleared when 0 is written to the TME bit (Only applies to WDT1) Cleared by reading TCSR* when OVF = 1, then writing 0 to OVF When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. (Initial value) [Setting condition] Note: * When interval timer interrupts are disabled and OVF is polled, read the OVF = 1 state at least twice. In the interval timer mode, the OVF flag can be cleared in the interval timer interrupt routine by writing 0 to OVF after reading TCSR when OVF is set to 1, in accordance with the conditions for clearing the OVF flag. However, when attempting to poll the OVF flag when interval timer interrupts are prohibited the OVF value will not be recognized as 1 (even though it is set to 1) if there is a conflict between the timing used to set the OVF flag and the timing used to read the OVF flag. In such cases it is possible to completely satisfy the conditions for clearing the OVF flag by reading OVF two or more times while its value is 1. In a situation such as the above, the OVF flag should be read two or more times while its value is 1 and then cleared. Bit 6--Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or interval timer. This selection determines whether WDT0 issues an internal reset when TCNT overflows while bit RSTE of the reset control/status register (RSTCSR) is set to 1. In the interval timer mode, WDT0 sends a WOVI interrupt request to the CPU. WDT1, on the other hand, requests a reset or an NMI interrupt from the CPU if the watchdog timer mode is chosen, whereas it requests a WOVI interrupt from the CPU if the interval timer mode is chosen. Rev. 6.00 Feb 22, 2005 page 421 of 1484 REJ09B0103-0600 Section 12 Watchdog Timer WDT0 Mode Select TCSR0 WT/IT 0 1 Description Interval timer mode: WDT0 requests an interval timer interrupt (WOVI) from the CPU when the TCNT overflows (Initial value) Watchdog timer mode: A reset is issued when the TCNT overflows if the RSTE bit of RSTCSR is set to 1* Note: * For details see section 12.2.3, Reset Control/Status Register (RSTCSR). WDT1 Mode Select TCSR1 WT/IT 0 1 Description Interval timer mode: WDT1 requests an interval timer interrupt (WOVI) from the CPU when the TCNT overflows Watchdog timer mode: WDT1 requests a reset or an NMI interrupt from the CPU when the TCNT overflows (Initial value) Bit 5--Timer Enable (TME): Selects whether TCNT runs or is halted. Bit 5 TME 0 1 Description TCNT is initialized to H'00 and halted TCNT counts (Initial value) WDT0 TCSR Bit 4--Reserved Bit: A read operation on this bit always causes a 1 to be read out. Every write operation on this bit is invalidated. WDT1 TCSR Bit 4--Prescaler Select (PSS): This bit is used to select an input clock source for the TCNT of WDT1. See the descriptions of Clock Select 2 to 0 for details. Rev. 6.00 Feb 22, 2005 page 422 of 1484 REJ09B0103-0600 Section 12 Watchdog Timer WDT1 TCSR Bit 4 PSS 0 1 Description The TCNT counts frequency-division clock pulses of the based prescaler (PSM) (Initial value) *-based prescaler The TCNT counts frequency-division clock pulses of the SUB (PSS) Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available only in the U-mask and W-mask versions, but are not available in the other versions. WDT0 TCSR Bit 3--Reserved: A read operation on this bit always causes a 1 to be read out. Every write operation on this bit is invalidated. WDT1 TCSR Bit 3--Reset or NMI (RST/NMI): This bit is used to choose between an internal reset request and an NMI request when the TCNT overflows during the watchdog timer mode. Bit 3 RST/NMI 0 1 Description NMI request Internal reset request (Initial value) Bits 2 to 0--Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources, obtained by dividing the system clock () or subclock* (SUB), for input to TCNT. Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used with the other versions, and in them the PSS bit is reserved. Only 0 should be written to this bit. Rev. 6.00 Feb 22, 2005 page 423 of 1484 REJ09B0103-0600 Section 12 Watchdog Timer WDT0 Input Clock Select Description Bit 2 CKS2 0 Bit 1 CKS1 0 1 1 0 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 Clock Overflow Period*1 (where = 20 MHz) /2*2 (initial value) 25.6 s /64*2 819.2 s *2 /128 1.6 ms /512*2 /2048*2 /8192 *2 /32768*2 /131072*2 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s Notes: 1. An overflow period is the time interval between the start of counting up from H'00 on the TCNT and the occurrence of a TCNT overflow. 2. In the U-mask and W-mask versions, and H8S/2635 Group, in subactive and subsleep modes operates as SUB. Rev. 6.00 Feb 22, 2005 page 424 of 1484 REJ09B0103-0600 Section 12 Watchdog Timer WDT1 Input Clock Select Description Bit 4 PSS*2 0 Bit 2 CKS2 0 Bit 1 CKS1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock /2 (initial value) /64 /128 /512 /2048 /8192 /32768 /131072 SUB/2*2 SUB/4*2 SUB/8*2 SUB/16*2 SUB/32*2 SUB/64*2 SUB/128*2 SUB/256*2 Overflow Period*1 (where = 20 MHz) (where SUB*2 = 32.768 kHz) 25.6 s 819.2 s 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s 15.6 ms 31.3 ms 62.5 ms 125 ms 250 ms 500 ms 1s 2s Notes: 1. An overflow period is the time interval between the start of counting up from H'00 on the TCNT and the occurrence of a TCNT overflow. 2. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used with the other versions, therefore PSS bit is reserved. 0 should be written when writing. Rev. 6.00 Feb 22, 2005 page 425 of 1484 REJ09B0103-0600 Section 12 Watchdog Timer 12.2.3 Bit Reset Control/Status Register (RSTCSR) : 7 WOVF 0 R/(W)* 6 RSTE 0 R/W 5 RSTS 0 R/W 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial value : R/W : Note: * Can only be written with 0 for flag clearing. RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. SER RSTCSR is initialized to H'1F by a reset signal from the reset signal caused by overflows. pin, but not by the WDT internal Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details see section 12.2.4, Notes on Register Access. Bit 7--Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode. Bit 7 WOVF 0 1 Description [Clearing condition] * * [Setting condition] Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer operation (Initial value) Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF Bit 6--Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the H8S/2636 if TCNT overflows during watchdog timer operation. Bit 6 RSTE 0 1 Description Reset signal is not generated if TCNT overflows* Reset signal is generated if TCNT overflows (Initial value) Note: * The modules within the chip are not reset, but TCNT and TCSR within the WDT are reset. Rev. 6.00 Feb 22, 2005 page 426 of 1484 REJ09B0103-0600 Section 12 Watchdog Timer Bit 5--Reset Select (RSTS): Selects the type of internal reset generated if TCNT overflows during watchdog timer operation. For details of the types of reset, see section 4, Exception Handling. Bit 5 RSTS 0 1 Description Reset Do not set (Initial value) Bits 4 to 0--Reserved: Always read as 1 and cannot be modified. 12.2.4 Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction. They cannot be written to with byte instructions. Figure 12-2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the same write address. For a write to TCNT, the upper byte of the written word must contain H'5A and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written word must contain H'A5 and the lower byte must contain the write data. This transfers the write data from the lower byte to TCNT or TCSR. TCNT write 15 Address: H'FF74 H'5A 87 Write data 0 TCSR write 15 Address: H'FF74 H'A5 87 Write data 0 Figure 12-2 Format of Data Written to TCNT and TCSR (WDT0) Rev. 6.00 Feb 22, 2005 page 427 of 1484 REJ09B0103-0600 Section 12 Watchdog Timer Writing to RSTCSR: RSTCSR must be written to by word transfer instruction to address H'FF76. It cannot be written to with byte instructions. Figure 12-3 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF bit differs from that for writing to the RSTE bit. To write 0 to the WOVF bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0, but has no effect on the RSTE bit. To write to the RSTE bit, the upper byte must contain H'5A and the lower byte must contain the write data. This writes the values in bits 6 and 5 of the lower byte into the RSTE bit, but has no effect on the WOVF bit. Writing 0 to WOVF bit 15 Address: H'FF76 H'A5 87 H'00 0 Writing to RSTE bit 15 Address: H'FF76 H'5A 87 Write data 0 Figure 12-3 Format of Data Written to RSTCSR (WDT0) Reading TCNT, TCSR, and RSTCSR (WDT0): These registers are read in the same way as other registers. The read addresses are H'FF74 for TCSR, H'FF75 for TCNT, and H'FF77 for RSTCSR. Rev. 6.00 Feb 22, 2005 page 428 of 1484 REJ09B0103-0600 Section 12 Watchdog Timer 12.3 12.3.1 Operation Watchdog Timer Operation To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and the TME bit to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally by writing H'00) before overflow occurs. This ensures that TCNT does not overflow while the system is operating normally. If TCNT overflows without being rewritten because of a system malfunction or other error, an internal reset is issued, in the case of WDT0, if the RSTE bit in RSTCSR is set to 1. pin occurs at the same time as a reset caused by a If a reset caused by a signal input to the pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. WDT overflow, the In the case of WDT1, the chip is reset, or an NMI interrupt request is generated, for 516 system clock periods (516) (515 or 516 clock periods when the clock source is /SUB* (PSS = 1)). This is illustrated in figure 12-4 (b). An NMI request from the watchdog timer and an interrupt request from the NMI pin are both treated as having the same vector. So, avoid handling an NMI request from the watchdog timer and an interrupt request from the NMI pin at the same time. Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used with the other versions. SER SER Rev. 6.00 Feb 22, 2005 page 429 of 1484 REJ09B0103-0600 Section 12 Watchdog Timer TCNT value Overflow H'FF H'00 WT/IT = 1 TME = 1 Write H'00 to TCNT WOVF = 1 Internal reset is generated Internal reset signal* 518 states Legend: WT/IT: Timer mode select bit TME: Timer enable bit Note: * The internal reset signal is generated only if the RSTE bit is set to 1. Time WT/IT = 1 Write H'00 TME = 1 to TCNT Figure 12-4 (a) WDT0 Watchdog Timer Operation TCNT value Overflow H'FF H'00 WT/IT = 1 TME = 1 Time Write H'00 to TCNT WOVF = 1* Internal reset is generated WT/IT = 1 Write H'00 TME = 1 to TCNT Internal reset signal 515/516 states Legend: WT/IT: Timer mode select bit TME: Timer enable bit Note: * The WOVF bit is set to 1 and then cleared to 0 by an internal reset. Figure 12-4 (b) WDT1 Watchdog Timer Operation Rev. 6.00 Feb 22, 2005 page 430 of 1484 REJ09B0103-0600 Section 12 Watchdog Timer 12.3.2 Interval Timer Operation To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 12-5. This function can be used to generate interrupt requests at regular intervals. TCNT value H'FF Overflow Overflow Overflow Overflow H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI Time Legend: WOVI: Interval timer interrupt request generation Figure 12-5 Interval Timer Operation 12.3.3 Timing of Setting Overflow Flag (OVF) The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 12-6. With WDT1, the OVF bit of the TCSR is set to 1 and a simultaneous NMI interrupt is requested when the TCNT overflows if the NMI request has been chosen in the watchdog timer mode. Rev. 6.00 Feb 22, 2005 page 431 of 1484 REJ09B0103-0600 Section 12 Watchdog Timer TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 12-6 Timing of Setting of OVF 12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) In the WDT0, the WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire chip. Figure 12-7 shows the timing in this case. TCNT Overflow signal (internal signal) WOVF Internal reset signal H'FF H'00 518 states (WDT0) 515/516 states (WDT1) Figure 12-7 Timing of Setting of WOVF Rev. 6.00 Feb 22, 2005 page 432 of 1484 REJ09B0103-0600 Section 12 Watchdog Timer 12.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. If an NMI request has been chosen in the watchdog timer mode, an NMI request is generated when a TCNT overflow occurs. 12.5 12.5.1 Usage Notes Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 12-8 shows this operation. TCNT write cycle T1 T2 Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12-8 Contention between TCNT Write and Increment Rev. 6.00 Feb 22, 2005 page 433 of 1484 REJ09B0103-0600 Section 12 Watchdog Timer 12.5.2 Changing Value of PSS* and CKS2 to CKS0 If bits PSS and CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits PSS* and CKS2 to CKS0. Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used with the other versions. 12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. 12.5.4 Internal Reset in Watchdog Timer Mode The chip is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer operation, but TCNT and TSCR of the WDT are reset. 12.5.5 OVF Flag Clearing in Interval Timer Mode If conflict occurs between OVF flag clearing and OVF flag reading in interval timer mode, the flag may not be cleared by writing 0 to OVF even though the OVF = 1 state has been read. When interval timer interrupts are disabled and the OVF flag is polled, for instance, and there is a possibility of conflict between OVF flag setting and reading, the OVF = 1 state should be read at least twice before writing 0 to OVF in order to clear the flag. Rev. 6.00 Feb 22, 2005 page 434 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Section 13 Serial Communication Interface (SCI) Note: The H8S/2635 Group is not equipped with a DTC. 13.1 Overview The chip is equipped with 3 independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function). 13.1.1 Features SCI features are listed below. * Choice of asynchronous or clocked synchronous serial communication mode Asynchronous mode Serial data communication executed using asynchronous system in which synchronization is achieved character by character Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA) A multiprocessor communication function is provided that enables serial data communication with a number of processors Choice of 12 serial data transfer formats Data length : 7 or 8 bits Stop bit length : 1 or 2 bits Parity : Even, odd, or none Multiprocessor bit : 1 or 0 Receive error detection : Parity, overrun, and framing errors Break detection : Break can be detected by reading the RxD pin level directly in case of a framing error Clocked Synchronous mode Serial data communication synchronized with a clock Serial data communication can be carried out with other chips that have a synchronous communication function Rev. 6.00 Feb 22, 2005 page 435 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) One serial data transfer format Data length : 8 bits Receive error detection : Overrun errors detected * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data * Choice of LSB-first or MSB-first transfer Can be selected regardless of the communication mode* (except in the case of asynchronous mode 7-bit data) Note: * Descriptions in this section refer to LSB-first transfer. * On-chip baud rate generator allows any bit rate to be selected * Choice of serial clock source: internal clock from baud rate generator or external clock from SCK pin * Four interrupt sources Four interrupt sources -- transmit-data-empty, transmit-end, receive-data-full, and receive error -- that can issue requests independently The transmit-data-empty interrupt and receive data full interrupts can activate the data transfer controller (DTC) to execute data transfer * Module stop mode can be set As the initial setting, SCI operation is halted. Register access is enabled by exiting module stop mode Rev. 6.00 Feb 22, 2005 page 436 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) 13.1.2 Block Diagram Figure 13-1 shows a block diagram of the SCI. Bus interface Module data bus Internal data bus RDR TDR RxD RSR TSR SCMR SSR SCR SMR Transmission/ reception control BRR Baud rate generator /4 /16 /64 Clock TxD Parity generation Parity check SCK External clock TEI TXI RXI ERI Legend: RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR: Serial status register SCMR: Smart card mode register BRR: Bit rate register Figure 13-1 Block Diagram of SCI Rev. 6.00 Feb 22, 2005 page 437 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) 13.1.3 Pin Configuration Table 13-1 shows the serial pins for each SCI channel. Table 13-1 SCI Pins Channel 0 Pin Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 1 Serial clock pin 1 Receive data pin 1 Transmit data pin 1 2 Serial clock pin 2 Receive data pin 2 Transmit data pin 2 Symbol* SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 SCK2 RxD2 TxD2 I/O I/O Input Output I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI2 clock input/output SCI2 receive data input SCI2 transmit data output Note: * Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation. Rev. 6.00 Feb 22, 2005 page 438 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) 13.1.4 Register Configuration The SCI has the internal registers shown in table 13-2. These registers are used to specify asynchronous mode or clocked synchronous mode, the data format, and the bit rate, and to control transmitter/receiver. Table 13-2 SCI Registers Channel 0 Name Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Smart card mode register 0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Smart card mode register 1 2 Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit data register 2 Serial status register 2 Receive data register 2 Smart card mode register 2 All Module stop control register B Abbreviation SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 SMR2 BRR2 SCR2 TDR2 SSR2 RDR2 SCMR2 MSTPCRB R/W R/W R/W R/W Initial Value H'00 H'FF H'00 Address*1 H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FDE9 R/W H'FF R/(W)*2 H'84 R R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W H'00 H'F2 H'00 H'FF H'00 H'FF H'00 H'F2 H'00 H'FF H'00 R/(W)*2 H'84 H'FF *2 H'84 R/(W) R R/W R/W H'00 H'F2 H'FF Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. Rev. 6.00 Feb 22, 2005 page 439 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) 13.2 13.2.1 Bit R/W Register Descriptions Receive Shift Register (RSR) : : 7 6 5 4 3 2 1 0 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly read or written to by the CPU. 13.2.2 Bit Receive Data Register (RDR) : 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R Initial value : R/W : RDR is a register that stores received serial data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR where it is stored, and completes the receive operation. After this, RSR is receive-enabled. Since RSR and RDR function as a double buffer in this way, enables continuous receive operations to be performed. RDR is a read-only register, and cannot be written to by the CPU. RDR is initialized to H'00 by a reset, in standby mode, watch mode*, subactive mode*, and subsleep mode* or module stop mode. Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used with the other versions. Rev. 6.00 Feb 22, 2005 page 440 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) 13.2.3 Bit R/W Transmit Shift Register (TSR) : : 7 6 5 4 3 2 1 0 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically. However, data transfer from TDR to TSR is not performed if the TDRE bit in SSR is set to 1. TSR cannot be directly read or written to by the CPU. 13.2.4 Bit Transmit Data Register (TDR) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : R/W : TDR is an 8-bit register that stores data for serial transmission. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts serial transmission. Continuous serial transmission can be carried out by writing the next transmit data to TDR during serial transmission of the data in TSR. TDR can be read or written to by the CPU at all times. TDR is initialized to H'FF by a reset, in standby mode, watch mode*, subactive mode*, and subsleep mode* or module stop mode. Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used with the other versions. Rev. 6.00 Feb 22, 2005 page 441 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) 13.2.5 Bit Serial Mode Register (SMR) : 7 C/) 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : SMR is an 8-bit register used to set the SCI's serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times. SMR is initialized to H'00 by a reset and in hardware standby mode. Bit 7--Communication Mode (C/A): Selects asynchronous mode or clocked synchronous mode as the SCI operating mode. Bit 7 C/A 0 1 Description Asynchronous mode Clocked synchronous mode (Initial value) Bit 6--Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In clocked synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting. Bit 6 CHR 0 1 Description 8-bit data 7-bit data* (Initial value) Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible to choose between LSB-first or MSB-first transfer. Rev. 6.00 Feb 22, 2005 page 442 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Bit 5--Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In clocked synchronous mode with a multiprocessor format, parity bit addition and checking is not performed, regardless of the PE bit setting. Bit 5 PE 0 1 Description Parity bit addition and checking disabled Parity bit addition and checking enabled* (Initial value) Note:* When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Bit 4--Parity Mode (O/E): Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit setting is invalid in clocked synchronous mode, when parity addition and checking is disabled in asynchronous mode, and when a multiprocessor format is used. Bit 4 O/E 0 1 Description Even parity*1 Odd parity*2 (Initial value) Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2 When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. Rev. 6.00 Feb 22, 2005 page 443 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Bit 3--Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bits setting is only valid in asynchronous mode. If clocked synchronous mode is set the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP 0 1 Description 1 stop bit: In transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent (Initial value) 2 stop bits: In transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2--Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in clocked synchronous mode. For details of the multiprocessor communication function, see section 13.3.3, Multiprocessor Communication Function. Bit 2 MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value) Rev. 6.00 Feb 22, 2005 page 444 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Bits 1 and 0--Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from , /4, /16, and /64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 13.2.8, Bit Rate Register (BRR). Bit 1 CKS1 0 1 Bit 0 CKS0 0 1 0 1 Description clock /4 clock /16 clock /64 clock (Initial value) 13.2.6 Bit Serial Control Register (SCR) : 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Initial value : R/W : SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. SCR can be read or written to by the CPU at all times. SCR is initialized to H'00 by a reset and in standby mode. Bit 7--Transmit Interrupt Enable (TIE): Enables or disables transmit data empty interrupt (TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE flag in SSR is set to 1. Bit 7 TIE 0 1 Description Transmit data empty interrupt (TXI) requests disabled* Transmit data empty interrupt (TXI) requests enabled (Initial value) Note:* TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. Rev. 6.00 Feb 22, 2005 page 445 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Bit 6--Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI) request and receive error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1. Bit 6 RIE 0 1 Description Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled* (Initial value) Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Note:* RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0. Bit 5--Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI. Bit 5 TE 0 1 Description Transmission disabled*1 Transmission enabled*2 (Initial value) Notes: 1. The TDRE flag in SSR is fixed at 1. 2. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transfer format before setting the TE bit to 1. Bit 4--Receive Enable (RE): Enables or disables the start of serial reception by the SCI. Bit 4 RE 0 1 Description Reception disabled*1 Reception enabled*2 (Initial value) Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the transfer format before setting the RE bit to 1. Rev. 6.00 Feb 22, 2005 page 446 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Bit 3--Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1. The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE 0 Description Multiprocessor interrupts disabled (normal reception performed) [Clearing conditions] * * 1 When the MPIE bit is cleared to 0 When MPB= 1 data is received (Initial value) Multiprocessor interrupts enabled* Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received. Note: * When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR , is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. Bit 2--Transmit End Interrupt Enable (TEIE): Enables or disables transmit end interrupt (TEI) request generation when there is no valid transmit data in TDR in MSB data transmission. Bit 2 TEIE 0 1 Description Transmit end interrupt (TEI) request disabled* Transmit end interrupt (TEI) request enabled* (Initial value) Note: * TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0. Rev. 6.00 Feb 22, 2005 page 447 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Bits 1 and 0--Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin. The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The CKE0 bit setting is invalid in clocked synchronous mode, and in the case of external clock operation (CKE1 = 1). Note that the SCI's operating mode must be decided using SMR before setting the CKE1 and CKE0 bits. For details of clock source selection, see table 13.9 in section 13.3, Operation. Bit 1 CKE1 0 Bit 0 CKE0 0 Description Asynchronous mode Clocked synchronous mode 1 Asynchronous mode Clocked synchronous mode 1 0 Asynchronous mode Clocked synchronous mode 1 Asynchronous mode Clocked synchronous mode Internal clock/SCK pin functions as I/O port*1 Internal clock/SCK pin functions as serial clock output*1 Internal clock/SCK pin functions as clock output*2 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*3 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*3 External clock/SCK pin functions as serial clock input Notes: 1. Initial value 2. Outputs a clock of the same frequency as the bit rate. 3. Inputs a clock with a frequency 16 times the bit rate. Rev. 6.00 Feb 22, 2005 page 448 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) 13.2.7 Bit Serial Status Register (SSR) : 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Initial value : R/W : Note: * Only 0 can be written, to clear the flag. SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits. SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified. SSR is initialized to H'84 by a reset, in standby mode, watch mode*, subactive mode*, and subsleep mode* or module stop mode. Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used with the other versions. Bit 7--Transmit Data Register Empty (TDRE): Indicates that data has been transferred from TDR to TSR and the next serial data can be written to TDR. Bit 7 TDRE 0 Description [Clearing conditions] * * 1 * * When 0 is written to TDRE after reading TDRE = 1 When the DTC is activated by a TXI interrupt and writes data to TDR (Initial value) When the TE bit in SCR is 0 When data is transferred from TDR to TSR and data can be written to TDR [Setting conditions] Rev. 6.00 Feb 22, 2005 page 449 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Bit 6--Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR. Bit 6 RDRF 0 Description [Clearing conditions] * * 1 * When 0 is written to RDRF after reading RDRF = 1 When the DTC is activated by an RXI interrupt and reads data from RDR When serial reception ends normally and receive data is transferred from RSR to RDR (Initial value) [Setting condition] Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Bit 5--Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5 ORER 0 1 Description [Clearing condition] * * When 0 is written to ORER after reading ORER = 1 When the next serial reception is completed while RDRF = 1*2 [Setting condition] (Initial value)*1 Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. Rev. 6.00 Feb 22, 2005 page 450 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Bit 4--Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4 FER 0 1 Description [Clearing condition] * * When 0 is written to FER after reading FER = 1 When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0*2 [Setting condition] (Initial value)*1 Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. Bit 3--Parity Error (PER): Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. Bit 3 PER 0 1 Description [Clearing condition] * * When 0 is written to PER after reading PER = 1 When, in reception, the number of 1 bits in the receive data plus the parity bit does 2 not match the parity setting (even or odd) specified by the O/E bit in SMR* [Setting condition] (Initial value)*1 Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. Bit 2--Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Rev. 6.00 Feb 22, 2005 page 451 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Bit 2 TEND 0 Description [Clearing conditions] * * 1 * * When 0 is written to TDRE after reading TDRE = 1 When the DMAC or DTC is activated by a TXI interrupt and writes data to TDR (Initial value) When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Setting conditions] Bit 1--Multiprocessor Bit (MPB): When reception is performed using multiprocessor format in asynchronous mode, MPB stores the multiprocessor bit in the receive data. MPB is a read-only bit, and cannot be modified. Bit 1 MPB 0 1 Description [Clearing condition] * * When data with a 0 multiprocessor bit is received When data with a 1 multiprocessor bit is received [Setting condition] (Initial value)* Note: * Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor format. Bit 0--Multiprocessor Bit Transfer (MPBT): When transmission is performed using multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid when multiprocessor format is not used, when not transmitting, and in clocked synchronous mode. Bit 0 MPBT 0 1 Description Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted (Initial value) Rev. 6.00 Feb 22, 2005 page 452 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) 13.2.8 Bit Bit Rate Register (BRR) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : R/W : BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times. BRR is initialized to H'FF by a reset and in standby mode. As baud rate generator control is performed independently for each channel, different values can be set for each channel. Table 13-3 shows sample BRR settings in asynchronous mode, and table 13-4 shows sample BRR settings in clocked synchronous mode. Table 13-3 BRR Settings for Various Bit Rates (Asynchronous Mode) = 4 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -- 0.00 -- = 4.9152 MHz Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 = 5 MHz Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 n 2 1 1 0 0 0 0 0 -- 0 -- N 70 207 103 207 103 51 25 12 -- 3 -- n 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 Rev. 6.00 Feb 22, 2005 page 453 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) = 6 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 = 6.144 MHz Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 = 7.3728 MHz Error (%) -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 = 8 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -- n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 n 2 2 1 1 0 0 0 0 0 0 0 N 108 79 159 79 159 79 39 19 9 5 4 n 2 2 1 1 0 0 0 0 0 -- 0 N 130 95 191 95 191 95 47 23 11 -- 5 n 2 2 1 1 0 0 0 0 0 0 -- N 141 103 207 103 207 103 51 25 12 7 -- = 9.8304 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 = 10 MHz Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 = 12 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.00 -2.34 = 12.288 MHz Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 n 2 2 2 1 1 0 0 0 0 0 0 N 217 159 79 159 79 159 79 39 19 11 9 Rev. 6.00 Feb 22, 2005 page 454 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) = 14 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) -0.17 0.16 0.16 0.16 0.16 0.16 0.16 -0.93 -0.93 0.00 -- = 14.7456 MHz Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 = 16 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 = 17.2032 MHz Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00 n 2 2 2 1 1 0 0 0 0 0 -- N 248 181 90 181 90 181 90 45 22 13 -- n 3 2 2 1 1 0 0 0 0 0 0 N 64 191 95 191 95 191 95 47 23 14 11 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 n 3 2 2 1 1 0 0 0 0 0 0 N 75 223 111 223 111 223 111 55 27 16 13 = 18 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.69 1.02 0.00 -2.34 = 19.6608 MHz Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 = 20 MHz Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 28 17 14 n 3 2 2 1 1 0 0 0 0 0 0 N 86 255 127 255 127 255 127 63 31 19 15 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 Rev. 6.00 Feb 22, 2005 page 455 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Table 13-4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Bit Rate (bit/s) 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M 5M = 4 MHz n -- 2 2 1 1 0 0 0 0 0 0 0 0 N -- 249 124 249 99 199 99 39 19 9 3 1 0* 3 2 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 0 0* -- -- -- 1 1 0 0 0 0 0 0 -- -- -- 249 124 249 99 49 24 9 4 3 3 2 2 1 1 0 0 0 0 0 0 249 124 249 99 199 99 159 79 39 15 7 3 -- -- 2 1 1 0 0 0 0 0 0 0 0 -- -- 124 249 124 199 99 49 19 9 4 1 0* n = 8 MHz N n = 10 MHz N n = 16 MHz N n = 20 MHz N Note: As far as possible, the setting should be made so that the error is no more than 1%. Legend: Blank: Cannot be set. --: Can be set, but there will be a degree of error. *: Continuous transfer is not possible. Rev. 6.00 Feb 22, 2005 page 456 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) The BRR setting is found from the following formulas. Asynchronous mode: N= 64 x 22n-1 x B x 106 - 1 Clocked synchronous mode: N= Where B: N: : n: 8 x 22n-1 x B x 106 - 1 Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SMR Setting n 0 1 2 3 Clock /4 /16 /64 CKS1 0 0 1 1 CKS0 0 1 0 1 The bit rate error in asynchronous mode is found from the following formula: Error (%) = { x 106 (N + 1) x B x 64 x 22n-1 - 1} x 100 Rev. 6.00 Feb 22, 2005 page 457 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Table 13-5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 13-6 and 13-7 show the maximum bit rates with external clock input. Table 13-5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) (MHz) 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 Maximum Bit Rate (bit/s) 125000 153600 156250 187500 192000 230400 250000 307200 312500 375000 384000 437500 460800 500000 537600 562500 614400 625000 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rev. 6.00 Feb 22, 2005 page 458 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Table 13-6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) (MHz) 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 External Input Clock (MHz) 1.0000 1.2288 1.2500 1.5000 1.5360 1.8432 2.0000 2.4576 2.5000 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.9152 5.0000 Maximum Bit Rate (bit/s) 62500 76800 78125 93750 96000 115200 125000 153600 156250 187500 192000 218750 230400 250000 268800 281250 307200 312500 Table 13-7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) (MHz) 4 6 8 10 12 14 16 18 20 External Input Clock (MHz) 0.6667 1.0000 1.3333 1.6667 2.0000 2.3333 2.6667 3.0000 3.3333 Maximum Bit Rate (bit/s) 666666.7 1000000.0 1333333.3 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3 Rev. 6.00 Feb 22, 2005 page 459 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) 13.2.9 Bit Smart Card Mode Register (SCMR) : 3/4 3/4 1 7 3/4 3/4 1 6 3/4 3/4 1 5 3/4 3/4 1 4 3 SDIR 0 R/W 2 SINV 0 R/W 3/4 3/4 1 1 0 SMIF 0 R/W Initial value : R/W : SCMR selects LSB-first or MSB-first by means of bit SDIR. Except in the case of asynchronous mode 7-bit data, LSB-first or MSB-first can be selected regardless of the serial communication mode. The descriptions in this chapter refer to LSB-first transfer. For details of the other bits in SCMR, see section 14.2.1, Smart Card Mode Register (SCMR). SCMR is initialized to H'F2 by a reset and in standby mode. Bits 7 to 4--Reserved: These bits are always read as 1 and cannot be modified. Bit 3--Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. This bit is valid when 8-bit data is used as the transmit/receive format. Bit 3 SDIR 0 1 Description TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value) Rev. 6.00 Feb 22, 2005 page 460 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Bit 2--Smart Card Data Invert (SINV): Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the O/E bit in SMR. Bit 2 SINV 0 1 Description TDR contents are transmitted without modification Receive data is stored in RDR without modification TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form (Initial value) Bit 1--Reserved: This bit is always read as 1 and cannot be modified. Bit 0--Smart Card Interface Mode Select (SMIF): When the smart card interface operates as a normal SCI, 0 should be written in this bit. Bit 0 SMIF 0 1 Description Operates as normal SCI (smart card interface function disabled) Smart card interface function enabled (Initial value) 13.2.10 Module Stop Control Register B (MSTPCRB) MSTPCRB Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : R/W : MSTPCRB is 8-bit readable/writable registers that perform module stop mode control. Setting any of bits MSTPB7 to MSTBP5 to 1 stops SCI0 to SCI2 operating and enter module stop mode on completion of the bus cycle. For details, see section 23A.5, 23B.5, Module Stop Mode. MSTPCRB is initialized to H'FF by a reset and in hardware standby mode. They are not initialized by a manual reset and in software standby mode. Rev. 6.00 Feb 22, 2005 page 461 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Bit 7--Module Stop (MSTPB7): Specifies the SCI0 module stop mode. Bit 7 MSTPB7 0 1 Description SCI0 module stop mode is cleared SCI0 module stop mode is set (Initial value) Bit 6--Module Stop (MSTPB6): Specifies the SCI1 module stop mode. Bit 6 MSTPB6 0 1 Description SCI1 module stop mode is cleared SCI1 module stop mode is set (Initial value) Bit 5--Module Stop (MSTPB5): Specifies the SCI2 module stop mode. Bit 5 MSTPB5 0 1 Description SCI2 module stop mode is cleared SCI2 module stop mode is set (Initial value) Rev. 6.00 Feb 22, 2005 page 462 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) 13.3 13.3.1 Operation Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and clocked synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or clocked synchronous mode and the transmission format is made using SMR as shown in table 13-8. The SCI clock is determined by a combination of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 13-9. Asynchronous Mode * Data length: Choice of 7 or 8 bits * Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) * Detection of framing, parity, and overrun errors, and breaks, during reception * Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used) Clocked Synchronous Mode * Transfer format: Fixed 8-bit data * Detection of overrun errors during reception * Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a serial clock is output off-chip When external clock is selected: The on-chip baud rate generator is not used, and the SCI operates on the input serial clock Rev. 6.00 Feb 22, 2005 page 463 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Table 13-8 SMR Settings and Serial Transfer Format Selection SMR Settings Bit 7 C/A 0 Bit 6 CHR 0 Bit 2 MP 0 Bit 5 PE 0 Bit 3 STOP 0 1 1 0 1 1 0 0 1 1 0 1 0 1 -- -- 1 -- -- 1 -- -- -- 0 1 0 1 -- Clocked 8-bit data synchronous mode No Asynchronous mode (multiprocessor format) 8-bit data Yes No Yes 7-bit data No Mode Asynchronous mode Data Length 8-bit data SCI Transfer Format Multi Processor Bit No Parity Bit No Stop Bit Length 1 bit 2 bits Yes 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 7-bit data 1 bit 2 bits None Table 13-9 SMR and SCR Settings and SCI Clock Source Selection SMR Bit 7 C/A 0 SCR Setting Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 1 0 1 0 1 0 1 0 1 Clocked synchronous mode Internal External Mode Asynchronous mode Clock Source Internal SCI Transmit/Receive Clock SCK Pin Function SCI does not use SCK pin Outputs clock with same frequency as bit rate External Inputs clock with frequency of 16 times the bit rate Outputs serial clock Inputs serial clock Rev. 6.00 Feb 22, 2005 page 464 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) 13.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 13-2 shows the general format for asynchronous serial communication. In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One serial communication character consists of a start bit (low level), followed by data (in LSBfirst order), a parity bit (high or low level), and finally stop bits (high level). In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 Parity bit 1 bit, or none 1 1 1 Stop bit Transmit/receive data 7 or 8 bits 1 or 2 bits One unit of transfer data (character or frame) Figure 13-2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Rev. 6.00 Feb 22, 2005 page 465 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Data Transfer Format: Table 13-10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. Table 13-10 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 -- -- -- -- MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 S Serial Transfer Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data STOP S STOP STOP S P STOP S P STOP STOP S S STOP STOP S P STOP S P STOP STOP S MPB STOP S MPB STOP STOP S MPB STOP S MPB STOP STOP Legend: S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Rev. 6.00 Feb 22, 2005 page 466 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Clock: Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 13-9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 13-3. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 13-3 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) Data Transfer Operations: * SCI initialization (asynchronous mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When an external clock is used the clock should not be stopped during operation, including initialization, since operation is uncertain. Rev. 6.00 Feb 22, 2005 page 467 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Figure 13-4 shows a sample SCI initialization flowchart. Start initialization Clear TE and RE bits in SCR to 0 [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [4] Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR Set value in BRR Wait [2] [3] 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits No Figure 13-4 Sample SCI Initialization Flowchart Rev. 6.00 Feb 22, 2005 page 468 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) * Serial data transmission (asynchronous mode) Figure 13-5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. Initialization Start transmission [1] Read TDRE flag in SSR [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and date is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1 Yes No Break output? Yes Clear DR to 0 and set DDR to 1 [4] Clear TE bit in SCR to 0 Figure 13-5 Sample Serial Transmission Flowchart Rev. 6.00 Feb 22, 2005 page 469 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. A format in which neither a parity bit nor a multiprocessor bit is output can also be selected. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Rev. 6.00 Feb 22, 2005 page 470 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Figure 13-6 shows an example of the operation for transmission in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and request generated TDRE flag cleared to 0 in TXI interrupt service routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 13-6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 6.00 Feb 22, 2005 page 471 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) * Serial data reception (asynchronous mode) Figure 13-7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing and break detection: Read ORER, PER, and If a receive error occurs, read the [2] FER flags in SSR ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error Yes processing, ensure that the PER FER ORER = 1 ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot No Error processing be resumed if any of these flags (Continued on next page) are set to 1. In the case of a framing error, a break can be detected by reading the value of [4] Read RDRF flag in SSR the input port corresponding to the RxD pin. No RDRF= 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] SCI status check and receive data read : Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] No All data received? Yes Clear RE bit in SCR to 0 [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. The RDRF flag is cleared automatically when DTC is activated by an RXI interrupt and the RDR value is read. Figure 13-7 Sample Serial Reception Data Flowchart Rev. 6.00 Feb 22, 2005 page 472 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 No PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 13-7 Sample Serial Reception Data Flowchart (cont) Rev. 6.00 Feb 22, 2005 page 473 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) In serial reception, the SCI operates as described below. [1] The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. [a] Parity check: The SCI checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the O/E bit in SMR. [b] Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the first is checked. [c] Status check: The SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from RSR to RDR. If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error* is detected in the error check, the operation is as shown in table 13-11. Note: * Subsequent receive operations cannot be performed when a receive error has occurred. Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared to 0. [4] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a receive error interrupt (ERI) request is generated. Rev. 6.00 Feb 22, 2005 page 474 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Table 13-11 Receive Errors and Conditions for Occurrence Receive Error Overrun error Abbreviation ORER Occurrence Condition Data Transfer When the next data reception is Receive data is not completed while the RDRF flag transferred from RSR to in SSR is set to 1 RDR When the stop bit is 0 Receive data is transferred from RSR to RDR Framing error Parity error FER PER When the received data differs Receive data is transferred from the parity (even or odd) set from RSR to RDR in SMR Figure 13-8 shows an example of the operation for reception in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 1 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ERI interrupt request generated by framing error 1 frame Figure 13-8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 6.00 Feb 22, 2005 page 475 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) 13.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing transmission lines. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips the data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this way, data communication is carried out among a number of processors. Figure 13-9 shows an example of inter-processor communication using the multiprocessor format. Data Transfer Format: There are four data transfer formats. When the multiprocessor format is specified, the parity bit specification is invalid. For details, see table 13-10. Clock: See the section on asynchronous mode. Rev. 6.00 Feb 22, 2005 page 476 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Transmitting station Serial transmission line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) H'01 (MPB = 1) ID transmission cycle = receiving station specification H'AA (MPB = 0) Data transmission cycle = Data transmission to receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 13-9 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Data Transfer Operations: * Multiprocessor serial data transmission Figure 13-10 shows a sample flowchart for multiprocessor serial data transmission. The following procedure should be used for multiprocessor serial data transmission. Rev. 6.00 Feb 22, 2005 page 477 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Initialization Start transmission [1] [1] SCI initialization: Read TDRE flag in SSR No [2] The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is [3] possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set the port DDR to [4] 1, clear DR to 0, then clear the TE bit in SCR to 0. Clear TDRE flag to 0 All data transmitted? Yes No Read TEND flag in SSR No TEND = 1 Yes Break output? Yes No Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 Figure 13-10 Sample Multiprocessor Serial Transmission Flowchart Rev. 6.00 Feb 22, 2005 page 478 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Multiprocessor bit One multiprocessor bit (MPBT value) is output. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a transmission end interrupt (TEI) request is generated. Rev. 6.00 Feb 22, 2005 page 479 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Figure 13-11 shows an example of SCI operation for transmission using the multiprocessor format. Multiprocessor Stop bit bit D7 0/1 1 1 Start bit 0 D0 D1 Data Start bit 0 D0 D1 Data D7 Multiproces- Stop 1 sor bit bit 0/1 1 Idle state (mark state) TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine 1 frame TXI interrupt request generated TEI interrupt request generated Figure 13-11 Example of SCI Operation in Transmission (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) * Multiprocessor serial data reception Figure 13-12 shows a sample flowchart for multiprocessor serial reception. The following procedure should be used for multiprocessor serial data reception. Rev. 6.00 Feb 22, 2005 page 480 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. Read MPIE bit in SCR Read ORER and FER flags in SSR FER ORER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR [2] Yes [3] FER ORER = 1 No Read RDRF flag in SSR Yes [4] No RDRF = 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 [5] Error processing (Continued on next page) Figure 13-12 Sample Multiprocessor Serial Reception Flowchart Rev. 6.00 Feb 22, 2005 page 481 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 13-12 Sample Multiprocessor Serial Reception Flowchart (cont) Rev. 6.00 Feb 22, 2005 page 482 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Figure 13-13 shows an example of SCI operation for multiprocessor format reception. Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 D1 Data (Data1) MPB D7 0 Stop bit 1 1 1 Idle state (mark state) MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ID1 If not this station's ID, RXI interrupt request is MPIE bit is set to 1 not generated, and RDR again retains its state (a) Data does not match station's ID 1 Start bit Data (ID2) MPB D0 D1 D7 1 Stop bit 1 Start bit 0 D0 Data (Data2) MPB D1 D7 0 Stop bit 1 0 1 Idle state (mark state) MPIE RDRF RDR value ID1 ID2 Data2 MPIE bit set to 1 again MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine Matches this station's ID, so reception continues, and data is received in RXI interrupt service routine (b) Data matches station's ID Figure 13-13 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 6.00 Feb 22, 2005 page 483 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) 13.3.4 Operation in Clocked Synchronous Mode In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 13-14 shows the general format for clocked synchronous serial communication. One unit of transfer data (character or frame) * * Serial clock LSB MSB Serial data Don't care Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don't care Note: * High except in continuous transfer Figure 13-14 Data Format in Synchronous Communication In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. Data confirmation is guaranteed at the rising edge of the serial clock. In clocked serial communication, one character consists of data output starting with the LSB and ending with the MSB. After the MSB is output, the transmission line holds the MSB state. In clocked synchronous mode, the SCI receives data in synchronization with the rising edge of the serial clock. Rev. 6.00 Feb 22, 2005 page 484 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Data Transfer Format: A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Clock: Either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 13-9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. When only receive operations are performed, however, the serial clock is output until an overrun error occurs or the RE bit is cleared to 0. If you want to perform receive operations in units of one character, you should select an external clock as the clock source. Rev. 6.00 Feb 22, 2005 page 485 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Data Transfer Operations: * SCI initialization (clocked synchronous mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. Figure 13-15 shows a sample SCI initialization flowchart. Start initialization [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. [2] Set the data transfer format in SMR and SCMR. Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) Set data transfer format in SMR and SCMR Set value in BRR Wait [1] [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Figure 13-15 Sample SCI Initialization Flowchart Rev. 6.00 Feb 22, 2005 page 486 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) * Serial data transmission (clocked synchronous mode) Figure 13-16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. Initialization Start transmission [1] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. Read TDRE flag in SSR [2] No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1 Yes Clear TE bit in SCR to 0 Figure 13-16 Sample Serial Transmission Flowchart Rev. 6.00 Feb 22, 2005 page 487 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an external clock has been specified, data is output synchronized with the input clock. The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with the MSB (bit 7). [3] The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sent, and the TxD pin maintains its state. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. [4] After completion of serial transmission, the SCK pin is fixed high. Figure 13-17 shows an example of SCI operation in transmission. Rev. 6.00 Feb 22, 2005 page 488 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Transfer direction Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated TXI interrupt Data written to TDR request generated and TDRE flag cleared to 0 in TXI interrupt service routine 1 frame TEI interrupt request generated Figure 13-17 Example of SCI Operation in Transmission * Serial data reception (clocked synchronous mode) Figure 13-18 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. When changing the operating mode from asynchronous to clocked synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible. Rev. 6.00 Feb 22, 2005 page 489 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Read ORER flag in SSR Yes ORER = 1 No [2] [3] Error processing (Continued below) [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. The RDRF flag is cleared automatically when the DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read. Read RDRF flag in SSR [4] No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 Overrun error processing Clear ORER flag in SSR to 0 Figure 13-18 Sample Serial Reception Flowchart Rev. 6.00 Feb 22, 2005 page 490 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) In serial reception, the SCI operates as described below. [1] The SCI performs internal initialization in synchronization with serial clock input or output. [2] The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error is detected in the error check, the operation is as shown in table 13-11. Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. [3] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER flag changes to 1, a receive error interrupt (ERI) request is generated. Figure 13-19 shows an example of SCI operation in reception. Serial clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 13-19 Example of SCI Operation in Reception * Simultaneous serial data transmission and reception (clocked synchronous mode) Figure 13-20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. Rev. 6.00 Feb 22, 2005 page 491 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Initialization Start transmission/reception [1] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error processing: Read ORER flag in SSR Yes [3] Error processing ORER = 1 No If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] [5] Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. Also, the RDRF flag is cleared automatically when the DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read. No All data received? Yes [5] Clear TE and RE bits in SCR to 0 Figure 13-20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations Rev. 6.00 Feb 22, 2005 page 492 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) 13.4 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 13-13 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR. Each kind of interrupt request is sent to the interrupt controller independently. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is performed by the DTC. The DTC cannot be activated by a TEI interrupt request. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DTC to perform data transfer. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC. The DTC cannot be activated by an ERI interrupt request. Table 13-12 SCI Interrupt Sources Interrupt Channel Source Description 0 ERI RXI TXI TEI 1 ERI RXI TXI TEI 2 ERI RXI TXI TEI Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) DTC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Low Priority* High Note: * This table shows the initial state immediately after a reset. Relative priorities among channels can be changed by means of the interrupt controller. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a Rev. 6.00 Feb 22, 2005 page 493 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) TXI interrupt are requested simultaneously, the TXI interrupt may have priority for acceptance, with the result that the TDRE and TEND flags are cleared. Note that the TEI interrupt will not be accepted in this case. 13.5 Usage Notes The following points should be noted when using the SCI. Relation between Writes to TDR and the TDRE Flag The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to TDR. Operation when Multiple Receive Errors Occur Simultaneously If a number of receive errors occur at the same time, the state of the status flags in SSR is as shown in table 13-14. If there is an overrun error, data is not transferred from RSR to RDR, and the receive data is lost. Table 13-13 State of SSR Status Flags and Transfer of Receive Data SSR Status Flags RDRF 1 0 0 1 1 0 1 Notes: ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 X X X Receive Data Transfer RSR to RDR X Receive Error Status Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error : Receive data is transferred from RSR to RDR. X: Receive data is not transferred from RSR to RDR. Rev. 6.00 Feb 22, 2005 page 494 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Break Detection and Processing (Asynchronous Mode Only): When framing error (FER) detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. Sending a Break (Asynchronous Mode Only): The TxD pin has a dual function as an I/O port whose direction (input or output) is determined by DR and DDR. This can be used to send a break. Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced by the value of DR (the pin does not function as the TxD pin until the TE bit is set to 1). Consequently, DDR and DR for the port corresponding to the TxD pin are first set to 1. To send a break during serial transmission, first clear DR to 0, then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only): Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. Receive Data Sampling Timing and Reception Margin in Asynchronous Mode: In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock. This is illustrated in figure 13-21. Rev. 6.00 Feb 22, 2005 page 495 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) 16 clocks 8 clocks 0 Internal basic clock 7 15 0 7 15 0 Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 13-21 Receive Data Sampling Timing in Asynchronous Mode Thus the reception margin in asynchronous mode is given by formula (1) below. M = | (0.5 - 1 2N ) - (L - 0.5) F - | D - 0.5 | (1 + F) | x 100% N ... Formula (1) Where M : Reception margin (%) N : Ratio of bit rate to clock (N = 16) D : Clock duty (D = 0 to 1.0) L : Frame length (L = 9 to 12) F : Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by formula (2) below. When D = 0.5 and F = 0, M = (0.5 - 1 2 x 16 ) x 100% ... Formula (2) = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. Rev. 6.00 Feb 22, 2005 page 496 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Restrictions on Use of DTC* Note: * The DTC is not implemented in the H8S/2635 and H8S/2634. * When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 clock cycles after TDR is updated by the DTC. Misoperation may occur if the transmit clock is input within 4 clocks after TDR is updated (figure 13-22). * When RDR is read by the DTC, be sure to set the activation source to the relevant SCI reception end interrupt (RXI). SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: When operating on an external clock, set t > 4 clocks. Figure 13-22 Example of Clocked Synchronous Transmission by DTC Operation in Case of Mode Transition * Transmission Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. TSR, TDR, and SSR are reset. The output pin states in module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode depend on the port settings, and becomes high-level output after the relevant mode is cleared. If a transition is made during transmission, the data being transmitted will be undefined. When transmitting without changing the transmit mode after the relevant mode is cleared, transmission can be started by setting TE to 1 again, and performing the following sequence: SSR read -> TDR write -> TDRE clearance. To transmit with a different transmit mode after clearing the relevant mode, the procedure must be started again from initialization. Figure 13-23 shows a sample flowchart for mode transition during transmission. Port pin states are shown in figures 13-24 and 13-25. Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a transition from transmission by DTC* transfer to module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. To perform transmission with the DTC* after the relevant mode is cleared, setting TE and TIE to 1 will set the TXI flag and start DTC* transmission. Note: * The DTC is not implemented in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 497 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) * Reception Receive operation should be stopped (by clearing RE to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. RSR, RDR, and SSR are reset. If a transition is made without stopping operation, the data being received will be invalid. To continue receiving without changing the reception mode after the relevant mode is cleared, set RE to 1 before starting reception. To receive with a different receive mode, the procedure must be started again from initialization. Figure 13-26 shows a sample flowchart for mode transition during reception. All data transmitted? Yes Read TEND flag in SSR No [1] TEND = 1 Yes TE = 0 [2] No [1] Data being transmitted is interrupted. After exiting software standby mode, etc., normal CPU transmission is possible by setting TE to 1, reading SSR, writing TDR, and clearing TDRE to 0, but note that if the DTC has been activated, the remaining data in DTCRAM will be transmitted when TE and TIE are set to 1. [2] If TIE and TEIE are set to 1, clear them to 0 in the same way. Transition to software standby mode, etc. Exit from software standby mode, etc. Change operating mode? Yes Initialization No [3] [3] Includes module stop mode, watch mode, subactive mode, and subsleep mode. TE = 1 Figure 13-23 Sample Flowchart for Mode Transition during Transmission Rev. 6.00 Feb 22, 2005 page 498 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Start of transmission End of transmission Transition to software standby Exit from software standby TE bit SCK output pin Port input/output TxD output pin Port input/output Port High output Start SCI TxD output Stop Port input/output Port High output SCI TxD output Figure 13-24 Asynchronous Transmission Using Internal Clock Transition to software standby Exit from software standby Start of transmission End of transmission TE bit SCK output pin Port input/output TxD output pin Port input/output Port Marking output SCI TxD output Last TxD bit held Port input/output Port High output* SCI TxD output Note: * Initialized by software standby. Figure 13-25 Synchronous Transmission Using Internal Clock Rev. 6.00 Feb 22, 2005 page 499 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) RDRF = 1 Yes Read receive data in RDR RE = 0 Transition to software standby mode, etc. Exit from software standby mode, etc. Change operating mode? Yes Initialization No [2] [2] Includes module stop mode, watch mode, subactive mode, and subsleep mode. RE = 1 Figure 13-26 Sample Flowchart for Mode Transition during Reception Rev. 6.00 Feb 22, 2005 page 500 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) Switching from SCK Pin Function to Port Pin Function: * Problem in Operation: When switching the SCK pin function to the output port function (highlevel output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle. 1. End of serial data transmission 2. TE bit = 0 3. C/A bit = 0 ... switchover to port output 4. Occurrence of low-level output (see figure 13-27) Half-cycle low-level output SCK/port 1. End of transmission Data TE C/A CKE1 CKE0 Bit 6 Bit 7 2. TE = 0 4. Low-level output 3. C/A = 0 Figure 13-27 Operation when Switching from SCK Pin Function to Port Pin Function Rev. 6.00 Feb 22, 2005 page 501 of 1484 REJ09B0103-0600 Section 13 Serial Communication Interface (SCI) * Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown. 1. End of serial data transmission 2. TE bit = 0 3. CKE1 bit = 1 4. C/A bit = 0 ... switchover to port output 5. CKE1 bit = 0 High-level output TE SCK/port 1. End of transmission Data TE C/A 3. CKE1 = 1 CKE1 CKE0 5. CKE1 = 0 Bit 6 Bit 7 2. TE = 0 4. C/A = 0 Figure 13-28 Operation when Switching from SCK Pin Function to Port Pin Function (Example of Preventing Low-Level Output) Rev. 6.00 Feb 22, 2005 page 502 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface Section 14 Smart Card Interface Note: The H8S/2635 Group is not equipped with a DTC. 14.1 Overview SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting. 14.1.1 Features Features of the Smart Card interface supported by the chip are as follows. * Asynchronous mode Data length: 8 bits Parity bit generation and checking Transmission of error signal (parity error) in receive mode Error signal detection and automatic data retransmission in transmit mode Direct convention and inverse convention both supported * On-chip baud rate generator allows any bit rate to be selected * Three interrupt sources Three interrupt sources (transmit data empty, receive data full, and transmit/receive error) that can issue requests independently The transmit data empty interrupt and receive data full interrupt can activate the data transfer controller (DTC)* to execute data transfer Note: * The DTC is not implemented in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 503 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface 14.1.2 Block Diagram Figure 14-1 shows a block diagram of the Smart Card interface. Bus interface Module data bus Internal data bus RDR TDR RxD RSR TSR SCMR SSR SCR SMR Transmission/ reception control BRR Baud rate generator /4 /16 /64 Clock TxD Parity generation Parity check SCK TXI RXI ERI Legend: SCMR: Smart Card mode register RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR: Serial status register BRR: Bit rate register Figure 14-1 Block Diagram of Smart Card Interface Rev. 6.00 Feb 22, 2005 page 504 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface 14.1.3 Pin Configuration Table 14-1 shows the Smart Card interface pin configuration. Table 14-1 Smart Card Interface Pins Channel 0 Pin Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 1 Serial clock pin 1 Receive data pin 1 Transmit data pin 1 2 Serial clock pin 2 Receive data pin 2 Transmit data pin 2 Symbol SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 SCK2 RxD2 TxD2 I/O I/O Input Output I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI2 clock input/output SCI2 receive data input SCI2 transmit data output Rev. 6.00 Feb 22, 2005 page 505 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface 14.1.4 Register Configuration Table 14-2 shows the registers used by the Smart Card interface. Details of SMR, BRR, SCR, TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register descriptions in section 13, Serial Communication Interface (SCI). Table 14-2 Smart Card Interface Registers Channel 0 Name Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Smart card mode register 0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Smart card mode register 1 2 Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit data register 2 Serial status register 2 Receive data register 2 Smart card mode register 2 All Module stop control register B Abbreviation SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 SMR2 BRR2 SCR2 TDR2 SSR2 RDR2 SCMR2 MSTPCRB R/W R/W R/W R/W Initial Value H'00 H'FF H'00 Address*1 H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FDE9 R/W H'FF R/(W)*2 H'84 R R/W R/W R/W R/W R/W H'00 H'F2 H'00 H'FF H'00 H'FF *2 H'84 R/(W) R R/W R/W R/W R/W H'00 H'F2 H'00 H'FF H'00 R/W H'FF R/(W)*2 H'84 R R/W R/W H'00 H'F2 H'FF Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. Rev. 6.00 Feb 22, 2005 page 506 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface 14.2 Register Descriptions Registers added with the Smart Card interface and bits for which the function changes are described here. 14.2.1 Bit Smart Card Mode Register (SCMR) : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- 1 -- 0 SMIF 0 R/W Initial value : R/W : SCMR is an 8-bit readable/writable register that selects the Smart Card interface function. SCMR is initialized to H'F2 by a reset and in standby mode. Bits 7 to 4--Reserved: These bits are always read as 1 and cannot be modified. Bit 3--Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3 SDIR 0 1 Description TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value) Rev. 6.00 Feb 22, 2005 page 507 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface Bit 2--Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the SDIR bit for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 14.3.4, Register Settings. Bit 2 SINV 0 1 Description TDR contents are transmitted as they are Receive data is stored as it is in RDR TDR contents are inverted before being transmitted Receive data is stored in inverted form in RDR (Initial value) Bit 1--Reserved: This bit is always read as 1 and cannot be modified. Bit 0--Smart Card Interface Mode Select (SMIF): Enables or disables the Smart Card interface function. Bit 0 SMIF 0 1 Description Smart Card interface function is disabled Smart Card interface function is enabled (Initial value) Rev. 6.00 Feb 22, 2005 page 508 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface 14.2.2 Bit Serial Status Register (SSR) : 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Initial value : R/W : Note: * Only 0 can be written, to clear these flags. Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting conditions for bit 2, TEND, are also different. Bits 7 to 5--Operate in the same way as for the normal SCI. For details, see section 13.2.7, Serial Status Register (SSR). Bit 4--Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the error signal sent back from the receiving end in transmission. Framing errors are not detected in Smart Card interface mode. Bit 4 ERS 0 Description Normal reception, with no error signal [Clearing conditions] * * 1 Upon reset, and in standby mode or module stop mode When 0 is written to ERS after reading ERS = 1 (Initial value) Error signal sent from receiver indicating detection of parity error [Setting condition] * When the Low level of the error signal is sampled Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state. Rev. 6.00 Feb 22, 2005 page 509 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface Bits 3 to 0--Operate in the same way as for the normal SCI. For details, see section 13.2.7, Serial Status Register (SSR). However, the setting conditions for the TEND bit, are as shown below. Bit 2 TEND 0 Description Transmission is in progress [Clearing conditions] * * 1 When 0 is written to TDRE after reading TDRE = 1 When the DTC is activated by a TXI interrupt and write data to TDR (Initial value) Transmission has ended [Setting conditions] * * * * * * Upon reset, and in standby mode or module stop mode When the TE bit in SCR is 0 and the ERS bit is also 0 When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 0 When TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 1 When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 0 When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 1 Note: etu: Elementary Time Unit (time for transfer of 1 bit) Rev. 6.00 Feb 22, 2005 page 510 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface 14.2.3 Bit Serial Mode Register (SMR) : 7 GM 0 R/W 6 BLK 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 BCP1 0 R/W 2 BCP0 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : Note: When the smart card interface is used, be sure to make the 1 setting shown for bit 5. The function of bits 7, 6, 3, and 2 of SMR changes in Smart Card interface mode. Bit 7--GSM Mode (GM): Sets the smart card interface function to GSM mode. This bit is cleared to 0 when the normal smart card interface is used. In GSM mode, this bit is set to 1, the timing of setting of the TEND flag that indicates transmission completion is advanced and clock output control mode addition is performed. The contents of the clock output control mode addition are specified by bits 1 and 0 of the serial control register (SCR). Bit 7 GM 0 Description Normal smart card interface mode operation * * 1 * * (Initial value) TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit Clock output ON/OFF control only TEND flag generation 11.0 etu after beginning of start bit High/Low fixing control possible in addition to clock output ON/OFF control (set by SCR) GSM mode smart card interface mode operation Note: etu: Elementary Time Unit (time for transfer of 1 bit) Rev. 6.00 Feb 22, 2005 page 511 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface Bit 6--Block Transfer Mode (BLK): Selects block transfer mode. Bit 6 BLK 0 Description Normal Smart Card interface mode operation * * * 1 * * * Error signal transmission/detection and automatic data retransmission performed TXI interrupt generated by TEND flag TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode) Error signal transmission/detection and automatic data retransmission not performed TXI interrupt generated by TDRE flag TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode) Block transfer mode operation Note: etu: Elementary Time Unit (time for transfer of 1 bit) Bits 3 and 2--Basic Clock Pulse 1 and 2 (BCP1, BCP0): These bits specify the number of basic clock periods in a 1-bit transfer interval on the Smart Card interface. Bit 3 BCP1 0 1 Bit 2 BCP0 0 1 0 1 Description 32 clock periods 64 clock periods 372 clock periods 256 clock periods (Initial value) Bits 5, 4, 1, and 0: Operate in the same way as for the normal SCI. For details, see section 13.2.5, Serial Mode Register (SMR). Rev. 6.00 Feb 22, 2005 page 512 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface 14.2.4 Bit Serial Control Register (SCR) : 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Initial value : R/W : In smart card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial mode register (SMR) is set to 1. Bits 7 to 2--Operate in the same way as for the normal SCI. For details, see section 13.2.6, Serial Control Register (SCR). Bits 1 and 0--Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. In smart card interface mode, in addition to the normal switching between clock output enabling and disabling, the clock output can be specified as to be fixed high or low. SCMR SMIF 0 1 1 1 1 1 1 SMR C/A, GM See the SCI 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 Operates as port I/O pin Outputs clock as SCK output pin Operates as SCK output pin, with output fixed low Outputs clock as SCK output pin Operates as SCK output pin, with output fixed high Outputs clock as SCK output pin SCR Setting CKE1 CKE0 SCK Pin Function Rev. 6.00 Feb 22, 2005 page 513 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface 14.3 14.3.1 Operation Overview The main functions of the Smart Card interface are as follows. * One frame consists of 8-bit data plus a parity bit. * In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of 1 bit) is left between the end of the parity bit and the start of the next frame. * If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. * If the error signal is sampled during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer (except in block transfer mode). * Only asynchronous communication is supported; there is no clocked synchronous communication function. Note: etu: Elementary time unit (time for transfer of 1 bit) 14.3.2 Pin Connections Figure 14-2 shows a schematic diagram of Smart Card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected with the LSI pin. The data transmission line should be pulled up to the VCC power supply with a resistor. When the clock generated on the Smart Card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock. LSI port output is used as the reset signal. Other pins must normally be connected to the power supply or ground. Rev. 6.00 Feb 22, 2005 page 514 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface VCC TxD I/O RxD SCK Rx (port) Chip Connected equipment Data line Clock line Reset line CLK RST IC card Figure 14-2 Schematic Diagram of Smart Card Interface Pin Connections Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. Rev. 6.00 Feb 22, 2005 page 515 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface 14.3.3 Data Format Normal Transfer Mode: Figure 14-3 shows the normal Smart Card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. If an error signal is sampled during transmission, the same data is retransmitted. When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transmitting station output When a parity error occurs Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Transmitting station output Receiving station output Start bit Data bits Parity bit Error signal Legend: Ds: D0 to D7: Dp: DE: Figure 14-3 Normal Smart Card Interface Data Format The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). [3] With the Smart Card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. Rev. 6.00 Feb 22, 2005 page 516 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface [4] The receiving station carries out a parity check. If there is no parity error and the data is received normally, the receiving station waits for reception of the next data. If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. [5] If the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. If it does receive an error signal, however, it returns to step [2] and retransmits the erroneous data. Block Transfer Mode: The operation sequence in block transfer mode is as follows. [1] When the data line in not in use it is in the high-impedance state, and is fixed high with a pullup resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). [3] With the Smart Card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. [4] After reception, a parity error check is carried out, but an error signal is not output even if an error has occurred. When an error occurs reception cannot be continued, so the error flag should be cleared to 0 before the parity bit of the next frame is received. [5] The transmitting station proceeds to transmit the next data frame. Rev. 6.00 Feb 22, 2005 page 517 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface 14.3.4 Register Settings Table 14-3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 14-3 Smart Card Interface Register Settings Bit Register SMR BRR SCR TDR SSR RDR SCMR Bit 7 GM BRR7 TIE TDR7 TDRE RDR7 -- Bit 6 BLK BRR6 RIE TDR6 RDRF RDR6 -- Bit 5 1 BRR5 TE TDR5 ORER RDR5 -- Bit 4 O/E BRR4 RE TDR4 ERS RDR4 -- Bit 3 BCP1 BRR3 0 TDR3 PER RDR3 SDIR Bit 2 BCP0 BRR2 0 TDR2 TEND RDR2 SINV Bit 1 CKS1 BRR1 CKE1* TDR1 0 RDR1 -- Bit 0 CKS0 BRR0 CKE0 TDR0 0 RDR0 SMIF Notes: --: Unused bit. *: The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0. SMR Setting: The GM bit is cleared to 0 in normal smart card interface mode, and set to 1 in GSM mode. The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. Bits BCP1 and BCP0 select the number of basic clock periods in a 1-bit transfer interval. For details, see section 14.3.5, Clock. The BLK bit is cleared to 0 in normal smart card interface mode, and set to 1 in block transfer mode. BRR Setting: BRR is used to set the bit rate. See section 14.3.5, Clock, for the method of calculating the value to be set. SCR Setting: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI. For details, see section 13, Serial Communication Interface (SCI). Bits CKE1 and CKE0 specify the clock output. When the GM bit in SMR is cleared to 0, set these bits to B'00 if a clock is not to be output, or to B'01 if a clock is to be output. When the GM bit in SMR is set to 1, clock output is performed. The clock output can also be fixed high or low. Rev. 6.00 Feb 22, 2005 page 518 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface Smart Card Mode Register (SCMR) Setting: The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SMIF bit is set to 1 in the case of the Smart Card interface. Examples of register settings and the waveform of the start character are shown below for the two types of IC card (direct convention and inverse convention). * Direct convention (SDIR = SINV = O/E = 0) (Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) State With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. The parity bit is 1 since even parity is stipulated for the Smart Card. * Inverse convention (SDIR = SINV = O/E = 1) (Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) State With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. The parity bit is 0, corresponding to state Z, since even parity is stipulated for the Smart Card. With the H8S/2636, H8S/2638, H8S/2639, and H8S/2630 inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SMR is set to odd parity mode (the same applies to both transmission and reception). Rev. 6.00 Feb 22, 2005 page 519 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface 14.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1, CKS0, BCP1 and BCP0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 14-5 shows some sample bit rates. If clock output is selected by setting CKE0 to 1, a clock is output from the SCK pin. The clock frequency is determined by the bit rate and the setting of bits BCP1 and BCP0. B= Sx2 2n+1 x (N + 1) x 106 Where: N = Value set in BRR (0 N 255) B = Bit rate (bit/s) = Operating frequency (MHz) n = See table 14-4 S = Number of internal clocks in 1-bit period, set by BCP1 and BCP0 Table 14-4 Correspondence between n and CKS1, CKS0 n 0 1 2 3 1 CKS1 0 CKS0 0 1 0 1 Table 14-5 Examples of Bit Rate B (bit/s) for Various BRR Settings (When n = 0 and S = 372) (MHz) N 0 1 2 10.00 13441 6720 4480 10.714 14400 7200 4800 13.00 17473 8737 5824 14.285 19200 9600 6400 16.00 21505 10753 7168 18.00 24194 12097 8065 20.00 26882 13441 8961 Note: Bit rates are rounded to the nearest whole number. Rev. 6.00 Feb 22, 2005 page 520 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface The method of calculating the value to be set in the bit rate register (BRR) from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 N 255, and the smaller error is specified. N= Sx2 2n+1 xB x 106 - 1 Table 14-6 Examples of BRR Settings for Bit Rate B (bit/s) (When n = 0 and S = 372) (MHz) 7.1424 bit/s 9600 N 0 Error 0.00 N 1 10.00 Error 30 10.7136 N 1 Error 25 N 1 13.00 Error 8.99 14.2848 N 1 Error 0.00 N 1 16.00 Error 12.01 N 2 18.00 Error 15.99 N 2 20.00 Error 6.60 Note: A blank means no setting is available. Table 14-7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372) (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 Maximum Bit Rate (bit/s) 9600 13441 14400 17473 19200 21505 24194 26882 N 0 0 0 0 0 0 0 0 n 0 0 0 0 0 0 0 0 The bit rate error is given by the following formula: Error (%) = ( Sx2 2n+1 x B x (N + 1) x 106 - 1) x 100 Rev. 6.00 Feb 22, 2005 page 521 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface 14.3.6 Data Transfer Operations Initialization: Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0. [3] Set the GM, BLK, O/E, BCP1, BCP0, CKS1, CKS0 bits in SMR. Set the PE bit to 1. [4] Set the SMIF, SDIR, and SINV bits in SCMR. When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins, and are placed in the high-impedance state. [5] Set the value corresponding to the bit rate in BRR. [6] Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. [7] Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. Rev. 6.00 Feb 22, 2005 page 522 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface Serial Data Transmission (Except Block Transfer Mode): As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 14-4 shows a flowchart for transmitting, and figure 14-5 shows the relation between a transmit operation and the internal registers. [1] Perform Smart Card interface mode initialization as described above in initialization. [2] Check that the ERS error flag in SSR is cleared to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the TEND flag in SSR is set to 1. [4] Write the transmit data to TDR, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is cleared to 0. [5] When transmitting data continuously, go back to step [2]. [6] To end transmission, clear the TE bit to 0. With the above processing, interrupt servicing or data transfer by the DTC is possible. If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a transmit data empty interrupt (TXI) request will be generated. If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a transfer error interrupt (ERI) request will be generated. The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag set timing is shown in figure 14-6. If the DTC* is activated by a TXI request, the number of bytes set in the DTC* can be transmitted automatically, including automatic retransmission. For details, see Interrupt Operation and Data Transfer Operation by DTC below. Notes: For block transfer mode, see section 13.3.2, Operation in Asynchronous Mode. * The DTC is not implemented in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 523 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface Start Initialization Start transmission ERS = 0? Yes No Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit to 0 End Figure 14-4 Example of Transmission Processing Flow Rev. 6.00 Feb 22, 2005 page 524 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface TDR (1) Data write (2) Transfer from TDR to TSR (3) Serial data output Data 1 Data 1 Data 1 TSR (shift register) Data 1 ; Data remains in TDR Data 1 I/O signal line output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has been completed. Figure 14-5 Relation Between Transmit Operation and Internal Registers I/O data TXI (TEND interrupt) When GM = 0 Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Guard time 12.5 etu When GM = 1 11.0 etu Legend: Ds: D0 to D7: Dp: DE: Start bit Data bits Parity bit Error signal Note: etu: Elementary Time Unit (time for transfer of 1 bit) Figure 14-6 TEND Flag Generation Timing in Transmission Operation Rev. 6.00 Feb 22, 2005 page 525 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface Serial Data Reception (Except Block Transfer Mode): Data reception in Smart Card mode uses the same processing procedure as for the normal SCI. Figure 14-7 shows an example of the transmission processing flow. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0. If either is set, perform the appropriate receive error processing, then clear both the ORER and the PER flag to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the RDRF flag is set to 1. [4] Read the receive data from RDR. [5] When receiving data continuously, clear the RDRF flag to 0 and go back to step [2]. [6] To end reception, clear the RE bit to 0. Start Initialization Start reception ORER = 0 and PER = 0 Yes No No Error processing RDRF = 1? Yes Read RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit to 0 Figure 14-7 Example of Reception Processing Flow Rev. 6.00 Feb 22, 2005 page 526 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface With the above processing, interrupt servicing or data transfer by the DTC* is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transfer error interrupt (ERI) request will be generated. If the DTC* is activated by an RXI request, the receive data in which the error occurred is skipped, and only the number of bytes of receive data set in the DTC* are transferred. For details, see Interrupt Operation and Data Transfer Operation by DTC* followings. If a parity error occurs during reception and the PER is set to 1, the received data is still transferred to RDR, and therefore this data can be read. Note: For block transfer mode, see section 13.3.2, Operation in Asynchronous Mode. * The DTC is not implemented in the H8S/2635 and H8S/2634. Mode Switching Operation: When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE bit to 0 and setting TE bit to 1. The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed. When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE bit to 0 and setting RE bit to 1. The TEND flag can be used to check that the transmit operation has been completed. Fixing Clock Output Level: When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 14-8 shows the timing for fixing the clock output level. In this example, GSM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled. Specified pulse width Specified pulse width SCK SCR write (CKE0 = 0) SCR write (CKE0 = 1) Figure 14-8 Timing for Fixing Clock Output Level Rev. 6.00 Feb 22, 2005 page 527 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface Interrupt Operation (Except Block Transfer Mode): There are three interrupt sources in smart card interface mode: transmit data empty interrupt (TXI) requests, transfer error interrupt (ERI) requests, and receive data full interrupt (RXI) requests. The transmit end interrupt (TEI) request is not used in this mode. When the TEND flag in SSR is set to 1, a TXI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated. The relationship between the operating states and interrupt sources is shown in table 14-8. Note: For block transfer mode, see section 13.4, SCI Interrupts. Table 14-8 Smart Card Mode Operating States and Interrupt Sources Operating State Transmit Mode Normal operation Error Receive Mode Normal operation Error Flag TEND ERS RDRF PER, ORER Enable Bit TIE RIE RIE RIE Interrupt Source TXI ERI RXI ERI DTC Activation Possible Not possible Possible Not possible Data Transfer Operation by DTC*: In smart card mode, as with the normal SCI, transfer can be carried out using the DTC. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is designated beforehand as a DTC activation source, the DTC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE and TEND flags are automatically cleared to 0 when data transfer is performed by the DTC. In the event of an error, the SCI retransmits the same data automatically. During this period, TEND remains cleared to 0 and the DTC is not activated. Therefore, the SCI and DTC will automatically transmit the specified number of bytes, including retransmission in the event of an error. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. When performing transfer using the DTC, it is essential to set and enable the DTC before carrying out SCI setting. For details of the DTC setting procedures, see section 8, Data Transfer Controller (DTC). Rev. 6.00 Feb 22, 2005 page 528 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DTC activation source, the DTC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DTC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared. Notes: For block transfer mode, see section 13.4, SCI Interrupts. * The DTC is not implemented in the H8S/2635 and H8S/2634. 14.3.7 Operation in GSM Mode Switching the Mode: When switching between smart card interface mode and software standby mode, the following switching procedure should be followed in order to maintain the clock duty. * When changing from smart card interface mode to software standby mode [1] Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode. [2] Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive operation. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. [3] Write 0 to the CKE0 bit in SCR to halt the clock. [4] Wait for one serial clock period. During this interval, clock output is fixed at the specified level, with the duty preserved. [5] Make the transition to the software standby state. * When returning to smart card interface mode from software standby mode [6] Exit the software standby state. [7] Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the normal duty. Rev. 6.00 Feb 22, 2005 page 529 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface Normal operation Software standby Normal operation [1] [2] [3] [4] [5] [6] [7] Figure 14-9 Clock Halt and Restart Procedure Powering On: To secure the clock duty from power-on, the following switching procedure should be followed. [1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. [2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR. [3] Set SMR and SCMR, and switch to smart card mode operation. [4] Set the CKE0 bit in SCR to 1 to start clock output. 14.3.8 Operation in Block Transfer Mode Operation in block transfer mode is the same as in SCI asynchronous mode, except for the following points. For details, see section 13.3.2, Operation in Asynchronous Mode. Data Format: The data format is 8 bits with parity. There is no stop bit, but there is a 2-bit (1-bit or more in reception) error guard time. Also, except during transmission (with start bit, data bits, and parity bit), the transmission pins go to the high-impedance state, so the signal lines must be fixed high with a pull-up resistor. Transmit/Receive Clock: Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock. The number of basic clock periods in a 1-bit transfer interval can be set to 32, 64, 372, or 256 with bits BCP1 and BCP0. For details, see section 14.3.5, Clock. ERS (FER) Flag: As with the normal Smart Card interface, the ERS flag indicates the error signal status, but since error signal transmission and reception is not performed, this flag is always cleared to 0. Rev. 6.00 Feb 22, 2005 page 530 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface 14.4 Usage Notes The following points should be noted when using the SCI as a Smart Card interface. Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode: In Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, or 256 times the transfer rate (as determined by bits BCP1 and BCP0). In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock. Figure 14-10 shows the receive data sampling timing when using a clock of 372 times the transfer rate. 372 clocks 186 clocks 0 185 371 0 185 371 0 Internal basic clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 14-10 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Transfer Rate) Rev. 6.00 Feb 22, 2005 page 531 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface Thus the reception margin in asynchronous mode is given by the following formula. Formula for reception margin in smart card interface mode M = (0.5 - ) - (L - 0.5) F - 1 2N D - 0.5 N (1 + F) x 100% Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 32, 64, 372, and 256) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin formula is as follows. When D = 0.5 and F = 0, M = (0.5 - 1/2 x 372) x 100% = 49.866% Rev. 6.00 Feb 22, 2005 page 532 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface Retransfer Operations (Except Block Transfer Mode): Retransfer operations are performed by the SCI in receive mode and transmit mode as described below. * Retransfer operation when SCI is in receive mode Figure 14-11 illustrates the retransfer operation when the SCI is in receive mode. [1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [2] The RDRF bit in SSR is not set for a frame in which an error has occurred. [3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1. [4] If no error is found when the received parity bit is checked, the receive operation is judged to have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is generated. If DTC* data transfer by an RXI source is enabled, the contents of RDR can be read automatically. When the RDR data is read by the DTC*, the RDRF flag is automatically cleared to 0. [5] When a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission. Note: * The DTC is not implemented in the H8S/2635 and H8S/2634. Transfer frame n + 1 nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF [2] PER [1] Retransferred frame (DE) Ds D0 D1 D2 D3 D4 Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp [4] [3] Figure 14-11 Retransfer Operation in SCI Receive Mode * Retransfer operation when SCI is in transmit mode Figure 14-12 illustrates the retransfer operation when the SCI is in transmit mode. [6] If an error signal is sent back from the receiving end after transmission of one frame is completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI Rev. 6.00 Feb 22, 2005 page 533 of 1484 REJ09B0103-0600 Section 14 Smart Card Interface interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality is received. [8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set. [9] If an error signal is not sent back from the receiving end, transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt request is generated. If data transfer by the DTC* by means of the TXI source is enabled, the next data can be written to TDR automatically. When data is written to TDR by the DTC*, the TDRE bit is automatically cleared to 0. Note: * The DTC is not implemented in the H8S/2635 and H8S/2634. Transfer frame n + 1 (DE) Ds D0 D1 D2 D3 D4 nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE TDRE Transfer to TSR from TDR TEND [7] FER/ERS [6] Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transfer to TSR from TDR Transfer to TSR from TDR [9] [8] Figure 14-12 Retransfer Operation in SCI Transmit Mode Rev. 6.00 Feb 22, 2005 page 534 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) A two-channel I2C bus interface is available as an option in the H8S/2638, H8S/2639, and H8S/2630 (the product equipped with the I2C bus interface is the W-mask version). Observe the following notes when using this option. A "W" is added to the part number in products in which this optional function is used. Examples: HD64F2638WF* Note: * When the optional function is used in a U-mask version, "U" is replaced with "W". Example: HD64F2638UF HD64F2638WF 15.1 Overview A two-channel I2C bus interface is available for the H8S/2638, H8S/2639, and H8S/2630 as an option. The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. Each I2C bus interface channel uses only one data line (SDA) and one clock line (SCL) to transfer data, saving board and connector space. 15.1.1 Features * Selection of addressing format or non-addressing format I2C bus format: addressing format with acknowledge bit, for master/slave operation Serial format: non-addressing format without acknowledge bit, for master operation only * Conforms to Philips I2C bus interface (I2C bus format) * Two ways of setting slave address (I2C bus format) * Start and stop conditions generated automatically in master mode (I2C bus format) * Selection of acknowledge output levels when receiving (I2C bus format) * Automatic loading of acknowledge bit when transmitting (I2C bus format) * Wait function in master mode (I2C bus format) A wait can be inserted by driving the SCL pin low after data transfer, excluding acknowledgement. The wait can be cleared by clearing the interrupt flag. Rev. 6.00 Feb 22, 2005 page 535 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) * Wait function in slave mode (I2C bus format) A wait request can be generated by driving the SCL pin low after data transfer, excluding acknowledgement. The wait request is cleared when the next transfer becomes possible. * Three interrupt sources Data transfer end (including transmission mode transition with I2C bus format and address reception after loss of master arbitration) Address match: when any slave address matches or the general call address is received in slave receive mode (I2C bus format) Stop condition detection * Selection of 16 internal clocks (in master mode) * Direct bus drive (with SCL and SDA pins) Two pins--P35/SCL0 and P34/SDA0--(normally NMOS push-pull outputs) function as NMOS open-drain outputs when the bus drive function is selected. Two pins--P33/SCL1 and P32/SDA1--(normally CMOS pins) function as NMOS-only outputs when the bus drive function is selected. 15.1.2 Block Diagram Figure 15-1 shows a block diagram of the I2C bus interface. Figure 15-2 shows an example of I/O pin connections to external circuits. Channel 0 I/O pins are NMOS open drains, and it is possible to apply voltages in excess of the power supply (VCC) voltage for this LSI. Set the upper limit of voltage applied to the power supply (VCC) power supply range + 0.3 V, i.e. 5.8 V. Channel 1 I/O pins are driven solely by NMOS, so in terms of appearance they carry out the same operations as an NMOS open drain. However, the voltage which can be applied to the I/O pins depends on the voltage of the power supply (VCC) of this LSI. Rev. 6.00 Feb 22, 2005 page 536 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) SCL PS ICCR Clock control Noise canceler Bus state decision circuit Arbitration decision circuit ICMR ICSR ICDRT SDA Output data control circuit ICDRS ICDRR Noise canceler Address comparator SAR, SARX Legend: ICCR: I2C bus control register ICMR: I2C bus mode register ICSR: I2C bus status register ICDR: I2C bus data register SAR: Slave address register SARX: Second slave address register X PS: Prescaler Interrupt generator Interrupt request Figure 15-1 Block Diagram of I2C Bus Interface Rev. 6.00 Feb 22, 2005 page 537 of 1484 REJ09B0103-0600 Internal data bus Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) VCC VCC SCL SCLin SCLout SDA SCL SDA SDAin SDAout (Master) Chip SCL SDA SCLin SCLout SCLin SCLout SDAin SDAout (Slave 1) SDAin SDAout (Slave 2) Figure 15-2 I2C Bus Interface Connections (Example: The Chip as Master) 15.1.3 Input/Output Pins Table 15-1 summarizes the input/output pins used by the I2C bus interface. Table 15-1 I2C Bus Interface Pins Channel 0 1 Name Serial clock Serial data Serial clock Serial data Abbreviation SCL0 SDA0 SCL1 SDA1 I/O I/O I/O I/O I/O Function IIC0 serial clock input/output IIC0 serial data input/output IIC1 serial clock input/output IIC1 serial data input/output Note: In the text, the channel subscript is omitted, and only SCL and SDA are used. Rev. 6.00 Feb 22, 2005 page 538 of 1484 REJ09B0103-0600 SCL SDA Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) 15.1.4 Register Configuration Table 15-2 summarizes the registers of the I2C bus interface. Table 15-2 Register Configuration Channel 0 Name I2C bus control register I C bus status register I2C bus data register I2C bus mode register Slave address register Second slave address register 1 I2C bus control register I2C bus status register I C bus data register I2C bus mode register Slave address register Second slave address register Common Serial control register X DDC switch register Module stop control register B 2 2 Abbreviation ICCR0 ICSR0 ICDR0 ICMR0 SAR0 SARX0 ICCR1 ICSR1 ICDR1 ICMR1 SAR1 SARX1 SCRX DDCSWR MSTPCRB R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'01 H'00 -- H'00 H'00 H'01 H'01 H'00 -- H'00 H'00 H'01 H'08 H'0F H'FF Address*1 H'FF78*3 H'FF79*3 H'FF7E*2*3 H'FF7F*2*3 H'FF7F*2*3 H'FF7E*2*3 H'FF80*3 H'FF81*3 H'FF86*2*3 H'FF87*2*3 H'FF87*2*3 H'FF86*2*3 H'FDB4 H'FDB5 H'FDE9 Notes: 1. Lower 16 bits of the address. 2. The register that can be written or read depends on the ICE bit in the I2C bus control 2 register. The slave address register can be accessed when ICE = 0, and the I C bus mode register can be accessed when ICE = 1. 3. The I2C bus interface registers are assigned to the same addresses as other registers. Register selection is performed by means of the IICE bit in the serial control register X (SCRX). Rev. 6.00 Feb 22, 2005 page 539 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) 15.2 15.2.1 Bit Register Descriptions I2C Bus Data Register (ICDR) : 7 ICDR7 6 ICDR6 5 ICDR5 4 ICDR4 3 ICDR3 2 ICDR2 1 ICDR1 0 ICDR0 Initial value : R/W : 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 R/W R/W R/W R/W R/W R/W R/W R/W * ICDRR Bit : 7 6 5 4 3 2 1 0 ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0 Initial value : R/W : 3/4 R 3/4 R 3/4 R 3/4 R 3/4 R 3/4 R 3/4 R 3/4 R * ICDRS Bit : 7 6 5 4 3 2 1 0 ICDRS7 ICDRS6 ICDRR5 ICDRS4 ICDRS3 ICDRS2 ICDRS1 ICDRS0 Initial value : R/W : 3/4 3/4 7 3/4 3/4 6 3/4 3/4 5 3/4 3/4 4 3/4 3/4 3 3/4 3/4 2 3/4 3/4 1 3/4 3/4 0 * ICDRT Bit : ICDRT7 ICDRT6 ICDRT5 ICDRT4 ICDRT3 ICDRT2 ICDRT1 ICDRT0 Initial value : R/W : 3/4 W 3/4 W 3/4 W 3/4 W 3/4 W 3/4 W 3/4 W 3/4 W * TDRE, RDRF (internal flags) Bit Initial value R/W : : : 3/4 TDRE 3/4 RDRF 3/4 0 3/4 0 Rev. 6.00 Feb 22, 2005 page 540 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is divided internally into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS cannot be read or written by the CPU, ICDRR is read-only, and ICDRT is write-only. Data transfers among the three registers are performed automatically in coordination with changes in the bus state, and affect the status of internal flags such as TDRE and RDRF. If IIC is in transmit mode and the next data is in ICDRT (the TDRE flag is 0) following transmission/reception of one frame of data using ICDRS, data is transferred automatically from ICDRT to ICDRS. If IIC is in receive mode and no previous data remains in ICDRR (the RDRF flag is 0) following transmission/reception of one frame of data using ICDRS, data is transferred automatically from ICDRS to ICDRR. If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1. ICDR is assigned to the same address as SARX, and can be written and read only when the ICE bit is set to 1 in ICCR. The value of ICDR is undefined after a reset. The TDRE and RDRF flags are set and cleared under the conditions shown below. Setting the TDRE and RDRF flags affects the status of the interrupt flags. Rev. 6.00 Feb 22, 2005 page 541 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) TDRE 0 Description The next transmit data is in ICDR (ICDRT), or transmission cannot be started [Clearing conditions] * * * * When transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1) When a stop condition is detected in the bus line state after a stop condition is 2 issued with the I C bus format or serial format selected When a stop condition is detected with the I2C bus format selected In receive mode (TRS = 0) (A 0 write to TRS during transfer is valid after reception of a frame containing an acknowledge bit) 1 The next transmit data can be written in ICDR (ICDRT) [Setting conditions] * In transmit mode (TRS = 1), when a start condition is detected in the bus line state 2 after a start condition is issued in master mode with the I C bus format or serial format selected When data is transferred from ICDRT to ICDRS (Data transfer from ICDRT to ICDRS when TRS = 1 and TDRE = 0, and ICDRS is empty) * In receive mode (TRS = 0), when a switch is made from slave receive mode (TRS = 0) to transmit mode (TRS = 1) after detection of a start condition (first time only) (Initial value) * RDRF 0 Description The data in ICDR (ICDRR) is invalid [Clearing condition] * When ICDR (ICDRR) receive data is read in receive mode (Initial value) 1 The ICDR (ICDRR) receive data can be read [Setting condition] * When data is transferred from ICDRS to ICDRR (Data transfer from ICDRS to ICDRR in case of normal termination with TRS = 0 and RDRF = 0) Rev. 6.00 Feb 22, 2005 page 542 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) 15.2.2 Bit Slave Address Register (SAR) : 7 SVA6 0 R/W 6 SVA5 0 R/W 5 SVA4 0 R/W 4 SVA3 0 R/W 3 SVA2 0 R/W 2 SVA1 0 R/W 1 SVA0 0 R/W 0 FS 0 R/W Initial value : R/W : SAR is an 8-bit readable/writable register that stores the slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device. SAR is assigned to the same address as ICMR, and can be written and read only when the ICE bit is cleared to 0 in ICCR. SAR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 1--Slave Address (SVA6 to SVA0): Set a unique address in bits SVA6 to SVA0, differing from the addresses of other slave devices connected to the I2C bus. Bit 0--Format Select (FS): Used together with the FSX bit in SARX to select the communication format. * I2C bus format: addressing format with acknowledge bit * Synchronous serial format: non-addressing format without acknowledge bit, for master mode only The FS bit also specifies whether or not SAR slave address recognition is performed in slave mode. Rev. 6.00 Feb 22, 2005 page 543 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) SAR Bit 0 FS 0 SARX Bit 0 FSX 0 1 Operating Mode I2C bus format * 2 SAR and SARX slave addresses recognized (Initial value) SAR slave address recognized SARX slave address ignored SAR slave address ignored SARX slave address recognized SAR and SARX slave addresses ignored I C bus format * * 1 0 I C bus format * * 2 1 Synchronous serial format * 15.2.3 Bit Second Slave Address Register (SARX) : 7 SVAX6 0 R/W 6 SVAX5 0 R/W 5 SVAX4 0 R/W 4 SVAX3 0 R/W 3 SVAX2 0 R/W 2 SVAX1 0 R/W 1 SVAX0 0 R/W 0 FSX 1 R/W Initial value : R/W : SARX is an 8-bit readable/writable register that stores the second slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device. SARX is assigned to the same address as ICDR, and can be written and read only when the ICE bit is cleared to 0 in ICCR. SARX is initialized to H'01 by a reset and in hardware standby mode. Bits 7 to 1--Second Slave Address (SVAX6 to SVAX0): Set a unique address in bits SVAX6 to SVAX0, differing from the addresses of other slave devices connected to the I2C bus. Rev. 6.00 Feb 22, 2005 page 544 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Bit 0--Format Select X (FSX): Used together with the FS bit in SAR to select the communication format. * I2C bus format: addressing format with acknowledge bit * Synchronous serial format: non-addressing format without acknowledge bit, for master mode only The FSX bit also specifies whether or not SARX slave address recognition is performed in slave mode. For details, see the description of the FS bit in SAR. 15.2.4 Bit I2C Bus Mode Register (ICMR) : 7 MLS 0 R/W 6 WAIT 0 R/W 5 CKS2 0 R/W 4 CKS1 0 R/W 3 CKS0 0 R/W 2 BC2 0 R/W 1 BC1 0 R/W 0 BC0 0 R/W Initial value : R/W : ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the master mode transfer clock frequency and the transfer bit count. ICMR is assigned to the same address as SAR. ICMR can be written and read only when the ICE bit is set to 1 in ICCR. ICMR is initialized to H'00 by a reset and in hardware standby mode. Bit 7--MSB-First/LSB-First Select (MLS): Selects whether data is transferred MSB-first or LSB-first. If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1. Do not set this bit to 1 when the I2C bus format is used. Bit 7 MLS 0 1 Description MSB-first LSB-first (Initial value) Rev. 6.00 Feb 22, 2005 page 545 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Bit 6--Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data and the acknowledge bit, in master mode with the I2C bus format. When WAIT is set to 1, after the fall of the clock for the final data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level). When the IRIC flag is cleared to 0 in ICCR, the wait ends and the acknowledge bit is transferred. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. The IRIC flag in ICCR is set to 1 on completion of the acknowledge bit transfer, regardless of the WAIT setting. The setting of this bit is invalid in slave mode. Bit 6 WAIT 0 1 Description Data and acknowledge bits transferred consecutively Wait inserted between data and acknowledge bits (Initial value) Rev. 6.00 Feb 22, 2005 page 546 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Bits 5 to 3--Serial Clock Select (CKS2 to CKS0): These bits, together with the IICX1 (channel 1) or IICX0 (channel 0) bit in the SCRX register, select the serial clock frequency in master mode. They should be set according to the required transfer rate. SCRX Bit 5 or 6 Bit 5 IICX 0 CKS2 0 Bit 4 CKS1 0 1 Bit 3 CKS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 = Clock 5 MHz /28 /40 /48 /64 /80 /100 /112 /128 /56 /80 /96 /128 /160 /200 /224 /256 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz 89.3 kHz 62.5 kHz 52.1 kHz 39.1 kHz 31.3 kHz 25.0 kHz 22.3 kHz 19.5 kHz = 8 MHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz Transfer Rate = 10 MHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz = 16 MHz = 20 MHz 571 kHz* 714 kHz* 400 kHz 500 kHz* 333 kHz 250 kHz 200 kHz 160 kHz 143 kHz 125 kHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz 417 kHz* 313 kHz 250 kHz 200 kHz 179 kHz 156 kHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz 1 0 1 80.0 kHz 71.4 kHz 62.5 kHz 143 kHz 100 kHz 83.3 kHz 62.5 kHz 50.0 kHz 40.0 kHz 35.7 kHz 31.3 kHz 2 1 0 0 1 1 0 1 Note: * These rates are outside the ranges stipulated in the I C bus interface specifications (normal mode: max. 100 kHz, high-speed mode: max. 400 kHz). Rev. 6.00 Feb 22, 2005 page 547 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Bits 2 to 0--Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the number of bits to be transferred next. With the I2C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low. The bit counter is initialized to 000 by a reset and when a start condition is detected. The value returns to 000 at the end of a data transfer, including the acknowledge bit. Bit 2 BC2 0 Bit 1 BC1 0 1 1 0 1 Bit 0 BC0 0 1 0 1 0 1 0 1 Bits/Frame Synchronous Serial Format 8 1 2 3 4 5 6 7 I2C Bus Format 9 2 3 4 5 6 7 8 (Initial value) Rev. 6.00 Feb 22, 2005 page 548 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) 15.2.5 Bit I2C Bus Control Register (ICCR) : 7 ICE 0 R/W 6 IEIC 0 R/W 5 MST 0 R/W 4 TRS 0 R/W 3 ACKE 0 R/W 2 BBSY 0 R/W 1 IRIC 0 R/(W)* 0 SCP 1 W Initial value : R/W : Note: * Only 0 can be written, for flag clearing. ICCR is an 8-bit readable/writable register that enables or disables the I2C bus interface, enables or disables interrupts, selects master or slave mode and transmission or reception, enables or disables acknowledgement, confirms the I2C bus interface bus status, issues start/stop conditions, and performs interrupt flag confirmation. ICCR is initialized to H'01 by a reset and in hardware standby mode. Bit 7--I2C Bus Interface Enable (ICE): Selects whether or not the I2C bus interface is to be used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer operations are enabled. When ICE is cleared to 0, the I2C bus interface module is halted and its internal states are cleared. The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers can be accessed when ICE is 1. Bit 7 ICE 0 Description I2C bus interface module disabled, with SCL and SDA signal pins set to port function (Initial value) 2 I C bus interface module internal states initialized SAR and SARX can be accessed 1 I2C bus interface module enabled for transfer operations (pins SCL and SCA are driving the bus) ICMR and ICDR can be accessed Rev. 6.00 Feb 22, 2005 page 549 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Bit 6--I2C Bus Interface Interrupt Enable (IEIC): Enables or disables interrupts from the I2C bus interface to the CPU. Bit 6 IEIC 0 1 Description Interrupts disabled Interrupts enabled (Initial value) Bit 5--Master/Slave Select (MST) Bit 4--Transmit/Receive Select (TRS) MST selects whether the I2C bus interface operates in master mode or slave mode. TRS selects whether the I2C bus interface operates in transmit mode or receive mode. In master mode with the I2C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. In slave receive mode with the addressing format (FS = 0 or FSX = 0), hardware automatically selects transmit or receive mode according to the R/W bit in the first frame after a start condition. Modification of the TRS bit during transfer is deferred until transfer of the frame containing the acknowledge bit is completed, and the changeover is made after completion of the transfer. MST and TRS select the operating mode as follows. Bit 5 MST 0 1 Bit 4 TRS 0 1 0 1 Operating Mode Slave receive mode Slave transmit mode Master receive mode Master transmit mode (Initial value) Rev. 6.00 Feb 22, 2005 page 550 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Bit 5 MST 0 Description Slave mode [Clearing conditions] (1) When 0 is written by software (2) When bus arbitration is lost after transmission is started in I2C bus format master mode 1 Master mode [Setting conditions] (1) When 1 is written by software (in cases other than clearing condition (2)) (2) When 1 is written in MST after reading MST = 0 (in case of clearing condition (2)) (Initial value) Bit 4 TRS 0 Description Receive mode [Clearing conditions] (1) When 0 is written by software (in cases other than setting condition (3)) (2) When 0 is written in TRS after reading TRS = 1 (in case of clearing condition (3)) (3) When bus arbitration is lost after transmission is started in I2C bus format master mode 1 Transmit mode [Setting conditions] (1) When 1 is written by software (in cases other than clearing conditions (3) and 4) (2) When 1 is written in TRS after reading TRS = 0 (in case of clearing conditions (3) and 4) 2 (3) When a 1 is received as the R/W bit of the first frame in I C bus format slave mode (Initial value) Rev. 6.00 Feb 22, 2005 page 551 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Bit 3--Acknowledge Bit Judgement Selection (ACKE): Specifies whether the value of the acknowledge bit returned from the receiving device when using the I2C bus format is to be ignored and continuous transfer is performed, or transfer is to be aborted and error handling, etc., performed if the acknowledge bit is 1. When the ACKE bit is 0, the value of the received acknowledge bit is not indicated by the ACKB bit, which is always 0. In this LSI, the DTC can be used to perform continuous transfer. The DTC is activated when the IRTR interrupt flag is set to 1 (IRTR is one of two interrupt flags, the other being IRIC). When the ACKE bit is 0, the TDRE, IRIC, and IRTR flags are set on completion of data transmission, regardless of the value of the acknowledge bit. When the ACKE bit is 1, the TDRE, IRIC, and IRTR flags are set on completion of data transmission when the acknowledge bit is 0, and the IRIC flag alone is set on completion of data transmission when the acknowledge bit is 1. When the DTC is activated, the TDRE, IRIC, and IRTR flags are cleared to 0 after the specified number of data transfers have been executed. Consequently, interrupts are not generated during continuous data transfer, but if data transmission is completed with a 1 acknowledge bit when the ACKE bit is set to 1, the DTC is not activated and an interrupt is generated, if enabled. Depending on the receiving device, the acknowledge bit may be significant, in indicating completion of processing of the received data, for instance, or may be fixed at 1 and have no significance. Bit 3 ACKE 0 1 Description The value of the acknowledge bit is ignored, and continuous transfer is performed (Initial value) If the acknowledge bit is 1, continuous transfer is interrupted Rev. 6.00 Feb 22, 2005 page 552 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Bit 2--Bus Busy (BBSY): The BBSY flag can be read to check whether the I2C bus (SCL, SDA) is busy or free. In master mode, this bit is also used to issue start and stop conditions. A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting BBSY to 1. A low-to-high transition of SDA while SCL is high is recognized as a stop condition, clearing BBSY to 0. To issue a start condition, use a MOV instruction to write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, use a MOV instruction to write 0 in BBSY and 0 in SCP. It is not possible to write to BBSY in slave mode; the I2C bus interface must be set to master transmit mode before issuing a start condition. MST and TRS should both be set to 1 before writing 1 in BBSY and 0 in SCP. Bit 2 BBSY 0 Description Bus is free [Clearing condition] * 1 When a stop condition is detected Bus is busy [Setting condition] * When a start condition is detected (Initial value) Bit 1--I2C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I2C bus interface has issued an interrupt request to the CPU. IRIC is set to 1 at the end of a data transfer, when a slave address or general call address is detected in slave receive mode, when bus arbitration is lost in master transmit mode, and when a stop condition is detected. IRIC is set at different times depending on the FS bit in SAR and the WAIT bit in ICMR. See section 15.3.7, IRIC Setting Timing and SCL Control. The conditions under which IRIC is set also differ depending on the setting of the ACKE bit in ICCR. IRIC is cleared by reading IRIC after it has been set to 1, then writing 0 in IRIC. When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously without CPU intervention. Rev. 6.00 Feb 22, 2005 page 553 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Bit 1 IRIC 0 Description Waiting for transfer, or transfer in progress [Clearing conditions] * When 0 is written in IRIC after reading IRIC = 1 * When ICDR is written or read by the DTC (When the TDRE or RDRF flag is cleared to 0) (This is not always a clearing condition; see the description of DTC operation for details) 1 Interrupt requested [Setting conditions] I2C bus format master mode * * * When a start condition is detected in the bus line state after a start condition is issued (when the TDRE flag is set to 1 because of first frame transmission) When a wait is inserted between the data and acknowledge bit when WAIT = 1 At the end of data transfer (at the rise of the 9th transmit/receive clock pulse, or at the fall of the 8th transmit/receive clock pulse when using wait insertion) When a slave address is received after bus arbitration is lost (when the AL flag is set to 1) When 1 is received as the acknowledge bit when the ACKE bit is 1 (when the ACKB bit is set to 1) When the slave address (SVA, SVAX) matches (when the AAS and AASX flags are set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the TDRE or RDRF flag is set to 1) When the general call address is detected (when FS = 0 and the ADZ flag is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the TDRE or RDRF flag is set to 1) When 1 is received as the acknowledge bit when the ACKE bit is 1 (when the ACKB bit is set to 1) When a stop condition is detected (when the STOP or ESTP flag is set to 1) At the end of data transfer (when the TDRE or RDRF flag is set to 1) When a start condition is detected with serial format selected (Initial value) * * 2 I C bus format slave mode * * * * * * * Synchronous serial format When any other condition arises in which the TDRE or RDRF flag is set to 1 Rev. 6.00 Feb 22, 2005 page 554 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) When, with the I2C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set. The IRTR flag (the DTC start request flag) is not set at the end of a data transfer up to detection of a retransmission start condition or stop condition after a slave address (SVA) or general call address match in I2C bus format slave mode. Even when the IRIC flag and IRTR flag are set, the TDRE or RDRF internal flag may not be set. The IRIC and IRTR flags are not cleared at the end of the specified number of transfers in continuous transfer using the DTC. The TDRE or RDRF flag is cleared, however, since the specified number of ICDR reads or writes have been completed. Table 15-3 shows the relationship between the flags and the transfer states. Rev. 6.00 Feb 22, 2005 page 555 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Table 15-3 Flags and Transfer States MST TRS BBSY ESTP STOP IRTR AASX AL 1/0 1 1 1 1 0 0 0 0 0 1/0 1 1 1/0 1/0 0 0 0 0 1/0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1/0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 AAS 0 0 0 0 0 1/0 1 1 0 0 ADZ 0 0 0 0 0 1/0 0 1 0 0 ACKB State 0 0 0 0/1 0/1 0 0 0 0 0/1 Idle state (flag clearing required) Start condition issuance Start condition established Master mode wait Master mode transmit/receive end Arbitration lost SAR match by first frame in slave mode General call address match SARX match Slave mode transmit/receive end (except after SARX match) Slave mode transmit/receive end (after SARX match) Stop condition detected 0 0 0 1/0 1 1/0 1 1 0 0 0 1/0 0 0 1/0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0/1 Bit 0--Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. If 1 is written, the data is not stored. Bit 0 SCP 0 1 Description Writing 0 issues a start or stop condition, in combination with the BBSY flag Reading always returns a value of 1 Writing is ignored (Initial value) Rev. 6.00 Feb 22, 2005 page 556 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) 15.2.6 Bit I2C Bus Status Register (ICSR) : 7 ESTP 0 R/(W)* 6 STOP 0 R/(W)* 5 IRTR 0 R/(W)* 4 AASX 0 R/(W)* 3 AL 0 R/(W)* 2 AAS 0 R/(W)* 1 ADZ 0 R/(W)* 0 ACKB 0 R/W Initial value : R/W : Note: * Only 0 can be written, for flag clearing. ICSR is an 8-bit readable/writable register that performs flag confirmation and acknowledge confirmation and control. ICSR is initialized to H'00 by a reset and in hardware standby mode. Bit 7--Error Stop Condition Detection Flag (ESTP): Indicates that a stop condition has been detected during frame transfer in I2C bus format slave mode. Bit 7 ESTP 0 Description No error stop condition [Clearing conditions] * * 1 When 0 is written in ESTP after reading ESTP = 1 When the IRIC flag is cleared to 0 (Initial value) In I2C bus format slave mode Error stop condition detected [Setting condition] * When a stop condition is detected during frame transfer In other modes No meaning Rev. 6.00 Feb 22, 2005 page 557 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Bit 6--Normal Stop Condition Detection Flag (STOP): Indicates that a stop condition has been detected after completion of frame transfer in I2C bus format slave mode. Bit 6 STOP 0 Description No normal stop condition [Clearing conditions] * * 1 When 0 is written in STOP after reading STOP = 1 When the IRIC flag is cleared to 0 2 (Initial value) In I C bus format slave mode Normal stop condition detected [Setting condition] * When a stop condition is detected after completion of frame transfer In other modes No meaning Bit 5--I2C Bus Interface Continuous Transmission/Reception Interrupt Request Flag (IRTR): Indicates that the I2C bus interface has issued an interrupt request to the CPU, and the source is completion of reception/transmission of one frame in continuous transmission/reception for which DTC activation is possible. When the IRTR flag is set to 1, the IRIC flag is also set to 1 at the same time. IRTR flag setting is performed when the TDRE or RDRF flag is set to 1. IRTR is cleared by reading IRTR after it has been set to 1, then writing 0 in IRTR. IRTR is also cleared automatically when the IRIC flag is cleared to 0. Rev. 6.00 Feb 22, 2005 page 558 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Bit 5 IRTR 0 Description Waiting for transfer, or transfer in progress [Clearing conditions] * * 1 When 0 is written in IRTR after reading IRTR = 1 When the IRIC flag is cleared to 0 (Initial value) Continuous transfer state [Setting conditions] * * In I2C bus interface slave mode When the TDRE or RDRF flag is set to 1 when AASX = 1 In other modes When the TDRE or RDRF flag is set to 1 Bit 4--Second Slave Address Recognition Flag (AASX): In I2C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX. AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX. AASX is also cleared automatically when a start condition is detected. Bit 4 AASX 0 Description Second slave address not recognized [Clearing conditions] * * * 1 When 0 is written in AASX after reading AASX = 1 When a start condition is detected In master mode (Initial value) Second slave address recognized [Setting condition] * When the second slave address is detected in slave receive mode and FSX = 0 Rev. 6.00 Feb 22, 2005 page 559 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Bit 3--Arbitration Lost (AL): This flag indicates that arbitration was lost in master mode. The I2C bus interface monitors the bus. When two or more master devices attempt to seize the bus at nearly the same time, if the I2C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been taken by another master. AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 3 AL 0 Description Bus arbitration won [Clearing conditions] * * 1 When ICDR data is written (transmit mode) or read (receive mode) When 0 is written in AL after reading AL = 1 (Initial value) Arbitration lost [Setting conditions] * * If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode If the internal SCL line is high at the fall of SCL in master transmit mode Bit 2--Slave Address Recognition Flag (AAS): In I2C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected. AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS. In addition, AAS is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Rev. 6.00 Feb 22, 2005 page 560 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Bit 2 AAS 0 Description Slave address or general call address not recognized [Clearing conditions] * * * 1 When ICDR data is written (transmit mode) or read (receive mode) When 0 is written in AAS after reading AAS = 1 In master mode (Initial value) Slave address or general call address recognized [Setting condition] * When the slave address or general call address is detected in slave receive mode and FS = 0 Bit 1--General Call Address Recognition Flag (ADZ): In I2C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (H'00). ADZ is cleared by reading ADZ after it has been set to 1, then writing 0 in ADZ. In addition, ADZ is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 1 ADZ 0 Description General call address not recognized [Clearing conditions] * * * 1 When ICDR data is written (transmit mode) or read (receive mode) When 0 is written in ADZ after reading ADZ = 1 In master mode (Initial value) General call address recognized [Setting condition] * When the general call address is detected in slave receive mode and (FSX = 0 or FS = 0) Rev. 6.00 Feb 22, 2005 page 561 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Bit 0--Acknowledge Bit (ACKB): Stores acknowledge data. In transmit mode, after the receiving device receives data, it returns acknowledge data, and this data is loaded into ACKB. In receive mode, after data has been received, the acknowledge data set in this bit is sent to the transmitting device. When this bit is read, in transmission (when TRS = 1), the value loaded from the bus line (returned by the receiving device) is read. In reception (when TRS = 0), the value set by internal software is read. In addition, when this bit is written to in reception the transmission acknowledge data setting is overwritten regardless of the value of TRS. The value loaded from the reception device is maintained unchanged, so caution is necessary when using bit operation instructions to overwrite this register. Bit 0 ACKB 0 Description Receive mode: 0 is output at acknowledge output timing (Initial value) Transmit mode: Indicates that the receiving device has acknowledged the data (signal is 0) 1 Receive mode: 1 is output at acknowledge output timing Transmit mode: Indicates that the receiving device has not acknowledged the data (signal is 1) Rev. 6.00 Feb 22, 2005 page 562 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) 15.2.7 Bit Serial Control Register X (SCRX) : 3/4 0 R/W 7 6 IICX1 0 R/W 5 IICX0 0 R/W 4 IICE 0 R/W 3/4 1 R 3 3/4 0 R/W 2 3/4 0 R/W 1 3/4 0 R/W 0 Initial value : R/W : SCRX is an 8-bit readable/writable register that controls register access, the I2C interface operating mode. If a module controlled by SCRX is not used, do not write 1 to the corresponding bit. SCRX is initialized to H'08 by a reset and in hardware standby mode. Bit 7--Reserved: Do not set 1. Bit 6--I2C Transfer Select 1 (IICX1): This bit, together with bits CKS2 to CKS0 in ICMR of IIC1, selects the transfer rate in master mode. For details, see section 15.2.4, I2C Bus Mode Register (ICMR). Bit 5--I2C Transfer Select 0 (IICX0): This bit, together with bits CKS2 to CKS0 in ICMR of IIC0, selects the transfer rate in master mode. For details, see section 15.2.4, I2C Bus Mode Register (ICMR). Bit 4--I2C Master Enable (IICE): Controls CPU access to the I2C bus interface data and control registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR). Bit 4 IICE 0 1 Description CPU access to I2C bus interface data and control registers is disabled CPU access to I C bus interface data and control registers is enabled 2 (Initial value) Bit 3-- Reserved: Always returns a value of 1 if it is read. Bits 2 to 0--Reserved: Do not set 1. Rev. 6.00 Feb 22, 2005 page 563 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) 15.2.8 Bit DDC Switch Register (DDCSWR) : 3/4 0 7 3/4 0 6 3/4 0 5 3/4 0 4 3 CLR3 1 W*2 2 CLR2 1 W*2 1 CLR1 1 W*2 0 CLR0 1 W*2 Initial value : R/W : R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 Notes: 1. Should always be written with 0. 2. Always read as 1. DDCSWR is an 8-bit readable/writable register that is used to initialize the IIC module. DDCSWR is initialized to H'0F by a reset and in hardware standby mode. Bits 7 to 4--Reserved: Should always be written with 0. Bits 3 to 0--IIC Clear 3 to 0 (CLR3 to CLR0): These bits control initialization of the internal state of IIC0 and IIC1. These bits can only be written to; if read they will always return a value of 1. When a write operation is performed on these bits, a clear signal is generated for the internal latch circuit of the corresponding module(s), and the internal state of the IIC module(s) is initialized. The write data for these bits is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. When clearing is required again, all the bits must be written to in accordance with the setting. Bit 3 CLR3 0 Bit 2 CLR2 0 1 Bit 1 CLR1 -- 0 1 1 -- -- Bit 0 CLR0 -- 0 1 0 1 -- Description Setting prohibited Setting prohibited IIC0 internal latch cleared IIC1 internal latch cleared IIC0 and IIC1 internal latches cleared Invalid setting Rev. 6.00 Feb 22, 2005 page 564 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) 15.2.9 Bit Module Stop Control Register B (MSTPCRB) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : R/W : MSTPCRB is an 8-bit readable/writable register that perform module stop mode control. When the MSTPB4 or MSTPB3 bit is set to 1, operation of the corresponding IIC channel is halted at the end of the bus cycle, and a transition is made to module stop mode. For details, see section 23A.5, 23B.5, Module Stop Mode. MSTPCRB is initialized to H'FF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset and in software standby mode. Bit 4--Module Stop (MSTPB4): Specifies IIC channel 0 module stop mode. Bit 4 MSTPB4 0 1 Description IIC channel 0 module stop mode is cleared IIC channel 0 module stop mode is set (Initial value) Bit 3--Module Stop (MSTPB3): Specifies IIC channel 1 module stop mode. Bit 3 MSTPB3 0 1 Description IIC channel 1 module stop mode is cleared IIC channel 1 module stop mode is set (Initial value) Rev. 6.00 Feb 22, 2005 page 565 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) 15.3 15.3.1 Operation I2C Bus Data Format The I2C bus interface has serial and I2C bus formats. The I2C bus formats are addressing formats with an acknowledge bit. These are shown in figures 15-3 (a) and (b). The first frame following a start condition always consists of 8 bits. The serial format is a non-addressing format with no acknowledge bit. Although start and stop conditions must be issued, this format can be used as a synchronous serial format. This is shown in figure 15-4. Figure 15-5 shows the I2C bus timing. The symbols used in figures 15-3 to 15-5 are explained in table 15-4. (a) I2C bus format (FS = 0 or FSX = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) (b) I2C bus format (start condition retransmission, FS = 0 or FSX = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 A/A 1 P 1 n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 1) Figure 15-3 I2C Bus Data Formats (I2C Bus Formats) Rev. 6.00 Feb 22, 2005 page 566 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) FS = 1 and FSX = 1 S 1 DATA 8 1 DATA n m P 1 n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) Figure 15-4 I2C Bus Data Format (Serial Format) SDA SCL S 1-7 SLA 8 R/W 9 A 1-7 DATA 8 9 A 1-7 DATA 8 9 A/A P Figure 15-5 I2C Bus Timing Table 15-4 I2C Bus Data Format Symbols Legend S SLA R/W A DATA P Start condition. The master device drives SDA from high to low while SCL is high Slave address, by which the master device selects a slave device Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0 Acknowledge. The receiving device (the slave in master transmit mode, or the master in master receive mode) drives SDA low to acknowledge a transfer Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-first or LSB-first format is selected by bit MLS in ICMR Stop condition. The master device drives SDA from low to high while SCL is high Rev. 6.00 Feb 22, 2005 page 567 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) 15.3.2 Initial Setting At startup the following procedure is used to initialize the IIC. Start initialization Set MSTP4 = 0 (IIC0) MSTP3 = 0 (IIC1) (MSTPCRB) Set IICE = 1 (SCRX) Set ICE = 0 (ICCR) Set SAR and SARX Set ICE = 1 (ICCR) Set ICSR Set SCRX Set IMCR Set ICCR Transmit/receive start Clear module stop Enable CPU access by IIC control register and data register Enable SAR and SARX access Set transfer format for 1st slave address, 2nd slave address, and IIC (SVA8-SVA0, FS, SVAX6-SVAX0, FSX) Enable IMCR and IMDR access. Use SCL and SDA pins is IIC port Set acknowledge bit (ACKB) Set transfer rate (IICX) Set transfer format, wait insertion, and transfer rate (MLS, WAIT, CKS2-CKS0) Set interrupt enable, transfer mode, and acknowledge judgment (IEIC, MST, TRS, ACKE) Figure 15-6 Flowchart for IIC Initialization (Example) Note: The ICMR register should be written to only after transmit or receive operations have completed. Writing to the ICMR register while a transmit or receive operation is in progress could cause an erroneous value to be written to bit counter bits BC2 to BC0. This could result in improper operation. 15.3.3 Master Transmit Operation In I2C bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. Figure 15-7 is a flowchart showing an example of the master transmit mode. Rev. 6.00 Feb 22, 2005 page 568 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Start Initial settings [1] Initial settings Read BBSY flag in ICCR [2] Determine status of SCL and SDA lines No BBSY = 0? Yes Set MST = 1 and TRS = 1 (ICCR) Write BBSY = 1 and SCP = 0 (ICCR) [3] Set to master transmit mode [4] Generate start condition Read IRIC flag in ICCR [5] Wait for start condition to be met No IRIC = 1? Yes Write transmit data to ICDR Clear IRIC flag in ICCR [6] Set 1st byte (slave address + R/W) transmit data (Perform ICDR write and IRIC flag clear operations continuously) Read IRIC flag in ICCR [7] Wait for end of 1 byte transmission No IRIC = 1? Yes Read ACKB bit in ICSR ACKB = 0? Yes Transmit mode? Yes Write transmit data to ICDR Clear IRIC flag in ICCR [9] Set transmit data for 2nd byte onward (Perform ICDR write and IRIC flag clear operations continuously) No Master receive mode No [8] Judge acknowledge signal from specified slave device Read IRIC flag in ICCR [10] Wait for end of 1 byte transmission No IRIC = 1? Yes Read ACKB bit in ICSR [11] Judge end of transmission No Transmit complete? (ACKB = 1?) Yes Clear IRIC flag in ICCR [12] Generate stop condition. Write BBSY = 0 and SCP = 0 (ICCR) End Figure 15-7 Flowchart for Master Transmit Mode (Example) Rev. 6.00 Feb 22, 2005 page 569 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) The procedure for transmitting data sequentially, synchronized with ICDR (ICDRT) write operations, is described below. [1] [2] [3] [4] [5] [6] Perform initial settings as described in section 15.3.2, Initial Setting. Read the BBSY flag in ICCR to confirm that the bus is free. Set bits MST and TSR in ICCR to 1 to switch to the master transmit mode. Write 1 to BBSY and 0 to SCP in ICCR. This changes SDA from high to low when SCL is high, and generates the start condition. The IRIC and IRTR flags are set to 1 when the start condition is generated. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. After the start condition is detected, write the data (slave address + R/W) to ICDR. With the I2C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame data following the start condition indicates the 7-bit slave address and transmit/receive direction (R/W). Next, clear the IRIC flag to 0 to indicate the end of the transfer. Continue successively writing to ICDR and clearing the IRIC flag to ensure that processing of other interrupts does not intervene. If the time required to transmit one byte of data elapses by the time the IRIC flag is cleared, it will not be possible to determine the end of the transmission. The master device sequentially sends the transmit clock and the data written to ICDR. The selected slave device (i.e., the slave device with the matching slave address) drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. Read the ACKB bit in ICSR to confirm that its value is 0. If the slave device has not returned an acknowledge signal and the value of ACKB is 1, perform the transmit end processing described in step [12] and then recommence the transmit operation from the beginning. Write the transmit data to ICDR. Next, clear the IRIC flag to 0 to indicate the end of the transfer. Then continue successively writing to ICDR and clearing the IRIC flag as described in step [6]. Transmission of the next frame is synchronized with the internal clock. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. Read the ACKB bit in ICSR to confirm that the slave device has returned an acknowledge signal and the value of ACKB is 0. If the slave device has not returned an acknowledge signal and the value of ACKB is 1, perform the transmit end processing described in step [12]. Clear the IRIC flag to 0. Write 0 to the ACKE bit in ICCR and clear the received ACKB bit to 0. [7] [8] [9] [10] [11] [12] Rev. 6.00 Feb 22, 2005 page 570 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. Generate start condition SCL (Master output) SDA (Master output) SDA (Slave output) ICDRE IRIC IRTR ICDRT ICDRS Note: ICDR data setting timing Normal operation Improper operation will result User processing [4] Write BBSY = 1 and SCP = 0 (generate start condition) [6] ICDR write [6] IRIC clearance [9] ICDR write [9] IRIC clearance Address + R/W Address + R/W Data 1 Data 1 Interrupt request Interrupt request 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 R/W [7] A 9 1 Bit 7 2 Bit 6 Slave address [5] Data 1 Figure 15-8 Example of Master Transmit Mode Operation Timing (MLS = WAIT = 0) Rev. 6.00 Feb 22, 2005 page 571 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Generate start condition SCL (Master output) SDA (Master output) 8 Bit 0 Data 1 SDA (Slave output) ICDRE IRIC IRTR ICDR Data 1 Data 2 [7] A 9 1 Bit 7 2 3 4 Bit 4 5 Bit 3 6 Bit 2 7 8 9 Bit 6 Bit 5 Bit 1 Bit 0 [10] A Data 2 User processing [9] ICDR write [9] IRIC clearance [11] ACKB read [12] Write BBSY = 0 and SCP = 0 (generate stop condition) [12] IRIC clearance Figure 15-9 Example of Master Transmit Mode Stop Condition Generation Timing (MLS = WAIT = 0) 15.3.4 Master Receive Operation In I2C bus format master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits data. The master device transmits the data containing the slave address + R/W (0: read) in the 1st frame after a start condition is generated in the master transmit mode. After the slave device is selected the switch to receive operation takes place. (1) Receive Operation Using Wait States Figures 15-10 and 15-11 are flowcharts showing examples of the master receive mode (WAIT = 1). Rev. 6.00 Feb 22, 2005 page 572 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Master receive mode Set TRS = 0 (ICCR) Set ACKB = 0 (ICSR) Clear IRIC flag in ICCR Set WAIT = 1 (ICMR) Read ICDR [2] Receive start, dummy read [1] Set to receive mode Read IRIC flag in ICCR No IRIC = 1? Yes No IRTR = 1? Yes Final receive? No Read ICDR Clear IRIC flag in ICCR Yes [3] Receive wait state (IRIC set at falling edge of 8th clock cycle) or Wait for end of reception of 1 byte (IRIC set at rising edge of 9th clock cycle) [4] Data receive completed judgment [5] Read receive data [6] Clear IRIC flag (cancel wait state) Set ACKB = 1 (ICSR) 1 clock cycle wait state Set TRS = 1 (ICCR) Read ICDR Clear IRIC flag in ICCR [7] Set acknowledge data for final receive [8] Wait time until TRS setting [9] Set TRS to generate stop condition [10] Read receive data [11] Clear IRIC flag (cancel wait state) Read IRIC flag in ICCR No IRIC = 1? Yes IRTR = 1? No Clear IRIC flag in ICCR Yes [12] Receive wait state (IRIC set at falling edge of 8th clock cycle) or Wait for end of reception of 1 byte (IRIC set at rising edge of 9th clock cycle) [13] Data receive completed judgment [14] Clear IRIC flag (cancel wait state) Set WAIT = 0 (ICMR) Clear IRIC flag in ICCR Read ICDR Write BBSY = 0 and SCP = 0 (ICCR) End [15] Cancel wait mode Clear IRIC flag (IRIC flag should be cleared when WAIT = 0) [16] Read final receive data [17] Generate stop condition Figure 15-10 Flowchart for Master Receive Mode (Receiving Multiple Bytes) (WAIT = 1) (Example) Rev. 6.00 Feb 22, 2005 page 573 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Master receive mode Set TRS = 0 (ICCR) Set ACKB = 0 (ICSR) [1] Clear IRIC flag in ICCR Set WAIT = 1 (ICMR) Read ICDR [2] Receive start, dummy read Set to receive mode Read IRIC flag in ICCR No IRIC = 1? Yes Set ACKB = 1 (ICSR) Set TRS = 1 (ICCR) Clear IRIC flag in ICCR [3] Receive wait state (IRIC set at falling edge of 8th clock cycle) or Wait for end of reception of 1 byte (IRIC set at rising edge of 9th clock cycle) [7] [9] Set acknowledge data for final receive Set TRS to generate stop condition [11] Clear IRIC flag (cancel wait state) Read IRIC flag in ICCR No [12] Wait for end of reception of 1 byte (IRIC set at rising edge of 9th clock cycle) IRIC = 1? Yes Set WAIT = 0 (ICMR) Clear IRIC flag in ICCR Read ICDR Write BBSY = 0 and SCP = 0 (ICCR) End [15] Cancel wait mode Clear IRIC flag (IRIC flag should be cleared when WAIT = 0) [16] Read final receive data [17] Generate stop condition Figure 15-11 Flowchart for Master Receive Mode (Receiving 1 Byte) (WAIT = 1) (Example) The procedure for receiving data sequentially, using the wait states (WAIT bit) for synchronization with ICDR (ICDRR) read operations, is described below. The procedure below describes the operation for receiving multiple bytes. Note that some of the steps are omitted when receiving only 1 byte. Refer to figure 15-11 for details. Rev. 6.00 Feb 22, 2005 page 574 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) [1] Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 (acknowledge data setting). Clear the IRIC flag to 0, then set the WAIT bit in ICMR to 1. [2] When ICDR is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. [3] The IRIC flag is set to 1 by the following two conditions. At that point, an interrupt request is issued to the CPU if the IEIC bit in ICCR is set to 1. 1. The flag is set at the falling edge of the 8th clock cycle of the receive clock for 1 frame. SCL is automatically held low, in synchronization with the internal clock, until the IRIC flag is cleared. 2. The flag is set at the rising edge of the 9th clock cycle of the receive clock for 1 frame. The IRIC flag and ICDRF flag are set to 1, indicating that reception of 1 frame of data has ended. The master device continues to output the receive clock for the receive data. [4] Read the IRTR flag in ICSR. If the IRTR flag value is 0, the wait state is cancelled by clearing the IRIC flag as described in step [6] below. If the IRTR flag value is 1 and the next receive data is the final receive data, perform the end processing described in step [7] below. [5] If the IRTR flag value is 1, read the ICDR receive data. [6] Clear the IRTR flag to 0. If condition [3]-1 is true, the master device drives SDA to low level and returns an acknowledge signal when the receive clock outputs the 9th clock cycle. Further data can be received by repeating steps [3] through [6]. [7] Set the ACKB bit in ICSR to 1 to set the acknowledge data for the final receive. [8] Wait for at least 1 clock cycle after the IRIC flag is set to 1 and then wait for the rising edge of the 1st clock cycle of the next receive data. [9] Set the TSR bit in ICCR to 1 to switch from the receive mode to the transmit mode. The TSR bit setting value at this point becomes valid when the rising edge of the next 9th clock cycle is input. [10] Read the ICDR receive data. [11] Clear the IRTR flag to 0. [12] The IRIC flag is set to 1 by the following two conditions. 1. The flag is set at the falling edge of the 8th clock cycle of the receive clock for 1 frame. SCL is automatically held low, in synchronization with the internal clock, until the IRIC flag is cleared. 2. The flag is set at the rising edge of the 9th clock cycle of the receive clock for 1 frame. The IRIC flag and ICDRF flag are set to 1, indicating that reception of 1 frame of data has ended. The master device continues to output the receive clock for the receive data. [13] Read the IRTR flag in ICSR. If the IRTR flag value is 0, the wait state is cancelled by clearing the IRIC flag as described in step [14] below. If the IRTR flag value is 1 and the Rev. 6.00 Feb 22, 2005 page 575 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) [14] [15] [16] [17] receive operation has finished, perform the issue stop condition processing described in step [15] below. If the IRTR flag value is 0, clear the IRIC flag to 0 to cancel the wait state. Return to reading the IRIC flag, as described in step [12], to detect the end of the receive operation. Clear the WAIT bit in ICMR to 0 to cancel the wait mode. Then clear the IRIC flag to 0. The IRIC flag should be cleared when the value of WAIT is 0 (The stop condition may not be output properly when the issue stop condition instruction is executed if the WAIT bit was cleared to 0 after the IRIC flag is cleared to 0). Read the final receive data in ICDR. Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. Master transmit mode Master receive mode SCL (master output) SDA (slave output) 9 A 1 2 3 4 5 6 7 8 9 1 2 3 4 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Data 1 Bit 1 Bit 0 [3] A [3] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Data 2 SDA (master output) IRIC IRTR ICDR [4] IRTR = 0 [4] IRTR = 1 Data 1 User processing [2] ICDR read (dummy read) [1] TRS cleared to 0 IRIC clearance [6] IRIC clearance (cancel wait) [5] ICDR read (data 1) [6] IRIC clearance Figure 15-12 Example of Master Receive Mode Operation Timing (MLS = ACKB = 0, WAIT = 1) Rev. 6.00 Feb 22, 2005 page 576 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) [8] 1 clock cycle wait time SCL (master output) Stop condition generated 4 5 6 7 8 9 8 9 1 2 3 SDA Bit 0 (slave output) Data 2 [3] SDA (master output) IRIC IRTR ICDR [4] IRTR = 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 [3] A Data 3 Bit 1 Bit 0 [12] A [12] [4] IRTR = 1 [13] IRTR = 0 [13] IRTR = 1 Data 1 Data 2 Data 3 User processing [6] IRIC clearance [11] IRIC clearance [10] ICDR read (data 2) [9] TRS set to 1 [14] IRIC clearance [15] WAIT cleared to 0 IRIC clearance [17] Stop condition issued [7] ACKB set to 1 [16] ICDR read (data 3) Figure 15-13 Example of Master Receive Mode Stop Condition Generation Timing (MLS = ACKB = 0, WAIT = 1) 15.3.5 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The slave device compares its own address with the slave address in the first frame following the establishment of the start condition issued by the master device. If the addresses match, the slave device operates as the slave device designated by the master device. Figure 15-14 is a flowchart showing an example of slave receive mode operation. Rev. 6.00 Feb 22, 2005 page 577 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Start Initialize Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR Read IRIC in ICCR No [2] IRIC = 1? Yes [1] Read AAS and ADZ in ICSR AAS = 1 and ADZ = 0? Yes Read TRS in ICCR TRS = 0? Yes Last receive? No Read ICDR Clear IRIC in ICCR Yes No Slave transmit mode No General call address processing * Description omitted [3] [1] Select slave receive mode [2] Wait for the first byte to be received (slave address) [3] Start receiving. The first read is a dummy read [4] Read IRIC in ICCR No IRIC = 1? Yes [4] Wait for the transfer to end [5] Set acknowledge data for the last receive [6] Start the last receive [7] Wait for the transfer to end Set ACKB = 0 in ICSR Read ICDR Clear IRIC in ICCR [5] [6] [8] Read the last receive data Read IRIC in ICCR No IRIC = 1? Yes Read ICDR Clear IRIC in ICCR End [7] [8] Figure 15-14 Flowchart for Slave Transmit Mode (Example) Rev. 6.00 Feb 22, 2005 page 578 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) The reception procedure and operations in slave receive mode are described below. (1) Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode. (2) When the start condition output by the master device is detected, the BBSY flag in ICCR is set to 1. (3) When the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the TRS bit in ICCR remains cleared to 0, and slave receive operation is performed. (4) At the 9th clock pulse of the receive frame, the slave device drives SDA low and returns an acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. If the RDRF internal flag has been cleared to 0, it is set to 1, and the receive operation continues. If the RDRF internal flag has been set to 1, the slave device drives SCL low from the fall of the receive clock until data is read into ICDR. (5) Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0. Receive operations can be performed continuously by repeating steps (4) and (5). When SDA is changed from low to high when SCL is high, and the stop condition is detected, the BBSY flag in ICCR is cleared to 0. Rev. 6.00 Feb 22, 2005 page 579 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Start condition issuance SCL (master output) SCL (slave output) SDA (master output) SDA (slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 1 2 3 4 5 6 7 8 9 1 2 Slave address R/W [4] A Data 1 RDRF IRIC Interrupt request generation Address + R/W ICDRS ICDRR Address + R/W User processing [5] ICDR read [5] IRIC clearance Figure 15-15 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0) Rev. 6.00 Feb 22, 2005 page 580 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) SCL (master output) SCL (slave output) SDA (master output) 7 8 9 1 2 3 4 5 6 7 8 9 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data 1 SDA (slave output) [4] Data 2 [4] A A RDRF IRIC Interrupt request generation Data 1 Data 2 Interrupt request generation ICDRS ICDRR Data 1 Data 2 User processing [5] ICDR read [5] IRIC clearance Figure 15-16 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0) Rev. 6.00 Feb 22, 2005 page 581 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) 15.3.6 Slave Transmit Operation In slave transmit operation, the slave device compares its own address with the slave address transmitted by the master device in the first frame (address receive frame) following detection of the start condition. If the addresses match and the 8th bit (R/W) is set to 1 (read), the TRS bit in ICCR is automatically set to 1 and slave transmit mode is activated. Figure 15-17 is a flowchart showing an example of slave transmit mode operation. Slave transmit mode Clear IRIC in ICCR [1] Set transmit data for the second and subsequent bytes [1] [2] Wait for 1 byte to be transmitted [3] Test for end of transfer Clear IRIC in ICCR [4] Select slave receive mode [5] Dummy read (to release the SCL line) Read IRIC in ICCR No [2] IRIC = 1? Yes Read ACKB in ICSR End of transmission (ACKB = 1)? Yes Set TRS = 0 in ICCR Read ICDR Clear IRIC in ICCR [4] [3] Write transmit data in ICDR No [5] End Figure 15-17 Flowchart for Slave Receive Mode (Example) Rev. 6.00 Feb 22, 2005 page 582 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. (1) Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode. (2) When the slave address matches in the first frame following detection of the start condition, the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. If the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to 1, and the mode changes to slave transmit mode automatically. The TDRF flag is set to 1. The slave device drives SCL low from the fall of the transmit clock until ICDR data is written. (3) After clearing the IRIC flag to 0, write data to ICDR. The TDRE internal flag is cleared to 0. The written data is transferred to ICDRS, and the TDRE internal flag and the IRIC and IRTR flags are set to 1 again. After clearing the IRIC flag to 0, write the next data to ICDR. The slave device sequentially sends the data written into ICDR in accordance with the clock output by the master device at the timing shown in figure 15-18. (4) When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock pulse. If the TDRE internal flag has been set to 1, this slave device drives SCL low from the fall of the transmit clock until data is written to ICDR. The master device drives SDA low at the 9th clock pulse, and returns an acknowledge signal. As this acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to determine whether the transfer operation was performed normally. When the TDRE internal flag is 0, the data written into ICDR is transferred to ICDRS, transmission is started, and the TDRE internal flag and the IRIC and IRTR flags are set to 1 again. (5) To continue transmission, clear the IRIC flag to 0, then write the next data to be transmitted into ICDR. The TDRE flag is cleared to 0. Transmit operations can be performed continuously by repeating steps (4) and (5). To end transmission, write H'FF to ICDR to release SDA on the slave side. When SDA is changed from low to high when SCL is high, and the stop condition is detected, the BBSY flag in ICCR is cleared to 0. Rev. 6.00 Feb 22, 2005 page 583 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Slave receive mode SCL (master output) SDA (slave output) Slave transmit mode 8 9 1 2 3 4 5 6 7 8 9 1 2 SDA (slave output) SDA (slave output) R/W A [2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Data 1 A Data 2 TDRE [4] IRIC Interrupt request generation Interrupt request generation Interrupt request generation ICDRT Data 1 Data 2 ICDRS Data 1 Data 2 User processing [3] IRIC clearance [3] ICDR write [3] ICDR write [5] IRIC clearance [3] ICDR write Figure 15-18 Example of Slave Transmit Mode Operation Timing (MLS = 0) Rev. 6.00 Feb 22, 2005 page 584 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) 15.3.7 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. Figure 15-19 shows the IRIC set timing and SCL control. (a) When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait) SCL 7 8 9 1 SDA IRIC 7 8 A 1 User processing Clear IRIC Write to ICDR (transmit) or read ICDR (receive) (b) When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted) SCL 8 9 1 SDA IRIC 8 A 1 User processing Clear IRIC Clear Write to ICDR (transmit) IRIC or read ICDR (receive) (c) When FS = 1 and FSX = 1 (synchronous serial format) SCL 7 8 1 SDA IRIC 7 8 1 User processing Clear IRIC Write to ICDR (transmit) or read ICDR (receive) Figure 15-19 IRIC Setting Timing and SCL Control Rev. 6.00 Feb 22, 2005 page 585 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) 15.3.8 Operation Using the DTC The I2C bus format provides for selection of the slave device and transfer direction by means of the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out in conjunction with CPU processing by means of interrupts. Table 15-5 shows some examples of processing using the DTC. These examples assume that the number of transfer data bytes is known in slave mode. Table 15-5 Examples of Operation Using the DTC Item Master Transmit Mode Master Receive Mode Transmission by CPU (ICDR write) Slave Transmit Mode Reception by CPU (ICDR read) Slave Receive Mode Reception by CPU (ICDR read) Slave address + Transmission by R/W bit DTC (ICDR write) transmission/ reception Dummy data read Actual data transmission/ reception Dummy data (H'FF) write Last frame processing Transfer request processing after last frame processing Setting of number of DTC transfer data frames -- Transmission by DTC (ICDR write) -- Not necessary 1st time: Clearing by CPU 2nd time: End condition issuance by CPU Processing by CPU (ICDR read) Reception by DTC (ICDR read) -- Reception by CPU (ICDR read) Not necessary -- Transmission by DTC (ICDR write) Processing by DTC (ICDR write) Not necessary -- Reception by DTC (ICDR read) -- Reception by CPU (ICDR read) Automatic clearing Not necessary on detection of end condition during transmission of dummy data (H'FF) Transmission: Reception: Actual Actual data count data count + 1 (+1 equivalent to dummy data (H'FF)) Transmission: Reception: Actual Actual data count data count + 1 (+1 equivalent to slave address + R/W bits) Rev. 6.00 Feb 22, 2005 page 586 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) 15.3.9 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 15-20 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held. Sampling clock C SCL or SDA input signal D Latch Q D C Q Latch Match detector Internal SCL or SDA signal System clock period Sampling clock Figure 15-20 Block Diagram of Noise Canceler 15.3.10 Initialization of Internal State The IIC has a function for forcible initialization of its internal state if a deadlock occurs during communication. Initialization is executed by (1) setting bits CLR3 to CLR0 in the DDCSWR register or (2) clearing the ICE bit. For details of settings for bits CLR3 to CLR0, see section 15.2.8, DDC Switch Register (DDCSWR). Scope of Initialization: The initialization executed by this function covers the following items: * TDRE and RDRF internal flags * Transmit/receive sequencer and internal operating clock counter * Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data output, etc.) Rev. 6.00 Feb 22, 2005 page 587 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) The following items are not initialized: * Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, DDCSWR, and STCR) * Internal latches used to retain register read information for setting/clearing flags in the ICMR, ICCR, ICSR, and DDCSWR registers * The value of the ICMR register bit counter (BC2 to BC0) * Generated interrupt sources (interrupt sources transferred to the interrupt controller) Notes on Initialization: * Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be taken as necessary. * Basically, other register flags are not cleared either, and so flag clearing measures must be taken as necessary. * When initialization is performed by means of the DDCSWR register, the write data for bits CLR3 to CLR0 is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. Similarly, when clearing is required again, all the bits must be written to simultaneously in accordance with the setting. * If a flag clearing setting is made during transmission/reception, the IIC module will stop transmitting/receiving at that point and the SCL and SDA pins will be released. When transmission/reception is started again, register initialization, etc., must be carried out as necessary to enable correct communication as a system. The value of the BBSY bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release timing of the SCL and SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and flags may also have an effect. To prevent problems caused by these factors, the following procedure should be used when initializing the IIC state. 1. Execute initialization of the internal state according to the setting of bits CLR3 to CLR0, or according to the ICE bit. 2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBST bit to 0, and wait for two transfer rate clock cycles. 3. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0, or according to the ICE bit. 4. Initialize (re-set) the IIC registers. Rev. 6.00 Feb 22, 2005 page 588 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) 15.4 Usage Notes * In master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. To output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that SCL and SDA are both low, then issue the instruction that generates the stop condition. Note that SCL may not yet have gone low when BBSY is cleared to 0. * Either of the following two conditions will start the next transfer. Pay attention to these conditions when reading or writing to ICDR. Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to ICDRS) Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to ICDRR) * Table 15-6 shows the timing of SCL and SDA output in synchronization with the internal clock. Timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance, series resistance, and parallel resistance. Table 15-6 I2C Bus Timing (SCL and SDA Output) Item SCL output cycle time SCL output high pulse width SCL output low pulse width SDA output bus free time Start condition output hold time Retransmission start condition output setup time Stop condition output setup time Data output setup time (master) Data output setup time (slave) Data output hold time tSDAHO Symbol tSCLO tSCLHO tSCLLO tBUFO tSTAHO tSTASO tSTOSO tSDASO Output Timing 28 tcyc to 256 tcyc 0.5 tSCLO 0.5 tSCLO 0.5 tSCLO - 1 tcyc 0.5 tSCLO - 1 tcyc 1 tSCLO 0.5 tSCLO + 2 tcyc 1 tSCLLO - 3 tcyc 1 tSCLL - 3 tcyc 3 tcyc ns Unit ns ns ns ns ns ns ns ns Notes Figure 24-28 (reference) Rev. 6.00 Feb 22, 2005 page 589 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) * SCL and SDA input is sampled in synchronization with the internal clock. The AC timing therefore depends on the system clock cycle tcyc, as shown in tables 24-19, 24-31, 24-43 in section 24, Electrical Characteristics. Note that the I2C bus interface AC timing specifications will not be met with a system clock frequency of less than 5 MHz. * The I2C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for highspeed mode). In master mode, the I2C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds the time determined by the input clock of the I2C bus interface, the high period of SCL is extended. The SCL rise time is determined by the pull-up resistance and load capacitance of the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the SCL rise time does not exceed the values given in the table 15-7. Table 15-7 Permissible SCL Rise Time (tSr) Values Time Indication tcyc IICX Indication 0 7.5 tcyc Standard mode High-speed mode 1 17.5 tcyc Standard mode High-speed mode I C Bus Specification = (Max.) 5 MHz 1000 ns 300 ns 1000 ns 300 ns 1000 ns 300 ns 1000 ns 300 ns 2 = 8 MHz 937 ns 300 ns 1000 ns 300 ns = 10 MHz 750 ns 300 ns 1000 ns 300 ns = = 16 MHz 20 MHz 468 ns 300 ns 375 ns 300 ns 1000 ns 875 ns 300 ns 300 ns Rev. 6.00 Feb 22, 2005 page 590 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) * The I2C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns and 300 ns. The I2C bus interface SCL and SDA output timing is prescribed by tScyc and tcyc, as shown in table 15-6. However, because of the rise and fall times, the I2C bus interface specifications may not be satisfied at the maximum transfer rate. Table 15-8 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. tBUFO fails to meet the I2C bus interface specifications at any frequency. The solution is either (a) to provide coding to secure the necessary interval (approximately 1 s) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input timing permits this output timing for use as slave devices connected to the I2C bus. tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I2C bus interface specifications for worst-case calculations of tSr/tSf. Possible solutions that should be investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input timing permits this output timing for use as slave devices connected to the I2C bus. Rev. 6.00 Feb 22, 2005 page 591 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Table 15-8 I2C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] I C Bus tSr/tSf SpecifiInfluence cation (Max.) (Min.) Standard mode -1000 4000 600 4700 1300 4700 1300 4000 600 4700 600 4000 600 250 100 250 100 2 Item tSCLHO tcyc Indication 0.5 tSCLO (-tSr) = 5 MHz 4000 950 4750 1000* 1 = 8 MHz 4000 950 4750 1000* 1 = 10 MHz 4000 950 4750 1000* 1 = 16 MHz 4000 950 4750 1000* 1 = 20 MHz 4000 950 4750 1000* 1 High-speed -300 mode tSCLLO 0.5 tSCLO (-tSf ) Standard mode -250 High-speed -250 mode tBUFO 0.5 tSCLO - 1 tcyc ( -tSr ) Standard mode -1000 3800*1 750* 1 3875*1 825*1 4625 875 9000 2200 4250 1200 3325 625 3325 625 3900*1 850*1 4650 900 9000 2200 4200 1150 3400 700 3400 700 3938*1 888*1 4688 938 9000 2200 4125 1075 3513 813 3513 813 3950*1 900*1 4700 950 9000 2200 4100 1050 3550 850 3550 850 High-speed -300 mode Standard mode -250 tSTAHO 0.5 tSCLO - 1 tcyc (-tSf ) 4550 800 9000 2200 4400 1350 3100 400 3100 400 High-speed -250 mode Standard mode -1000 tSTASO 1 tSCLO (-tSr ) High-speed -300 mode tSTOSO 0.5 tSCLO + 2 tcyc (-tSr ) Standard mode -1000 High-speed -300 mode 1 tSCLLO*2 - Standard -1000 (master) 3 tcyc mode (-tSr ) High-speed -300 mode tSDASO 2 1 tSCLL* - *2 (slave) 3 tcyc (-tSr ) tSDASO Standard mode -1000 High-speed -300 mode Rev. 6.00 Feb 22, 2005 page 592 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Time Indication (at Maximum Transfer Rate) [ns] I C Bus Specification (Min.) 0 0 2 Item tSDAHO tcyc Indication 3 tcyc Standard mode tSr/tSf Influence (Max.) 0 = 5 MHz 600 600 = 8 MHz 375 375 = 10 MHz 300 300 = 16 MHz 188 188 = 20 MHz 150 150 High-speed 0 mode Notes: 1. Does not meet the I2C bus interface specification. Remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. The values in the above table will vary depending on the settings of the IICX bit and bits CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the maximum transfer rate; therefore, whether or not the I2C bus interface specifications are met must be determined in accordance with the actual setting conditions. 2 2. Calculated using the I C bus specification values (standard mode: 4700 ns min.; highspeed mode: 1300 ns min.). * Note on ICDR Read at End of Master Reception To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. After this, receive data can be read by means of an ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to ICDR, and so it will not be possible to read the second byte of data. If it is necessary to read the second byte of data, issue the stop condition in master receive mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the BBSY bit in the ICCR register is cleared to 0, the stop condition has been generated, and the bus has been released, then read the ICDR register with TRS cleared to 0. Note that if the receive data (ICDR data) is read in the interval between execution of the instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the actual generation of the stop condition, the clock may not be output correctly in subsequent master transmission. Clearing of the MST bit after completion of master transmission/reception, or other modifications of IIC control bits to change the transmit/receive operating mode or settings, must be carried out during interval (a) in figure 15-18 (after confirming that the BBSY bit has been cleared to 0 in the ICCR register). Rev. 6.00 Feb 22, 2005 page 593 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) Stop condition (a) SDA SCL Internal clock BBSY bit Master receive mode ICDR reading prohibited Bit 0 8 A 9 Start condition Execution of stop condition issuance instruction (0 written to BBSY and SCP) Confirmation of stop condition generation (0 read from BBSY) Start condition issuance Figure 15-21 Points for Attention Concerning Reading of Master Receive Data Rev. 6.00 Feb 22, 2005 page 594 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) * Notes on Start Condition Issuance for Retransmission Figure 15-22 shows the timing of start condition issuance for retransmission, and the timing for subsequently writing data to ICDR, together with the corresponding flowchart. [1] Wait for end of 1-byte transfer IRIC = 1 ? Yes Clear IRIC in ICSR Start condition issuance? Yes Read SCL pin SCL = Low ? Yes Write BBSY = 1, SCP = 0 (ICSR) Read SCL pin SCL = High ? Yes Write transmit data to ICDR [5] No [4] [3] No [2] No Other processing [5] Set transmit data (slave address + R/W) Note: Program so that processing from [3] to [5] is executed continuously. No [1] [2] Determine whether SCL is low [3] Issue restart condition instruction for retransmission [4] Determine whether SCL is high SCL SDA ACK Start condition (retransmission) Bit 7 IRIC [1] IRIC determination [2] Determination of SCL = low [4] Determination of SCL = high [5] ICDR write [3] Start condition instruction issuance Figure 15-22 Flowchart and Timing of Start Condition Instruction Issuance for Retransmission Rev. 6.00 Feb 22, 2005 page 595 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) * Notes on I2C Bus Interface Stop Condition Instruction Issuance If the rise time of the 9th SCL acknowledge exceeds the specification because the bus load capacitance is large, or if there is a slave device of the type that drives SCL low to effect a wait, issue the stop condition instruction after reading SCL and determining it to be low, as shown below. 9th clock VIH High period secured SCL As waveform rise is late, SCL is detected as low SDA Stop condition IRIC [1] Determination of SCL = low [2] Stop condition instruction issuance Figure 15-23 Timing of Stop Condition Issuance * Notes on IRIC Flag Clearance when Using Wait Function If the SCL rise time exceeds the designated duration or if the slave device is of the type that keeps SCL low and applies a wait state when the wait function is used in the master mode of the I2C bus interface, read SCL and clear the IRIC flag after determining that SCL has gone low, as shown below. Clearing the IRIC flag to 0 when WAIT is set to 1 and SCL is being held at high level can cause the SDA value to change before SCL goes low, resulting in a start condition or stop condition being generated erroneously. SCL = high duration maintained SCL VIH SCL = low detected SDA IRIC [1] Judgement that SCL = low [2] IRIC clearance Figure 15-24 IRIC Flag Clearance in WAIT = 1 Status Rev. 6.00 Feb 22, 2005 page 596 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) * Notes on ICDR Reads and ICCR Access in Slave Transmit Mode In a transmit operation in the slave mode of the I2C bus interface, do not read the ICDR register or read or write to the ICCR register during the period indicated by the shaded portion in figure 15-25. Normally, when interrupt processing is triggered in synchronization with the rising edge of the 9th clock cycle, the period in question has already elapsed when the transition to interrupt processing takes place, so there is no problem with reading the ICDR register or reading or writing to the ICCR register. To ensure that the interrupt processing is performed properly, one of the following two conditions should be applied. (1) Make sure that reading received data from the ICDR register, or reading or writing to the ICCR register, is completed before the next slave address receive operation starts. (2) Monitor the BC2 to BC0 counter in the ICMR register and, when the value of BC2 to BC0 is 000 (8th or 9th clock cycle), allow a waiting time of at least 2 transfer clock cycles in order to involve the problem period in question before reading from the ICDR register, or reading or writing to the ICCR register. Waveforms if problem occurs SDA SCL TRS R/W 8 Address received Period when ICDR reads and ICCR reads and writes are prohibited (6 system clock cycles) A 9 Data transmission ICDR write Bit 7 Detection of 9th clock cycle rising edge Figure 15-25 ICDR Read and ICCR Access Timing in Slave Transmit Mode Rev. 6.00 Feb 22, 2005 page 597 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) * Notes on TRS Bit Setting in Slave Mode From the detection of the rising edge of the 9th clock cycle or of a stop condition to when the rising edge of the next SCL pin signal is detected (the period indicated as (a) in figure 15-26) in the slave mode of the I2C bus interface, the value set in the TRS bit in the ICCR register is effective immediately. However, at other times (indicated as (b) in figure 15-26) the value set in the TRS bit is put on hold until the next rising edge of the 9th clock cycle or stop condition is detected, rather than taking effect immediately. This results in the actual internal value of the TRS bit remaining 1 (transmit mode) and no acknowledge bit being sent at the 9th clock cycle address receive completion in the case of an address receive operation following a restart condition input with no stop condition intervening. When receiving an address in the slave mode, clear the TRS bit to 0 during the period indicated as (a) in figure 15-26. To cancel the holding of the SCL bit low by the wait function in the slave mode, clear the TRS bit to 0 and then perform a dummy read of the ICDR register. Restart condition (a) SDA SCL TRS 8 9 1 2 3 4 5 6 7 8 (b) A 9 Data transmission Address reception TRS bit setting hold time ICDR dummy read TRS bit set Detection of 9th clock cycle rising edge Detection of 9th clock cycle rising edge Figure 15-26 TRS Bit Setting Timing in Slave Mode Rev. 6.00 Feb 22, 2005 page 598 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) * Notes on ICDR Reads in Transmit Mode and ICDR Writes in Receive Mode When attempting to read ICDR in the transmit mode (TRS = 1) or write to ICDR in the receive mode (TRS = 0) under certain conditions, the SCL pin may not be held low after the completion of the transmit or receive operation and a clock may not be output to the SCL bus line before the ICDR register access operation can take place properly. When accessing ICDR, always change the setting to the transmit mode before performing a read operation, and always change the setting to the receive mode before performing a write operation. * Notes on ACKE Bit and TRS Bit in Slave Mode When using the I2C bus interface, if an address is received in the slave mode immediately after 1 is received as an acknowledge bit (ACKB = 1) in the transmit mode (TRS = 1), an interrupt may be generated at the rising edge of the 9th clock cycle if the address does not match. When performing slave mode operations using the IIC bus interface module, make sure to do the following. (1) When a 1 is received as an acknowledge bit for the final transmit data after completing a series of transmit operations, clear the ACKE bit in the ICCR register to 0 to initialize the ACKB bit to 0. (2) In the slave mode, change the setting to the receive mode (TRS = 0) before the start condition is input. To ensure that the switch from the slave transmit mode to the slave receive mode is accomplished properly, end the transmission as described in figure 15-17. * Notes on Arbitration Lost in Master Mode The I2C bus interface recognizes the data in transmit/receive frame as an address when arbitration is lost in master mode and a transition to slave receive mode is automatically carried out. When arbitration is lost not in the first frame but in the second frame or subsequent frame, transmit/receive data that is not an address is compared with the value set in the SAR or SARX register as an address. If the receive data matches with the address in the SAR or SARX register, the I2C bus interface erroneously recognizes that the address call has occurred. (See figure 15-27.) In multi-master mode, a bus conflict could happen. When The I2C bus interface is operated in master mode, check the state of the AL bit in the ICSR register every time after one frame of data has been transmitted or received. When arbitration is lost during transmitting the second frame or subsequent frame, take avoidance measures. Rev. 6.00 Feb 22, 2005 page 599 of 1484 REJ09B0103-0600 Section 15 I2C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630) * Arbitration is lost * The AL flag in ICSR is set to 1 I2C bus interface (Master transmit mode) S SLA R/W A Transmit data match Transmit timing match DATA1 Transmit data does not match Other device (Master transmit mode) S SLA R/W A DATA2 A DATA3 A Data contention bus interface (Slave receive mode) I 2C S SLA R/W A SLA R/W A DATA4 A * Receive address is ignored * Automatically transferred to slave receive mode * Receive data is recognized as an address * When the receive data matches to the address set in the SAR or SARX register, the I2C bus interface operates as a slave device. Figure 15-27 Diagram of Erroneous Operation when Arbitration is Lost Though it is prohibited in the normal I2C protocol, the same problem may occur when the MST bit is erroneously set to 1 and a transition to master mode is occurred during data transmission or reception in slave mode. In multi-master mode, pay attention to the setting of the MST bit when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to 1 according to the order below. (a) Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting the MST bit. (b) Set the MST bit to 1. (c) To confirm that the bus was not entered to the busy state while the MST bit is being set, check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been set. Note: Above restriction can be cleared by setting bits FNC1 and FNC0 in the ICXR register. Rev. 6.00 Feb 22, 2005 page 600 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Section 16 Controller Area Network (HCAN) Notes: The H8S/2635 Group is not equipped with a DTC. Only a single HCAN channel, HCAN0, is implemented in the H8S/2635 Group. 16.1 Overview The HCAN is a module for controlling a controller area network (CAN) for realtime communication in vehicular and industrial equipment systems, etc. The chip has a 2-channel onchip HCAN module. Reference: Bosch CAN Specification Version 2.0, 1991, Robert Bosch GmbH 16.1.1 Features * CAN version: Bosch 2.0B active compatible Communication systems: NRZ (Non-Return to Zero) system (with bit-stuffing function) Broadcast communication system Transmission path: Bidirectional 2-wire serial communication Communication speed: Max. 1 Mbps Data length: 0 to 8 bytes * Number of channel: 2 (HCAN0, HCAN1) * Data buffers: 16 per channel (one receive-only buffer and 15 buffers settable for transmission/reception) * Data transmission: Choice of two methods: Mailbox (buffer) number order (low-to-high) Message priority (identifier) high-to-low order * Data reception: Two methods: Message identifier match (transmit/receive-setting buffers) Reception with message identifier masked (receive-only) * CPU interrupts: Two interrupt vectors for 12 interrupt causes per channel: Error interrupt Reset processing interrupt Message reception interrupt (mailbox 1 to 15) Message reception interrupt (mailbox 0) Message transmission interrupt Rev. 6.00 Feb 22, 2005 page 601 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) * HCAN operating modes: Support for various modes: Hardware reset Software reset Normal status (error-active, error-passive) Bus off status HCAN configuration mode HCAN sleep mode HCAN halt mode * Other features: DTC can be activated by message reception mailbox (HCAN mailbox 0 only) Rev. 6.00 Feb 22, 2005 page 602 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.1.2 Block Diagram Figure 16-1 shows a block diagram of the HCAN. HCAN0 MBI Message buffer Mailboxes Message control Message data MC0 to MC15, MD0 to MD15 LAFM (CDLC) CAN Data Link Controller Bosch CAN 2.0B active HTxD0 Tx buffer MPI Microprocessor interface Peripheral address bus Rx buffer HRxD0 Peripheral data bus CPU interface Control register Status register HCAN1 MBI Message buffer Mailboxes Message control Message data MC0 to MC15, MD0 to MD15 (CDLC) CAN Data Link Controller Bosch CAN 2.0B active HTxD1 LAFM Tx buffer MPI Microprocessor interface CPU interface Control register Status register Rx buffer HRxD1 Figure 16-1 HCAN Block Diagram Rev. 6.00 Feb 22, 2005 page 603 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Message Buffer Interface (MBI): The MBI, consisting of mailboxes and a local acceptance filter mask (LAFM), stores CAN transmit/receive messages (identifiers, data, etc.). Transmit messages are written by the CPU. For receive messages, the data received by the CDLC is stored automatically. Microprocessor Interface (MPI): The MPI, consisting of a bus interface, control register, status register, etc., controls HCAN internal data, statuses, and so forth. CAN Data Link Controller (CDLC): The CDLC performs transmission and reception of messages conforming to the Bosch CAN Ver. 2.0B active standard (data frames, remote frames, error frames, overload frames, inter-frame spacing), as well as CRC checking, bus arbitration, and other functions. 16.1.3 Pin Configuration Table 16-1 shows the HCAN's pins. When using HCAN pins, settings must be made in the HCAN configuration mode (during initialization: MCR0 = 1 and GSR3 = 1). Table 16-1 HCAN Pins Channel 0 Name HCAN transmit data pin 0 HCAN receive data pin 0 1* HCAN transmit data pin 1 HCAN receive data pin 1 Abbreviation HTxD0 HRxD0 HTxD1 HRxD1 Input/Output Output Input Output Input Function Channel 0 CAN bus transmission pin Channel 0 CAN bus reception pin Channel 1 CAN bus transmission pin Channel 1 CAN bus reception pin Note: * The HCAN1 is not supported by the H8S/2635 and H8S/2634. A bus driver is necessary between the pins and the CAN bus. A HA13721 compatible model is recommended. Rev. 6.00 Feb 22, 2005 page 604 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.1.4 Register Configuration Table 16-2 lists the HCAN's registers. Table 16-2 HCAN Registers Channel 0 Name Master control register General status register Bit configuration register Mailbox configuration register Transmit wait register Transmit wait cancel register Transmit acknowledge register Abort acknowledge register Receive complete register Remote request register Interrupt register Mailbox interrupt mask register Interrupt mask register Receive error counter Transmit error counter Unread message status register Local acceptance filter mask L Local acceptance filter mask H Abbreviation MCR GSR BCR MBCR TXPR TXCR TXACK ABACK RXPR RFPR IRR MBIMR IMR REC TEC UMSR LAFML LAFMH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W Initial Value H'01 H'0C Address*1 Access Size H'F800 H'F801 8 bits 16 bits 8 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8 bits 16 bits 8 bits 8/16 bits 8/16 bits 8/16 bits H'0000 H'F802 H'0100 H'F804 H'0000 H'F806 H'0000 H'F808 H'0000 H'F80A H'0000 H'F80C H'0000 H'F80E H'0000 H'F810 H'0100 H'F812 H'FFFF H'F814 H'FEFF H'F816 H'00 H'00 H'F818 H'F819 H'0000 H'F81A H'0000 H'F81C H'0000 H'F81E Rev. 6.00 Feb 22, 2005 page 605 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Initial Value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Access Address*1 Size H'F820 H'F828 H'F830 H'F838 H'F840 H'F848 H'F850 H'F858 H'F860 H'F868 H'F870 H'F878 H'F880 H'F888 H'F890 H'F898 H'F8B0 H'F8B8 H'F8C0 H'F8C8 H'F8D0 H'F8D8 H'F8E0 H'F8E8 H'F8F0 H'F8F8 H'F900 H'F908 H'F910 H'F918 H'F920 H'F928 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits Channel Name 0 Message control 0 [1:8] Message control 1 [1:8] Message control 2 [1:8] Message control 3 [1:8] Message control 4 [1:8] Message control 5 [1:8] Message control 6 [1:8] Message control 7 [1:8] Message control 8 [1:8] Message control 9 [1:8] Message control 10 [1:8] Message control 11 [1:8] Message control 12 [1:8] Message control 13 [1:8] Message control 14 [1:8] Message control 15 [1:8] Message data 0 [1:8] Message data 1 [1:8] Message data 2 [1:8] Message data 3 [1:8] Message data 4 [1:8] Message data 5 [1:8] Message data 6 [1:8] Message data 7 [1:8] Message data 8 [1:8] Message data 9 [1:8] Message data 10 [1:8] Message data 11 [1:8] Message data 12 [1:8] Message data 13 [1:8] Message data 14 [1:8] Message data 15 [1:8] Abbreviation R/W MC0 [1:8] MC1 [1:8] MC2 [1:8] MC3 [1:8] MC4 [1:8] MC5 [1:8] MC6 [1:8] MC7 [1:8] MC8 [1:8] MC9 [1:8] MC10 [1:8] MC11 [1:8] MC12 [1:8] MC13 [1:8] MC14 [1:8] MC15 [1:8] MD0 [1:8] MD1 [1:8] MD2 [1:8] MD3 [1:8] MD4 [1:8] MD5 [1:8] MD6 [1:8] MD7 [1:8] MD8 [1:8] MD9 [1:8] MD10 [1:8] MD11 [1:8] MD12 [1:8] MD13 [1:8] MD14 [1:8] MD15 [1:8] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 6.00 Feb 22, 2005 page 606 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Abbreviation MCR GSR BCR MBCR TXPR TXCR TXACK ABACK RXPR RFPR IRR MBIMR IMR REC TEC UMSR LAFML LAFMH Initial Value H'01 H'0C Channel 1* 2 Name Master control register General status register Bit configuration register Mailbox configuration register Transmit wait register Transmit wait cancel register Transmit acknowledge register Abort acknowledge register Receive complete register Remote request register Interrupt register Mailbox interrupt mask register Interrupt mask register Receive error counter Transmit error counter Unread message status register Local acceptance filter mask L Local acceptance filter mask H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W Address*1 Access Size H'FA00 H'FA01 8 bits 16 bits 8 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8 bits 16 bits 8 bits 8/16 bits 8/16 bits 8/16 bits H'0000 H'FA02 H'0100 H'FA04 H'0000 H'FA06 H'0000 H'FA08 H'0000 H'FA0A H'0000 H'FA0C H'0000 H'FA0E H'0000 H'FA10 H'0100 H'FA12 H'FFFF H'FA14 H'FEFF H'FA16 H'00 H'00 H'FA18 H'FA19 H'0000 H'FA1A H'0000 H'FA1C H'0000 H'FA1E Rev. 6.00 Feb 22, 2005 page 607 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Initial Value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined H'FF Access Address*1 Size H'FA20 H'FA28 H'FA30 H'FA38 H'FA40 H'FA48 H'FA50 H'FA58 H'FA60 H'FA68 H'FA70 H'FA78 H'FA80 H'FA88 H'FA90 H'FA98 H'FAB0 H'FAB8 H'FAC0 H'FAC8 H'FAD0 H'FAD8 H'FAE0 H'FAE8 H'FAF0 H'FAF8 H'FB00 H'FB08 H'FB10 H'FB18 H'FB20 H'FB28 H'FDEA 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits Channel Name 2 Message control 0 [1:8] 1* Message control 1 [1:8] Message control 2 [1:8] Message control 3 [1:8] Message control 4 [1:8] Message control 5 [1:8] Message control 6 [1:8] Message control 7 [1:8] Message control 8 [1:8] Message control 9 [1:8] Message control 10 [1:8] Message control 11 [1:8] Message control 12 [1:8] Message control 13 [1:8] Message control 14 [1:8] Message control 15 [1:8] Message data 0 [1:8] Message data 1 [1:8] Message data 2 [1:8] Message data 3 [1:8] Message data 4 [1:8] Message data 5 [1:8] Message data 6 [1:8] Message data 7 [1:8] Message data 8 [1:8] Message data 9 [1:8] Message data 10 [1:8] Message data 11 [1:8] Message data 12 [1:8] Message data 13 [1:8] Message data 14 [1:8] Message data 15 [1:8] All Module stop control register C Abbreviation R/W MC0 [1:8] MC1 [1:8] MC2 [1:8] MC3 [1:8] MC4 [1:8] MC5 [1:8] MC6 [1:8] MC7 [1:8] MC8 [1:8] MC9 [1:8] MC10 [1:8] MC11 [1:8] MC12 [1:8] MC13 [1:8] MC14 [1:8] MC15 [1:8] MD0 [1:8] MD1 [1:8] MD2 [1:8] MD3 [1:8] MD4 [1:8] MD5 [1:8] MD6 [1:8] MD7 [1:8] MD8 [1:8] MD9 [1:8] MD10 [1:8] MD11 [1:8] MD12 [1:8] MD13 [1:8] MD14 [1:8] MD15 [1:8] MSTPCRC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Notes: 1. Lower 16 bits of the address. 2. The HCAN1 is not supported by the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 608 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.2 16.2.1 Register Descriptions Master Control Register (MCR) The master control register (MCR) is an 8-bit readable/writable register that controls the CAN interface. MCR Bit: Initial value: R/W: 7 MCR7 0 R/W 6 -- 0 R 5 MCR5 0 R/W 4 -- 0 R 3 -- 0 R 2 MCR2 0 R/W 1 MCR1 0 R/W 0 MCR0 1 R/W Bit 7--HCAN Sleep Mode Release (MCR7): Enables or disables HCAN sleep mode release by bus operation. Bit 7: MCR7 0 1 Description HCAN sleep mode release by CAN bus operation disabled HCAN sleep mode release by CAN bus operation enabled (Initial value) Bit 6--Reserved: This bit always reads 0. The write value should always be 0. Bit 5--HCAN Sleep Mode (MCR5): Enables or disables HCAN sleep mode transition. Bit 5: MCR5 0 1 Description HCAN sleep mode released Transition to HCAN sleep mode enabled (Initial value) Bits 4 and 3--Reserved: These bits always read 0. The write value should always be 0. Bit 2--Message Transmission Method (MCR2): Selects the transmission method for transmit messages. Bit 2: MCR2 0 1 Description Transmission order determined by message identifier priority (Initial value) Transmission order determined by mailbox (buffer) number priority (TXPR1 > TXPR15) Rev. 6.00 Feb 22, 2005 page 609 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Bit 1--Halt Request (MCR1): Controls halting of the HCAN module. Bit 1: MCR1 0 1 Description HCAN normal operating mode HCAN halt mode transition request (Initial value) Bit 0--Reset Request (MCR0): Controls resetting of the HCAN module. Bit 0: MCR0 0 Description Normal operating mode (MCR0 = 0 and GSR3 = 0) [Setting condition] * 1 When 0 is written after an HCAN reset (Initial value) HCAN reset mode transition request In order for GSR3 to change from 1 to 0 after 0 is written to MCR0, time is required before the HCAN is internally reset. There is consequently a delay before GSR3 is cleared to 0 after MCR0 is cleared to 0. 16.2.2 General Status Register (GSR) The general status register (GSR) is an 8-bit readable register that indicates the status of the CAN bus. GSR Bit: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 GSR3 1 R 2 GSR2 1 R 1 GSR1 0 R 0 GSR0 0 R Bits 7 to 4--Reserved: These bits always read 0. Rev. 6.00 Feb 22, 2005 page 610 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Bit 3--Reset Status Bit (GSR3): Indicates whether the HCAN module is in the normal operating state or the reset state. Writes are invalid. Bit 3: MCR3 0 Description Normal operating state [Setting condition] * 1 After an HCAN internal reset Configuration mode [Reset condition] * MCR0 reset mode and sleep mode (Initial value) Bit 2--Message Transmission Status Flag (GSR2): Flag that indicates whether the module is currently in the message transmission period. The "message transmission period" is the period from the start of message transmission (SOF) until the end of a 3-bit intermission interval after EOF (End of Frame). Writes are invalid. Bit 2: GSR2 0 1 Description Message transmission period [Reset condition] * Idle period (Initial value) Bit 1--Transmit/Receive Warning Flag (GSR1): Flag that indicates an error warning. Writes are invalid. Bit 1: GSR1 0 1 Description [Reset condition] * When TEC < 96 and REC < 96 or TEC 256 (Initial value) When TEC 96 or REC 96 Bit 0--Bus Off Flag (GSR0): Flag that indicates the bus off state. Writes are invalid. Bit 0: GSR0 0 1 Description [Reset condition] * Recovery from bus off state (Initial value) When TEC 256 (bus off state) Rev. 6.00 Feb 22, 2005 page 611 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.2.3 Bit Configuration Register (BCR) The bit configuration register (BCR) is a 16-bit readable/writable register that is used to set CAN bit timing parameters and the baud rate prescaler. BCR Bit: Initial value: R/W: Bit: Initial value: R/W: 15 BCR7 0 R/W 7 BCR15 0 R/W 14 BCR6 0 R/W 6 BCR14 0 R/W 13 BCR5 0 R/W 5 BCR13 0 R/W 12 BCR4 0 R/W 4 BCR12 0 R/W 11 BCR3 0 R/W 3 BCR11 0 R/W 10 BCR2 0 R/W 2 BCR10 0 R/W 9 BCR1 0 R/W 1 BCR9 0 R/W 8 BCR0 0 R/W 0 BCR8 0 R/W Bits 15 and 14--Resynchronization Jump Width (SJW): These bits set the bit synchronization range. Bit 15: BCR7 0 1 Bit 14: BCR6 0 1 0 1 Description Bit synchronization width = 1 time quantum Bit synchronization width = 2 time quanta Bit synchronization width = 3 time quanta Bit synchronization width = 4 time quanta (Initial value) Bits 13 to 8--Baud Rate Prescaler (BRP): These bits are used to set the CAN bus baud rate. Bit 13: BCR5 0 0 0 1 Bit 12: BCR4 0 0 0 1 Bit 11: BCR3 0 0 0 1 Bit 10: BCR2 0 0 0 1 Bit 9: BCR1 0 0 1 1 Bit 8: BCR0 0 1 0 1 Description 2 x system clock 4 x system clock 6 x system clock 128 x system clock (Initial value) Rev. 6.00 Feb 22, 2005 page 612 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Bit 7--Bit Sample Point (BSP): Sets the point at which data is sampled. Bit 7: BCR15 0 1 Description Bit sampling at one point (end of time segment 1 (TSEG1)) (Initial value) Bit sampling at three points (end of time segment 1 (TSEG1) and preceding and following time quanta) Bits 6 to 4--Time Segment 2 (TSEG2): These bits are used to set the segment for correcting 1bit time error. A value from 2 to 8 can be set. Bit 6: BCR14 0 Bit 5: BCR13 0 1 1 0 1 Bit 4: BCR12 0 1 0 1 0 1 0 1 Description Setting prohibited TSEG2 = 2 time quanta TSEG2 = 3 time quanta TSEG2 = 4 time quanta TSEG2 = 5 time quanta TSEG2 = 6 time quanta TSEG2 = 7 time quanta TSEG2 = 8 time quanta (Initial value) Bits 3 to 0--Time Segment 1 (TSEG1): These bits are used to set the segment for absorbing output buffer, CAN bus, and input buffer delay. A value from 1 to 16 can be set. Bit 3: BCR11 0 0 0 0 0 1 Bit 2: BCR10 0 0 0 0 1 1 Bit 1: BCR9 0 0 1 1 0 1 Bit 0: BCR8 0 1 0 1 0 1 Description Setting prohibited Setting prohibited Setting prohibited TSEG1 = 4 time quanta TSEG1 = 5 time quanta TSEG1 = 16 time quanta (Initial value) Rev. 6.00 Feb 22, 2005 page 613 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.2.4 Mailbox Configuration Register (MBCR) The mailbox configuration register (MBCR) is a 16-bit readable/writable register that is used to set mailbox (buffer) transmission/reception. MBCR Bit: Initial value: R/W: Bit: Initial value: R/W: 15 MBCR7 14 MBCR6 13 MBCR5 12 MBCR4 11 MBCR3 10 MBCR2 9 MBCR1 8 -- 1 R 0 MBCR8 0 R/W 7 0 R/W 0 R/W 6 0 R/W 0 R/W 5 0 R/W 0 R/W 4 0 R/W 0 R/W 3 0 R/W 0 R/W 2 0 R/W 0 R/W 1 MBCR9 MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 0 R/W 0 R/W Bits 15 to 9 and 7 to 0--Mailbox Setting Register (MBCR7 to MBCR1, MBCR15 to MBCR8): These bits set the polarity of the corresponding mailboxes. Bit x: MBCRx 0 1 Description Corresponding mailbox is set for transmission Corresponding mailbox is set for reception (x = 15 to 9, 7 to 0) (Initial value) Bit 8--Reserved: This bit always reads 1. The write value should always be 1. Rev. 6.00 Feb 22, 2005 page 614 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.2.5 Transmit Wait Register (TXPR) The transmit wait register (TXPR) is a 16-bit readable/writable register that is used to set a transmit wait after a transmit message is stored in a mailbox (buffer) (CAN bus arbitration wait). TXPR Bit: Initial value: R/W: Bit: Initial value: R/W: 15 TXPR7 0 R/W 7 0 R/W 14 TXPR6 0 R/W 6 0 R/W 13 TXPR5 0 R/W 5 0 R/W 12 TXPR4 0 R/W 4 0 R/W 11 TXPR3 0 R/W 3 0 R/W 10 TXPR2 0 R/W 2 0 R/W 9 TXPR1 0 R/W 1 0 R/W 8 -- 0 R 0 TXPR8 0 R/W TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 Bits 15 to 9 and 7 to 0--Transmit Wait Register (TXPR7 to TXPR1, TXPR15 to TXPR8): These bits set a transmit wait for the corresponding mailboxes. Bit x: TXPRx 0 Description Transmit message idle state in corresponding mailbox [Clearing condition] * 1 Message transmission completion and cancellation completion Transmit message transmit wait in corresponding mailbox (CAN bus arbitration) (x = 15 to 9, 7 to 0) (Initial value) Bit 8--Reserved: This bit always reads 0. The write value should always be 0. Rev. 6.00 Feb 22, 2005 page 615 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.2.6 Transmit Wait Cancel Register (TXCR) The transmit wait cancel register (TXCR) is a 16-bit readable/writable register that controls cancellation of transmit wait messages in mailboxes (buffers). TXCR Bit: Initial value: R/W: Bit: Initial value: R/W: 15 TXCR7 0 R/W 7 0 R/W 14 TXCR6 0 R/W 6 0 R/W 13 TXCR5 0 R/W 5 0 R/W 12 TXCR4 0 R/W 4 0 R/W 11 TXCR3 0 R/W 3 0 R/W 10 TXCR2 0 R/W 2 0 R/W 9 TXCR1 0 R/W 1 0 R/W 8 -- 0 R 0 TXCR8 0 R/W TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 (x = 15 to 9, 7 to 0) Bits 15 to 9 and 7 to 0--Transmit Wait Cancel Register (TXCR7 to TXCR1, TXCR15 to TXCR8): These bits control cancellation of transmit wait messages in the corresponding HCAN mailboxes. Bit x: TXCRx 0 Description Transmit message cancellation idle state in corresponding mailbox (Initial value) [Clearing condition] * 1 Completion of TXPR clearing (when transmit message is canceled normally) (x = 15 to 9, 7 to 0) TXPR cleared for corresponding mailbox (transmit message cancellation) Bit 8--Reserved: This bit always reads 0. The write value should always be 0. Rev. 6.00 Feb 22, 2005 page 616 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.2.7 Transmit Acknowledge Register (TXACK) The transmit acknowledge register (TXACK) is a 16-bit readable/writable register containing status flags that indicate normal transmission of mailbox (buffer) transmit messages. TXACK Bit: Initial value: R/W: Bit: Initial value: R/W: 15 TXACK7 14 TXACK6 13 TXACK5 12 TXACK4 11 TXACK3 10 TXACK2 9 TXACK1 8 -- 0 R 0 TXACK8 0 R/(W)* 7 0 R/(W)* 0 R/(W)* 6 0 R/(W)* 0 R/(W)* 5 0 R/(W)* 0 R/(W)* 4 0 R/(W)* 0 R/(W)* 3 0 R/(W)* 0 R/(W)* 2 0 R/(W)* 0 R/(W)* 1 0 R/(W)* TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 0 R/(W)* Note: * Only a write of 1 is permitted, to clear the flag. Bits 15 to 9 and 7 to 0--Transmit Acknowledge Register (TXACK7 to TXACK1, TXACK15 to TXACK8): These bits indicate that a transmit message in the corresponding HCAN mailbox has been transmitted normally. Bit x: TXACKx 0 1 Description [Clearing condition] * Writing 1 (Initial value) (x = 15 to 9, 7 to 0) Completion of message transmission for corresponding mailbox Bit 8--Reserved: This bit always reads 0. The write value should always be 0. Rev. 6.00 Feb 22, 2005 page 617 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.2.8 Abort Acknowledge Register (ABACK) The abort acknowledge register (ABACK) is a 16-bit readable/writable register containing status flags that indicate normal cancellation (aborting) of a mailbox (buffer) transmit messages. ABACK Bit: Initial value: R/W: Bit: Initial value: R/W: 15 ABACK7 14 ABACK6 13 ABACK5 12 ABACK4 11 ABACK3 10 ABACK2 9 ABACK1 8 -- 0 R 0 ABACK8 0 R/(W)* 7 0 R/(W)* 0 R/(W)* 6 0 R/(W)* 0 R/(W)* 5 0 R/(W)* 0 R/(W)* 4 0 R/(W)* 0 R/(W)* 3 0 R/(W)* 0 R/(W)* 2 0 R/(W)* 0 R/(W)* 1 0 R/(W)* ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 0 R/(W)* Note: * Only a write of 1 is permitted, to clear the flag. Bits 15 to 9 and 7 to 0--Abort Acknowledge Register (ABACK7 to ABACK1, ABACK15 to ABACK8): These bits indicate that a transmit message in the corresponding mailbox has been canceled (aborted) normally. Bit x: ABACKx 0 1 Description [Clearing condition] * Writing 1 (Initial value) (x = 15 to 9, 7 to 0) Completion of transmit message cancellation for corresponding mailbox Bit 8--Reserved: This bit always reads 0. The write value should always be 0. Rev. 6.00 Feb 22, 2005 page 618 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.2.9 Receive Complete Register (RXPR) The receive complete register (RXPR) is a 16-bit readable/writable register containing status flags that indicate normal reception of messages (data frame or remote frame) in mailboxes (buffers). In the case of remote frame reception, the corresponding remote request register (RFPR) is also set simultaneously. RXPR Bit: Initial value: R/W: Bit: Initial value: R/W: 15 RXPR7 0 R/(W)* 7 0 R/(W)* 14 RXPR6 0 R/(W)* 6 0 R/(W)* 13 RXPR5 0 R/(W)* 5 0 R/(W)* 12 RXPR4 0 R/(W)* 4 0 R/(W)* 11 RXPR3 0 R/(W)* 3 0 R/(W)* 10 RXPR2 0 R/(W)* 2 0 R/(W)* 9 RXPR1 0 R/(W)* 1 0 R/(W)* 8 RXPR0 0 R/(W)* 0 RXPR8 0 R/(W)* RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 Note: * Only a write of 1 is permitted, to clear the flag. Bits 15 to 0--Receive Complete Register (RXPR7 to RXPR0, RXPR15 to RXPR8): These bits indicate that a receive message has been received normally in the corresponding mailbox. Bit x: RXPRx 0 1 Description [Clearing condition] * Writing 1 (Initial value) Completion of message (data frame or remote frame) reception in corresponding mailbox (x = 15 to 0) Rev. 6.00 Feb 22, 2005 page 619 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.2.10 Remote Request Register (RFPR) The remote request register (RFPR) is a 16-bit readable/writable register containing status flags that indicate normal reception of remote frames in mailboxes (buffers). When a bit in this register is set, the corresponding reception complete bit is set simultaneously. RFPR Bit: Initial value: R/W: Bit: Initial value: R/W: 15 RFPR7 0 R/(W)* 7 0 R/(W)* 14 RFPR6 0 R/(W)* 6 0 R/(W)* 13 RFPR5 0 R/(W)* 5 0 R/(W)* 12 RFPR4 0 R/(W)* 4 0 R/(W)* 11 RFPR3 0 R/(W)* 3 0 R/(W)* 10 RFPR2 0 R/(W)* 2 0 R/(W)* 9 RFPR1 0 R/(W)* 1 0 R/(W)* 8 RFPR0 0 R/(W)* 0 RFPR8 0 R/(W)* RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 Note: * Only a write of 1 is permitted, to clear the flag. Bits 15 to 0--Remote Request Register (RFPR7 to RFPR0, RFPR15 to RFPR8): These bits indicate that a remote frame has been received normally in the corresponding mailbox. Bit x: RFPRx 0 1 Description [Clearing condition] * Writing 1 (Initial value) (x = 15 to 0) Completion of remote frame reception in corresponding mailbox Rev. 6.00 Feb 22, 2005 page 620 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.2.11 Interrupt Register (IRR) The interrupt register (IRR) is a 16-bit readable/writable register containing status flags for the various interrupt sources. IRR Bit: Initial value: R/W: Bit: Initial value: R/W: 15 IRR7 0 R/(W)* 7 -- 0 -- 14 IRR6 0 R/(W)* 6 -- 0 -- 13 IRR5 0 R/(W)* 5 -- 0 -- 12 IRR4 0 R/(W)* 4 IRR12 0 R/(W)* 11 IRR3 0 R/(W)* 3 -- 0 -- 10 IRR2 0 R 2 -- 0 -- 9 IRR1 0 R 1 IRR9 0 R 8 IRR0 1 R/(W)* 0 IRR8 0 R/(W)* Note: * Only a write of 1 is permitted, to clear the flag. Bit 15--Overload Frame Interrupt Flag (IRR7): Status flag indicating that the HCAN has transmitted an overload frame. Bit 15: IRR7 0 1 Description [Clearing condition] * Writing 1 (Initial value) Overload frame transmission [Setting condition] * When overload frame is transmitted Rev. 6.00 Feb 22, 2005 page 621 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Bit 14--Bus Off Interrupt Flag (IRR6): Status flag indicating the bus off state caused by the transmit error counter. Bit 14: IRR6 0 1 Description [Clearing condition] * Writing 1 (Initial value) Bus off state caused by transmit error [Setting condition] * When TEC 256 Bit 13--Error Passive Interrupt Flag (IRR5): Status flag indicating the error passive state caused by the transmit/receive error counter. Bit 13: IRR5 0 1 Description [Clearing condition] * Writing 1 (Initial value) Error passive state caused by transmit/receive error [Setting condition] * When TEC 128 or REC 128 Bit 12--Receive Overload Warning Interrupt Flag (IRR4): Status flag indicating the error warning state caused by the receive error counter. Bit 12: IRR4 0 1 Description [Clearing condition] * Writing 1 (Initial value) Error warning state caused by receive error [Setting condition] * When REC 96 Rev. 6.00 Feb 22, 2005 page 622 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Bit 11--Transmit Overload Warning Interrupt Flag (IRR3): Status flag indicating the error warning state caused by the transmit error counter. Bit 11: IRR3 0 1 Description [Clearing condition] * Writing 1 (Initial value) Error warning state caused by transmit error [Setting condition] * When TEC 96 Bit 10--Remote Frame Request Interrupt Flag (IRR2): Status flag indicating that a remote frame has been received in a mailbox (buffer). Bit 10: IRR2 0 Description [Clearing condition] * 1 Clearing of all bits in RFPR (remote request register) of mailbox for which receive interrupt requests are enabled by MBIMR (Initial value) Remote frame received and stored in mailbox [Setting conditions] * When remote frame reception is completed, when corresponding MBIMR = 0 Bit 9--Receive Message Interrupt Flag (IRR1): Status flag indicating that a mailbox (buffer) receive message has been received normally. Bit 9: IRR1 0 Description [Clearing condition] * 1 Clearing of all bits in RXPR (receive complete register) of mailbox for which receive interrupt requests are enabled by MBIMR (Initial value) Data frame or remote frame received and stored in mailbox [Setting conditions] * When data frame or remote frame reception is completed, when corresponding MBIMR = 0 Rev. 6.00 Feb 22, 2005 page 623 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Bit 8--Reset Interrupt Flag (IRR0): Status flag indicating that the HCAN module has been reset. This bit cannot be masked in the interrupt mask register (IMR). If this bit is not cleared after reset input or recovery from software standby mode, interrupt handling will be performed as soon as interrupts are enabled by the interrupt controller. Bit 8: IRR0 0 1 Description [Clearing condition] * Writing 1 (Initial value) Hardware reset (HCAN module stop*, software standby) [Setting condition] * When reset processing is completed after a hardware reset (HCAN module stop*, software standby) Note: * After reset or hardware standby release, the module stop bit is initialized to 1, and so the HCAN enters the module stop state. Bits 7 to 5, 3, and 2--Reserved: These bits always read 0. The write value should always be 0. Bit 4--Bus Operation Interrupt Flag (IRR12): Status flag indicating detection of a dominant bit due to bus operation when the HCAN module is in HCAN sleep mode. Bit 4: IRR12 0 Description CAN bus idle state [Clearing condition] * 1 Writing 1 CAN bus operation in HCAN sleep mode [Setting condition] * Bus operation (dominant bit detection) in HCAN sleep mode (Initial value) Rev. 6.00 Feb 22, 2005 page 624 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Bit 1--Unread Interrupt Flag (IRR9): Status flag indicating that a receive message has been overwritten while still unread. Bit 1: IRR9 0 Description [Clearing condition] * 1 Clearing of all bits in UMSR (unread message status register) (Initial value) Unread message overwrite [Setting condition] * When UMSR (unread message status register) is set Bit 0--Mailbox Empty Interrupt Flag (IRR8): Status flag indicating that the next transmit message can be stored in the mailbox. Bit 0: IRR8 0 1 Description [Clearing condition] * Writing 1 (Initial value) Transmit message has been transmitted or aborted, and new message can be stored [Setting condition] * When TXPR (transmit wait register) is cleared by completion of transmission or completion of transmission abort Rev. 6.00 Feb 22, 2005 page 625 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.2.12 Mailbox Interrupt Mask Register (MBIMR) The mailbox interrupt mask register (MBIMR) is a 16-bit readable/writable register containing flags that enable or disable individual mailbox (buffer) interrupt requests. MBIMR Bit: Initial value: R/W: Bit: Initial value: R/W: 15 MBIMR7 14 MBIMR6 13 MBIMR5 12 MBIMR4 11 MBIMR3 10 MBIMR2 9 MBIMR1 8 MBIMR0 1 R/W 7 1 R/W 1 R/W 6 1 R/W 1 R/W 5 1 R/W 1 R/W 4 1 R/W 1 R/W 3 1 R/W 1 R/W 2 1 R/W 1 R/W 1 1 R/W 1 R/W 0 MBIMR8 MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 1 R/W Bits 15 to 0--Mailbox Interrupt Mask (MBIMRx): Flags that enable or disable individual mailbox interrupt requests. Bit x: MBIMRx 0 Description [Transmitting] * * 1 Interrupt request to CPU due to TXPR clearing Interrupt request to CPU due to RXPR setting (Initial value) (x = 15 to 0) [Receiving] Interrupt requests to CPU disabled Rev. 6.00 Feb 22, 2005 page 626 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.2.13 Interrupt Mask Register (IMR) The interrupt mask register (IMR) is a 16-bit readable/writable register containing flags that enable or disable requests by individual interrupt sources. IMR Bit: Initial value: R/W: Bit: Initial value: R/W: 15 IMR7 1 R/W 7 -- 1 R 14 IMR6 1 R/W 6 -- 1 R 13 IMR5 1 R/W 5 -- 1 R 12 IMR4 1 R/W 4 IMR12 1 R/W 11 IMR3 1 R/W 3 -- 1 R 10 IMR2 1 R/W 2 -- 1 R 9 IMR1 1 R/W 1 IMR9 1 R/W 8 -- 0 R 0 IMR8 1 R/W Bit 15--Overload Frame/Bus Off Recovery Interrupt Mask (IMR7): Enables or disables overload frame/bus off recovery interrupt requests. Bit 15: IMR7 0 1 Description Overload frame/bus off recovery interrupt request (OVR0) to CPU by IRR7 enabled Overload frame/bus off recovery interrupt request (OVR0) to CPU by IRR7 disabled (Initial value) Bit 14--Bus Off Interrupt Mask (IMR6): Enables or disables bus off interrupt requests caused by the transmit error counter. Bit 14: IMR6 0 1 Description Bus off interrupt request (ERS0) to CPU by IRR6 enabled Bus off interrupt request (ERS0) to CPU by IRR6 disabled (Initial value) Rev. 6.00 Feb 22, 2005 page 627 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Bit 13--Error Passive Interrupt Mask (IMR5): Enables or disables error passive interrupt requests caused by the transmit/receive error counter. Bit 13: IMR5 0 1 Description Error passive interrupt request (ERS0) to CPU by IRR5 enabled Error passive interrupt request (ERS0) to CPU by IRR5 disabled (Initial value) Bit 12--Receive Overload Warning Interrupt Mask (IMR4): Enables or disables error warning interrupt requests caused by the receive error counter. Bit 12: IMR4 0 1 Description REC error warning interrupt request (OVR0) to CPU by IRR4 enabled REC error warning interrupt request (OVR0) to CPU by IRR4 disabled (Initial value) Bit 11--Transmit Overload Warning Interrupt Mask (IMR3): Enables or disables error warning interrupt requests caused by the transmit error counter. Bit 11: IMR3 0 1 Description TEC error warning interrupt request (OVR0) to CPU by IRR3 enabled TEC error warning interrupt request (OVR0) to CPU by IRR3 disabled (Initial value) Bit 10--Remote Frame Request Interrupt Mask (IMR2): Enables or disables remote frame reception interrupt requests. Bit 10: IMR2 0 1 Description Remote frame reception interrupt request (OVR0) to CPU by IRR2 enabled Remote frame reception interrupt request (OVR0) to CPU by IRR2 disabled (Initial value) Rev. 6.00 Feb 22, 2005 page 628 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Bit 9--Receive Message Interrupt Mask (IMR1): Enables or disables message reception interrupt requests. Bit 9: IMR1 0 1 Description Message reception interrupt request (RM1) to CPU by IRR1 enabled Message reception interrupt request (RM1) to CPU by IRR1 disabled (Initial value) Bit 8--Reserved: The reset flag cannot be masked. This bit always reads 0. The write value should always be 0. Bits 7 to 5, 3, and 2--Reserved: These bits always read 1. The write value should always be 1. Bit 4--Bus Operation Interrupt Mask (IMR12): Enables or disables interrupt requests due to bus operation in sleep mode. Bit 4: IMR12 0 1 Description Bus operation interrupt request (OVR0) to CPU by IRR12 enabled Bus operation interrupt request (OVR0) to CPU by IRR12 disabled (Initial value) Bit 1--Unread Interrupt Mask (IMR9): Enables or disables unread receive message overwrite interrupt requests. Bit 1: IMR9 0 1 Description Unread message overwrite interrupt request (OVR0) to CPU by IRR9 enabled Unread message overwrite interrupt request (OVR0) to CPU by IRR9 disabled (Initial value) Bit 0--Mailbox Empty Interrupt Mask (IMR8): Enables or disables mailbox empty interrupt requests. Bit 0: IMR8 0 1 Description Mailbox empty interrupt request (SLE0) to CPU by IRR8 enabled Mailbox empty interrupt request (SLE0) to CPU by IRR8 disabled (Initial value) Rev. 6.00 Feb 22, 2005 page 629 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.2.14 Receive Error Counter (REC) The receive error counter (REC) is an 8-bit read-only register that functions as a counter indicating the number of receive message errors on the CAN bus. The count value is stipulated in the CAN protocol. REC Bit: Initial value: R/W: 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R 16.2.15 Transmit Error Counter (TEC) The transmit error counter (TEC) is an 8-bit read-only register that functions as a counter indicating the number of transmit message errors on the CAN bus. The count value is stipulated in the CAN protocol. TEC Bit: Initial value: R/W: 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R Rev. 6.00 Feb 22, 2005 page 630 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.2.16 Unread Message Status Register (UMSR) The unread message status register (UMSR) is a 16-bit readable/writable register containing status flags that indicate, for individual mailboxes (buffers), that a received message has been overwritten by a new receive message before being read. When a message is overwritten by a new receive message, the old data is lost. UMSR Bit: Initial value: R/W: Bit: Initial value: R/W: 15 UMSR7 14 UMSR6 13 UMSR5 12 UMSR4 11 UMSR3 10 UMSR2 9 UMSR1 8 UMSR0 0 R/(W)* 7 0 R/(W)* 0 R/(W)* 6 0 R/(W)* 0 R/(W)* 5 0 R/(W)* 0 R/(W)* 4 0 R/(W)* 0 R/(W)* 3 0 R/(W)* 0 R/(W)* 2 0 R/(W)* 0 R/(W)* 1 UMSR9 0 R/(W)* 0 UMSR8 UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 0 R/(W)* 0 R/(W)* Note: * Only 1 can be written, to clear the flag to 0. Bits 15 to 0--Unread Message Status Flags (UMSRx): Status flags indicating that an unread receive message has been overwritten. Bit x: UMSRx 0 1 Description [Clearing condition] * Writing 1 (Initial value) Unread receive message is overwritten by a new message [Setting condition] * When a new message is received before RXPR is cleared Rev. 6.00 Feb 22, 2005 page 631 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.2.17 Local Acceptance Filter Masks (LAFML, LAFMH) The local acceptance filter masks (LAFML, LAFMH) are 16-bit readable/writable registers that filter receive messages to be stored in the receive-only mailbox (MC0, MD0) according to the identifier. In these registers, consist of LAFMH15: MSB to LAFMH5: LSB are 11 standard/extended identifier bits, and LAFMH1: MSB to LAFML0: LSB are 18 extended identifier bits. LAFML Bit: Initial value: R/W: Bit: Initial value: R/W: LAFMH Bit: Initial value: R/W: Bit: Initial value: R/W: 15 LAFMH7 15 LAFML7 14 LAFML6 13 LAFML5 12 LAFML4 11 LAFML3 10 LAFML2 9 LAFML1 8 LAFML0 0 R/W 7 0 R/W 0 R/W 6 0 R/W 0 R/W 5 0 R/W 0 R/W 4 0 R/W 0 R/W 3 0 R/W 0 R/W 2 0 R/W 0 R/W 1 0 R/W 0 R/W 0 LAFML8 LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 0 R/W 14 LAFMH6 13 LAFMH5 12 -- 0 R 4 0 R/W 11 -- 0 R 3 0 R/W 10 -- 0 R 2 0 R/W 9 LAFMH1 8 LAFMH0 0 R/W 7 0 R/W 0 R/W 6 0 R/W 0 R/W 5 0 R/W 0 R/W 1 0 R/W 0 R/W 0 LAFMH8 LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 0 R/W Rev. 6.00 Feb 22, 2005 page 632 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) LAFMH Bits 7 to 0 and 15 to 13--11-Bit Identifier Filter (LAFMH7 to LAFMH5, LAFMH15 to LAFMH8): Filter mask bits for the first 11 bits of the receive message identifier (for both standard and extended identifiers). Bit x: LAFMHx 0 Description Stored in MC0 and MD0 (receive-only mailbox) depending on bit match between MC0 message identifier and receive message identifier (Initial value) Stored in MC0 and MD0 (receive-only mailbox) regardless of bit match between MC0 message identifier and receive message identifier (x = 15 to 0) 1 LAFMH Bits 12 to 10--Reserved: These bits always read 0. The write value should always be 0. LAFMH Bits 9 and 8, LAFML Bits 15 to 0--18-Bit Identifier Filter (LAFMH1, LAFMH0, LAFML7 to LAFML0, LAFML15 to LAFML8): Filter mask bits for the 18 bits of the receive message identifier (extended). Bit x: LAFMHx LAFMLx 0 1 Description Stored in MC0 (receive-only mailbox) depending on bit match between MC0 message identifier and receive message identifier (Initial value) Stored in MC0 (receive-only mailbox) regardless of bit match between MC0 message identifier and receive message identifier (x = 15 to 0) Rev. 6.00 Feb 22, 2005 page 633 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.2.18 Message Control (MC0 to MC15) The message control register sets (MC0 to MC15) consist of eight 8-bit readable/writable registers (MCx[1] to MCx[8]). The HCAN has 16 sets of these registers (MC0 to MC15). The initial value of these registers is undefined, so they must be initialized (by writing 0 or 1). MCx [1] Bit: Initial value: R/W: MCx [2] Bit: Initial value: R/W: MCx [3] Bit: Initial value: R/W: MCx [4] Bit: Initial value: R/W: 7 -- * R/W 6 -- * R/W 5 -- * R/W 4 -- * R/W 3 -- * R/W 2 -- * R/W 1 -- * R/W 0 -- * R/W *:Undefined 7 -- * R/W 6 -- * R/W 5 -- * R/W 4 -- * R/W 3 -- * R/W 2 -- * R/W 1 -- * R/W 0 -- * R/W 7 -- * R/W 6 -- * R/W 5 -- * R/W 4 -- * R/W 3 -- * R/W 2 -- * R/W 1 -- * R/W 0 -- * R/W 7 -- * R/W 6 -- * R/W 5 -- * R/W 4 -- * R/W 3 DLC3 * R/W 2 DLC2 * R/W 1 DLC1 * R/W 0 DLC0 * R/W Rev. 6.00 Feb 22, 2005 page 634 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) MCx [5] Bit: Initial value: R/W: MCx [6] Bit: Initial value: R/W: MCx [7] Bit: Initial value: R/W: MCx [8] Bit: Initial value: R/W: 7 * R/W 6 * R/W 5 * R/W 4 * R/W 3 * R/W 2 * R/W 1 * R/W 0 * R/W *:Undefined (x = 15 to 0) 7 * R/W 6 * R/W 5 * R/W 4 * R/W 3 * R/W 2 * R/W 1 * R/W 0 * R/W 7 * R/W 6 * R/W 5 * R/W 4 * R/W 3 * R/W 2 * R/W 1 * R/W 0 * R/W 7 6 5 4 RTR 3 IDE 2 -- * R/W 1 0 STD_ID2 STD_ID1 STD_ID0 EXD_ID17 EXD_ID16 * R/W * R/W * R/W * R/W * R/W * R/W * R/W STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 MCx[1] Bits 7 to 4--Reserved: The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). Rev. 6.00 Feb 22, 2005 page 635 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) MCx[1] Bits 3 to 0--Data Length Code (DLC): These bits indicate the required length of data frames and remote frames. Bit 3: DLC3 0 Bit 2: DLC2 0 Bit 1: DLC1 0 1 1 0 1 1 0/1 0/1 Bit 0: DLC0 0 1 0 1 0 1 0 1 0/1 Description Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes MCx[2] Bits 7 to 0--Reserved: The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). MCx[3] Bits 7 to 0--Reserved: The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). MCx[4] Bits 7 to 0--Reserved: The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). MCx[6] Bits 7 to 0--Standard Identifier (STD_ID10 to STD_ID3) MCx[5] Bits 7 to 5--Standard Identifier (STD_ID2 to STD_ID0) These bits set the identifier (standard identifier) of data frames and remote frames. Standard identifier SOF ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR IDE SRR STD_IDxx Figure 16-2 Standard identifier Rev. 6.00 Feb 22, 2005 page 636 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) MCx[5] Bit 4--Remote Transmission Request (RTR): Used to distinguish between data frames and remote frames. Bit 4: RTR 0 1 Description Data frame Remote frame MCx[5] Bit 3--Identifier Extension (IDE): Used to distinguish between the standard format and extended format of data frames and remote frames. Bit 3: IDE 0 1 Description Standard format Extended format MCx[5] Bit 2--Reserved: The initial value of this bit is undefined; it must be initialized (by writing 0 or 1). MCx[5] Bits 1 and 0--Extended Identifier (EXD_ID17, EXD_ID16) MCx[8] Bits 7 to 0--Extended Identifier (EXD_ID15 to EXD_ID8) MCx[7] Bits 7 to 0--Extended Identifier (EXD_ID7 to EXD_ID0) These bits set the identifier (extended identifier) of data frames and remote frames. Extended Identifier IDE ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 EXD_IDxx ID4 ID3 ID2 ID1 ID0 RTR R1 EXD_IDxx Figure 16-3 Extended identifier Rev. 6.00 Feb 22, 2005 page 637 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.2.19 Message Data (MD0 to MD15) The message data register sets (MD0 to MD15) consist of eight 8-bit readable/writable registers (MDx[1] to MDx[8]). The HCAN has 16 sets of these registers (MD0 to MD15). The initial value of these registers is undefined, so they must be initialized (by writing 0 or 1). MDx [1] Bit: Initial value: R/W: MDx [2] Bit: Initial value: R/W: MDx [3] Bit: Initial value: R/W: MDx [4] Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 7 * R/W 6 * R/W 5 * R/W 4 * R/W 3 * R/W 2 * R/W 1 * R/W 0 * R/W 7 * R/W 6 * R/W 5 * R/W 4 * R/W 3 * R/W 2 * R/W 1 * R/W 0 * R/W 7 * R/W 6 * R/W 5 * R/W 4 * R/W 3 * R/W 2 * R/W 1 * R/W 0 * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W Rev. 6.00 Feb 22, 2005 page 638 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) MDx [5] Bit: Initial value: R/W: MDx [6] Bit: Initial value: R/W: MDx [7] Bit: Initial value: R/W: MDx [8] Bit: Initial value: R/W: 7 * R/W 6 * R/W 5 * R/W 4 * R/W 3 * R/W 2 * R/W 1 * R/W 0 * R/W *:Undefined (x = 0 to 15) 7 * R/W 6 * R/W 5 * R/W 4 * R/W 3 * R/W 2 * R/W 1 * R/W 0 * R/W 7 * R/W 6 * R/W 5 * R/W 4 * R/W 3 * R/W 2 * R/W 1 * R/W 0 * R/W 7 6 5 4 3 2 1 0 * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W Rev. 6.00 Feb 22, 2005 page 639 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.2.20 Module Stop Control Register C (MSTPCRC) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2* MSTPC1 MSTPC0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Note: * The MSTPC2 is not available and is reserved in the H8S/2635 and H8S/2634. MSTPCRC is an 8-bit readable/writable register that performs module stop mode control. When the MSTPC3 and MSTPC2 bits are set to 1, HCAN0 and 1 operation is stopped at the end of the bus cycle, and module stop mode is entered. Register read/write accesses are not possible in module stop mode. For details, see section 23A.5, 23B.5, Module Stop Mode. MSTPCRC is initialized to H'FF by a reset, and in hardware standby mode. It is not initialized in software standby mode. Bit 3--Module Stop (MSTPC3): Specifies the HCAN module stop mode. Bit 3: MSTPC3 0 1 Description HCAN0 module stop mode is cleared HCAN0 module stop mode is set (Initial value) Bit 2--Module Stop (MSTPC2)*: Specifies the HCAN module stop mode. Note: * The MSTPC2 is not available and is reserved in the H8S/2635 and H8S/2634. Bit 2: MSTPC2 0 1 Description HCAN1 module stop mode is cleared HCAN1 module stop mode is set (Initial value) Rev. 6.00 Feb 22, 2005 page 640 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.3 Operation This LSI device is equipped with 2-channel HCAN modules, which are controlled independently. Both modules have identical specifications, and they are controlled in the same manner. 16.3.1 Hardware and Software Resets The HCAN can be reset by a hardware reset or software reset. Hardware Reset (HCAN Module Stop, Reset*, Hardware*/Software Standby): Initialization is performed by automatic setting of the MCR reset request bit (MCR0) in MCR and the reset state bit (GSR3) in GSR within the HCAN (hardware reset). At the same time, all internal registers are initialized. However mailbox contents are retained. A flowchart of this reset is shown in figure 16-4. Note: * In a reset and in hardware standby mode, the module stop bit is initialized to 1 and the HCAN enters the module stop state. Software Reset (Write to MCR0): In normal operation initialization is performed by setting the MCR reset request bit (MCR0) in MCR (Software reset). With this kind of reset, if the CAN controller is performing a communication operation (transmission or reception), the initialization state is not entered until the message has been completed. During initialization, the reset state bit (GSR3) in GSR is set. In this kind of initialization, the error counters (TEC and REC) are initialized but other registers and RAM (mailboxes) are not. A flowchart of this reset is shown in figure 16-5. Rev. 6.00 Feb 22, 2005 page 641 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Hardware reset MCR0 = 1 (automatic) IRR0 = 1 (automatic)*1 GSR3 = 1 (automatic) Initialization of HCAN module Bit configuration mode Period in which BCR, MBCR, etc., are initialized Clear IRR0 BCR setting MBCR setting Mailbox (RAM) initialization Message transmission method initialization MCR0 = 0 GSR3 = 0? Yes IMR setting (interrupt mask setting) MBIMR setting (interrupt mask setting) MC[x] setting (receive identifier setting) LAFM setting (receive identifier mask setting) No GSR3 = 0 & 11 recessive bits received? Yes CAN bus communication enabled No : Settings by user : Processing by hardware Notes: 1. When IRR0 is set to 1 (automatically) due to a hardware reset*2, a "hardware reset initiated reset processing" interrupt is generated. 2. In a reset and in hardware standby mode, the module stop bit is initialized to 1 and the HCAN enters the module stop state. Figure 16-4 Hardware Reset Flowchart Rev. 6.00 Feb 22, 2005 page 642 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) MCR0 = 1 Bus idle? Yes GSR3 = 1 (automatic) No Initialization of REC and TEC only Correction BCR setting MBCR setting Mailbox (RAM) initialization Message transmission method initialization OK? Yes No GSR3 = 1? Yes MCR0 = 0 No GSR3 = 0? Yes No IMR setting MBIMR setting MC[x] setting LAFM setting OK? Yes Correction No GSR3 = 0 & 11 recessive bits received? Yes CAN bus communication enabled No : Settings by user : Processing by hardware Figure 16-5 Software Reset Flowchart Rev. 6.00 Feb 22, 2005 page 643 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.3.2 Initialization after Hardware Reset After a hardware reset, the following initialization processing should be carried out: * * * * * Clearing of IRR0 bit in interrupt register (IRR) Bit rate setting Mailbox transmit/receive settings Mailbox (RAM) initialization Message transmission method setting These initial settings must be made while the HCAN is in bit configuration mode. Configuration mode is a state in which the reset request bit (MCR0) in the master control register (MCR) is 1 and the reset status bit in the general status register (GSR) is also 1 (GSR3 = 1). Configuration mode is exited by clearing the reset request bit in MCR to 0; when MCR0 is cleared to 0, the HCAN automatically clears the reset state bit (GSR3) in the general status register (GSR). The power-up sequence then begins, and communication with the CAN bus is possible as soon as the sequence ends. The power-up sequence consists of the detection of 11 consecutive recessive bits. IRR0 Clearing: The reset interrupt flag (IRR0) is always set after a reset or recovery from software standby mode. As an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0 should be cleared. Bit Rate and Bit Timing Settings: As bit rate settings, a baud rate setting and bit timing setting must be made each time a CAN node begins communication. The baud rate and bit timing settings are made in the bit configuration register (BCR). a. Note BCR can be written to at all times, but should only be modified in configuration mode. Settings should be made so that all CAN controllers connected to the CAN bus have the same baud rate and bit width. Limits for the settable variables (TSEG1, TSEG2, BRP, sample point, and SJW) are shown in table 16-3. Rev. 6.00 Feb 22, 2005 page 644 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Table 16-3 BCR Register Value Setting Ranges Name Time segment 1 Time segment 2 Baud rate prescaler Sample point Synchronization jump width Abbreviation TSEG1 TSEG2 BRP SAM SJW Bits 4 3 6 1 2 Initial Value 0 0 0 0 0 Min. Value 3 1 0 0 1 Max. Value 15 7 63 1 3 b. Value Setting Ranges * The minimum value of SJW is stipulated in the CAN specifications. 3 SJW 0 * The minimum value of TSEG1 is stipulated in the CAN specifications. TSEG1 > TSEG2 * The minimum value of TSEG2 is stipulated in the CAN specifications. TSEG2 SJW The following formula is used to calculate the baud rate. fCLK Bit rate = 2 x (BRP + 1) x (3 + TSEG1 + TSEG2) [b/s] Note: fCLK = (system clock) The BCR value are used for BRP, TSEG1, and TSEG2. Example: With a 1 Mb/s baud rate and a 20 MHz input clock: 1 Mb/s = 20 MHz 2 x (0 + 1) x (3 + 4 + 3) Rev. 6.00 Feb 22, 2005 page 645 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Item fCLK BRP TSEG1 TSEG2 Set Values 20 MHz 0 (B'000000) 4 (B'0100) 3 (B'011) Actual Values -- System clock x 2 5TQ 4TQ 1-bit time 1-bit time (8 to 25 time quanta) SYNC_SEG PRSEG PHSEG1 PHSEG2 Time segment 2 (TSEG2)* 2 to 8 1 Time segment 1 (TSEG1)* 2 to16 Quantum Legend: SYNC_SEG: Segment for establishing synchronization of nodes on the CAN bus (Normal bit edge transitions occur in this segment). PRSEG: Segment for compensating for physical delay between networks. PHSEG1: Buffer segment for correcting phase drift (positive). (This segment is extended when synchronization (resynchronization) is established). PHSEG2: Buffer segment for correcting phase drift (negative). (This segment is shortened when synchronization (resynchronization) is established). Note: * The time quanta values of TSEG1 and TSEG2 become the value of TSEG + 1. Figure 16-6 Detailed Description of One Bit HCAN bit rate calculation: Bit rate = fCLK 2 x (BRP + 1) x (3 + TSEG1 + TSEG2) fCLK: peripheral clock () Note: The BCR values are used for BRP, TSEG1, and TSEG2. BCR Setting Constraints TSEG1 > TSEG2 SJW (SJW = 0 to 3) These constraints allow the setting range shown in table 16-4 for TSEG1 and TSEG2 in BCR. Rev. 6.00 Feb 22, 2005 page 646 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Table 16-4 Setting Range for TSEG1 and TSEG2 in BCR TSEG2 (BCR [14:12]) 001 TSEG1 (BCR [11:8]) 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 No Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* 010 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 011 No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 100 No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 101 No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 110 No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes 111 No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Note: * Setting is enabled except when BRP [13:8] = B'000000. Mailbox Transmit/Receive Settings: HCAN0, 1 each have 16 mailboxes. Mailbox 0 is receiveonly, while mailboxes 1 to 15 can be set for transmission or reception. Mailboxes that can be set for transmission or reception must be designated either for transmission use or for reception use before communication begins. The Initial status of mailboxes 1 to 15 is for transmission (while mailbox 0 is for reception only). Mailbox transmit/receive settings are not initialized by a software reset. * Setting for transmission Transmit mailbox setting (mailboxes 1 to 15) Clearing a corresponding mailbox in the mailbox configuration register (MBCR) to 0 designates the specified mailbox for transmission use. After a reset, mailboxes are initialized for transmission use, so this setting is not necessary. * Setting for reception Transmit/receive mailbox setting (mailboxes 1 to 15) Setting a bit to 1 in the mailbox configuration register (MBCR) designates the corresponding mailbox for reception use. When setting mailboxes for reception, to improve message transmission efficiency, high-priority messages should be set in low-to-high mailbox order (priority order: mailbox 1 > mailbox 15). Rev. 6.00 Feb 22, 2005 page 647 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) * Receive-only mailbox (mailbox 0) No setting is necessary, as this mailbox is always used for reception. Mailbox (Message Control/Data (MCx[x], MDx[x]) Initial Settings: After power is supplied, all registers and RAM (message control/data, control registers, status registers, etc.) are initialized. Message control/data (MCx[x], MDx[x]) only are in RAM, and so their values are undefined. Initial values must therefore be set in all the mailboxes (by writing 0s or 1s). Setting the Message Transmission Method: Either of the following message transmission methods can be selected with the message transmission method bit (MCR2) in the master control register (MCR): a. Transmission order determined by message identifier priority b. Transmission order determined by mailbox number priority When a is selected, if a number of messages are designated as waiting for transmission (TXPR = 1), the message with the highest priority set in the message identifier (MCx[5] to MCx[8]) is stored in the transmit buffer. CAN bus arbitration is then carried out for the message in the transmit buffer, and message transmission is performed when the transmission right is acquired. When the TXPR bit is set, internal arbitration is performed again, and the highest-priority message is found and stored in the transmit buffer. When b is selected, if a number of messages are designated as waiting for transmission (TXPR = 1), messages are stored in the transmit buffer in low-to-high mailbox order (priority order: mailbox 1 > mailbox 15). CAN bus arbitration is then carried out for the messages in the transmit buffer, and message transmission is performed when the bus is acquired. Rev. 6.00 Feb 22, 2005 page 648 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.3.3 Transmit Mode Message transmission is performed using mailboxes 1 to 15. The transmission procedure is described below, and a transmission flowchart is shown in figure 16-6. Initialization (after hardware reset only) a. b. c. d. e. Clearing of IRR0 bit in interrupt register (IRR) Bit rate settings Mailbox transmit/receive settings Mailbox (RAM) initialization Message transmission method setting Interrupt and transmit data settings a. b. c. d. CPU interrupt source setting Arbitration field setting Control field setting Data field setting Message transmission and interrupts a. b. c. d. Message transmission wait Message transmission completion and interrupt Message transmission cancellation Message retransmission Initialization (After Hardware Reset Only): These settings should be made while the HCAN is in bit configuration mode. * IRR0 clearing The reset interrupt flag (IRR0) is always set after a reset or recovery from software standby mode. As an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0 should be cleared. * Bit rate settings Set values relating to the CAN bus communication speed and resynchronization. Refer to Bit Rate and Bit Timing Settings in 16.3.2, Initialization after Hardware Reset, for details. Rev. 6.00 Feb 22, 2005 page 649 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) * Mailbox transmit/receive settings Mailbox transmit/receive settings should be made in advance. A total of 30 mailbox can be set for transmission or reception (mailboxes 1 to 15 in HCAN0 and HCAN1). To set a mailbox for transmission, clear the corresponding bit to 0 in the mailbox configuration register (MBCR). Refer to Mailbox Transmit/Receive Settings in 16.3.2, Initialization after Hardware Reset, for details. * Mailbox (RAM) initialization As message control/data registers (MCx[x], MDx[x]) are configured in RAM, their initial values after powering on are undefined, and so bit initialization is necessary. Write 0s or 1s to the mailboxes. See Mailbox (Message Control/Data (MCx[x], MDx[x]) Initial Setting in 16.3.2, Initialization after a Hardware Reset, for details. * Message transmission method setting Set the transmission method for mailboxes designated for transmission. The following two transmission methods can be used. Refer to Message Transmission Method Setting in 16.3.2, Initialization after Hardware Reset, for details. a. Transmission order determined by message identifier priority b. Transmission order determined by mailbox number priority Rev. 6.00 Feb 22, 2005 page 650 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Initialization (after hardware reset only) IRR0 clearing BCR setting MBCR setting Mailbox (RAM) initialization Message transmission method setting Interrupt settings Transmit data setting Arbitration field setting Control field setting Data field setting Message transmission wait TXPR setting Bus idle? Yes Message transmission GSR2 = 0 (during transmission only) No Transmission completed? Yes TXACK = 1 IRR8 = 1 No IMR8 = 1? No Interrupt to CPU Yes Clear TXACK Clear IRR8 : Settings by user End of transmission : Processing by hardware Figure 16-7 Transmission Flowchart Rev. 6.00 Feb 22, 2005 page 651 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Interrupt and Transmit Data Settings: When mailbox initialization is finished, CPU interrupt source settings and data settings must be made. Interrupt source settings are made in the mailbox interrupt register (MBIMR) and interrupt mask register (IMR), while transmit data settings are made by writing the necessary data from the arbitration field, control field, and data field, described below, in the corresponding message control (MCx[1] to MCx[8]) and message data (MDx[1] to MDx[8]). * CPU interrupt source setting Transmission acknowledge and transmission abort acknowledge interrupts can be masked for individual mailboxes in the mailbox interrupt mask register (MBIMR). Interrupt register (IRR) interrupts can be masked in the interrupt mask register (IMR). * Arbitration field setting In the arbitration field, the 11-bit identifier (STD_ID0 to STD_ID10) and RTR bit (standard format) or 29-bit identifier (STD_ID0 to STD_ID10, EXT_ID0 to EXT_ID17) and IDE, RTR bit (extended format) are set. The registers to be set are MCx[5] to MCx[8]. * Control field setting In the control field, the byte length of the data to be transmitted is set in DLC0 to DLC3. The register to be set is MCx[1]. * Data field setting In the data field, the data to be transmitted is set in byte units in the range of 0 to 8 bytes. The registers to be set are MDx[1] to MDx[8]. The number of bytes in the data actually transmitted depends on the data length code (DLC) in the control field. If a value exceeding the value set in DLC is set in the data field, only the number of bytes set in DLC will actually be transmitted. Message Transmission and Interrupts: * Message transmission wait If message transmission is to be performed after completion of the message control (MCx[1] to MCx[8]) and message data (MDx[1] to MDx[8]).settings, transmission is started by setting the corresponding mailbox transmit wait bit (TXPR1 to TXPR15) to 1 in the transmit wait register (TXPR). The following two transmission methods can be used: a. Transmission order determined by message identifier priority b. Transmission order determined by mailbox number priority Rev. 6.00 Feb 22, 2005 page 652 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) When a is selected, if a number of messages are designated as waiting for transmission (TXPR = 1), messages are stored in the transmit buffer in low-to-high mailbox order (priority order: mailbox 1 > mailbox 15). CAN bus arbitration is then carried out for the messages in the transmit buffer, and message transmission is performed when the bus is acquired. When b is selected, if a number of messages are designated as waiting for transmission (TXPR = 1), the message with the highest priority set in the message identifier (MCx[5] to MCx[8]) is stored in the transmit buffer. CAN bus arbitration is then carried out for the message in the transmit buffer, and message transmission is performed when the transmission right is acquired. When the TXPR bit is set, internal arbitration is performed again, the highest-priority message is found and stored in the transmit buffer, CAN bus arbitration is carried out in the same way, and message transmission is performed when the transmission right is acquired. * Message transmission completion and interrupt When a message is transmitted error-free using the above procedure, the corresponding acknowledge bit (TXACK1 to TXACK15) in the transmit acknowledge register (TXACK) and transmit wait bit (TXPR1 to TXPR15) in the transmit wait register (TXPR) are automatically initialized. Also, if the corresponding bit (MBIMR1 to MBIMR15) in the mailbox interrupt mask register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask register (IMR) are set to the interrupt enable state at the same time, an interrupt can be sent to the CPU. * Message transmission cancellation Transmission cancellation can be specified for a message stored in a mailbox as a transmit wait message. A transmit wait message is canceled by setting the bit for the corresponding mailbox (TXCR1 to TXCR15) to 1 in the transmit cancel register (TXCR). When cancellation is executed, the transmit wait register (TXPR) is automatically reset, and the corresponding bit is set to 1 in the abort acknowledge register (ABACK). An interrupt can be requested. Also, if the mailbox empty interrupt (IRR8) is enabled for the bits (MBIMR1 to MBIMR15) corresponding to the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR), interrupts may be sent to the CPU. However, a transmit wait message cannot be canceled at the following times: a. During internal arbitration or CAN bus arbitration b. During data frame or remote frame transmission Also, transmission cannot be canceled by clearing the transmit wait register (TXPR). Figure 16-5 shows a flowchart of transmit message cancellation. Rev. 6.00 Feb 22, 2005 page 653 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) * Message retransmission If transmission of a transmit message is aborted in the following cases, the message is retransmitted automatically: a. CAN bus arbitration failure (failure to acquire the bus) b. Error during transmission (bit error, stuff error, CRC error, frame error, ACK error) Message transmit wait TXPR setting Set TXCR bit corresponding to message to be canceled Cancellation possible? Yes Message not sent Clear TXCR, TXPR ABACK = 1 IRR8 = 1 No Completion of message transmission TXACK = 1 Clear TXCR, TXPR IRR8 = 1 IMR8 = 1? No Interrupt to CPU Yes Clear TXACK Clear ABACK Clear IRR8 : Settings by user End of transmission/transmission cancellation : Processing by hardware Figure 16-8 Transmit Message Cancellation Flowchart Rev. 6.00 Feb 22, 2005 page 654 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.3.4 Receive Mode Message reception is performed using mailboxes 0 and 1 to 15. The reception procedure is described below, and a reception flowchart is shown in figure 16-9. Initialization (after hardware reset only) a. b. c. d. Clearing of IRR0 bit in interrupt register (IRR) Bit rate settings Mailbox transmit/receive settings Mailbox (RAM) initialization Interrupt and receive message settings a. CPU interrupt source setting b. Arbitration field setting c. Local acceptance filter mask (LAFM) settings Message reception and interrupts a. b. c. d. Message reception CRC check Data frame reception Remote frame reception Unread message reception Initialization (After Hardware Reset Only): These settings should be made while the HCAN is in bit configuration mode. * IRR0 clearing The reset interrupt flag (IRR0) is always set after a reset or recovery from software standby mode. As an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0 should be cleared. * Bit rate settings Set values relating to the CAN bus communication speed and resynchronization. Refer to Bit Rate and Bit Timing Settings in 16.3.2, Initialization after Hardware Reset, for details. Rev. 6.00 Feb 22, 2005 page 655 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) * Mailbox transmit/receive settings Each channel has one receive-only mailbox (mailbox 0) plus 15 mailboxes that can be set for reception. Thus a total of 32 mailboxes can be used for reception. To set a mailbox for reception, set the corresponding bit to 1 in the mailbox configuration register (MBCR). The initial setting for mailboxes is 0, designating transmission use. Refer to Mailbox Transmit/Receive Settings in 16.3.2, Initialization after Hardware Reset, for details. * Mailbox (RAM) initialization As message control/data registers (MCx[x], MDx[x]) are configured in RAM, their initial values after powering on are undefined, and so bit initialization is necessary. Write 0s or 1s to the mailboxes. See Mailbox (Message Control/Data (MCx[x], MDx[x]) Initial Setting in 16.3.2, Initialization after a Hardware Reset, for details. Rev. 6.00 Feb 22, 2005 page 656 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Initialization IRR0 clearing BCR setting MBCR setting Mailbox (RAM) initialization : Settings by user : Processing by hardware Interrupt settings Receive data setting Arbitration field setting Local acceptance filter settings Message reception (Match of identifier in mailbox?) Yes Same RXPR = 1? No Data frame? Yes RXPR IRR1 = 1 No Yes Unread message No RXPR, RFPR = 1 IRR2 = 1, IRR1 = 1 Yes Yes IMR1 = 1? No Interrupt to CPU IMR2 = 1? No Interrupt to CPU Message control read Message data read Clear all RXPRn bits of mailbox for which receive interrupt requests are enabled by MBIMR IRR1 = 0 Message control read Message data read Clear all RXPRn bits of mailbox for which receive interrupt requests are enabled by MBIMR IRR2 = 0, IRR1 = 0 Transmission of data frame corresponding to remote frame End of reception Figure 16-9 Reception Flowchart Rev. 6.00 Feb 22, 2005 page 657 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Interrupt and Receive Message Settings: When mailbox initialization is finished, CPU interrupt source settings and receive message specifications must be made. Interrupt source settings are made in the mailbox interrupt register (MBIMR) and interrupt mask register (IMR). To receive a message, the identifier must be set in advance in the message control (MCx[1] to MCx[8]) for the receiving mailbox. When a message is received, all the bits in the receive message identifier are compared, and if a 100% match is found, the message is stored in the matching mailbox. Mailbox 0 (MB0) has a local acceptance filter mask (LAFM) that allows Don't care settings to be made. * CPU interrupt source settings When transmitting, transmission acknowledge and transmission abort acknowledge interrupts can be masked for individual mailboxes in the mailbox interrupt mask register (MBIMR). When receiving, data frame and remote frame receive wait interrupts can be masked. Interrupt register (IRR) interrupts can be masked in the interrupt mask register (IMR). * Arbitration field setting In the arbitration field, the identifier (STD_ID0 to STD_ID10, EXT_ID0 to EXT_ID17) of the message to be received is set. If all the bits in the set identifier do not match, the message is not stored in a mailbox. Example: Mailbox 1 010_1010_1010 (standard identifier) Only one kind of message identifier can be received by MB1 Identifier 1: 010_1010_1010 * Local acceptance filter mask (LAFM) setting The local acceptance filter mask is provided for mailbox 0 (MB0) only, enabling a Don't care specification to be made for all bits in the received identifier. This allows various kinds of messages to be received. Example: Mailbox 0 LAFM 010_1010_1010 (standard identifier) 000_0000_0011 (0: Care, 1: Don't care) A total of four kinds of message identifiers can be received by MB0 Identifier 1: 010_1010_1000 Identifier 2: 010_1010_1001 Identifier 3: 010_1010_1010 Identifier 4: 010_1010_1011 Rev. 6.00 Feb 22, 2005 page 658 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Message Reception and Interrupts: * Message reception CRC check When a message is received, a CRC check is performed automatically (by hardware). If the result of the CRC check is normal, ACK is transmitted in the ACK field irrespective of whether or not the message can be received. * Data frame reception If the received message is confirmed to be error-free by the CRC check, etc., the identifier in the mailbox (and also LAFM in the case of mailbox 0 only) and the identifier of the receive message are compared, and if a complete match is found, the message is stored in the mailbox. The message identifier comparison is carried out on each mailbox in turn, starting with mailbox 0 and ending with mailbox 15. If a complete match is found, the comparison ends at that point, the message is stored in the matching mailbox, and the corresponding receive complete bit (RXPR0 to RXPR15) is set in the receive complete register (RXPR). However, when a mailbox 0 LAFM comparison is carried out, even if the identifier matches, the mailbox comparison sequence does not end at that point, but continues with mailbox 1 and then the remaining mailboxes. It is therefore possible for a message matching mailbox 0 to be received by another mailbox (however, the same message cannot be stored in more than one of mailboxes 1 to 15). If the corresponding bit (MBIMR0 to MBIMR15) in the mailbox interrupt mask register (MBIMR) and the receive message interrupt mask (IMR1) in the interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt can be sent to the CPU. * Remote frame reception Two kinds of messages--data frames and remote frames--can be stored in mailboxes. A remote frame differs from a data frame in that the remote reception request bit (RTR) in the message control register (MC[x]5) and the data field are 0 bytes. The data length to be returned in a data frame must be stored in the data length code (DLC) in the control field. When a remote frame (RTR = recessive) is received, the corresponding bit is set in the remote request wait register (RFPR). If the corresponding bit (MBIMR0 to MBIMR15) in the mailbox interrupt mask register (MBIMR) and the remote frame request interrupt mask (IRR2) in the interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt can be sent to the CPU. * Unread message reception When a received message matches the identifier in a mailbox, the message is stored in the mailbox. If a message overwrite occurs before the CPU reads the message, the corresponding bit (UMSR0 to UMSR15) is set in the unread message register (UMSR). In overwriting of an unread message, when a new message is received before the corresponding bit in the receive complete register (RXPR) has been cleared, the unread message register (UMSR) is set. If the Rev. 6.00 Feb 22, 2005 page 659 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) unread interrupt flag (IRR9) in the interrupt mask register (IMR) is set to the interrupt enable value at this time, an interrupt can be sent to the CPU. Figure 16-10 shows a flowchart of unread message overwriting. Unread message overwrite UMSR = 1 IRR9 = 1 IMR9 = 1? No Interrupt to CPU Yes Clear IRR9 Message control/message data read : Settings by user End : Processing by hardware Figure 16-10 Unread Message Overwrite Flowchart Rev. 6.00 Feb 22, 2005 page 660 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.3.5 HCAN Sleep Mode The HCAN is provided with an HCAN sleep mode that places the HCAN module in the sleep state to reduce current dissipation. Figure 16-11 shows a flowchart of the HCAN sleep mode. MCR5 = 1 Bus idle? Yes Initialize TEC and REC No Bus operation? Yes IRR12 = 1 No IMR12 = 1? Yes No MB should not be accessed CPU interrupt Sleep mode clearing method MCR7 = 0? Yes (manual) No (automatic) Clear sleep mode? Yes No GSR3 = 1? Yes No GSR3 = 1? Yes MCR5 = 0 No MCR5 = 0 11 recessive bits? Yes CAN bus communication possible No : Settings by user : Processing by hardware Figure 16-11 HCAN Sleep Mode Flowchart Rev. 6.00 Feb 22, 2005 page 661 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is delayed until the bus becomes idle. Either of the following methods of clearing HCAN sleep mode can be selected by making a setting in the MCR7 bit. 1. Clearing by software 2. Clearing by CAN bus operation Eleven recessive bits must be received after HCAN sleep mode is cleared before CAN bus communication is enabled again. Clearing by software: HCAN sleep mode is cleared by writing a 0 to MCR5 from the CPU. Clearing by CAN bus operation: Clearing by CAN bus operation occurs automatically when the CAN bus performs an operation and this change is detected. In this case, the first message is not received in the mailbox, and normal reception starts from the next message. When a change is detected on the CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is set in the interrupt register (IRR). If the bus interrupt mask (IMR12) in the interrupt mask register (IMR) is set to the interrupt enable value at this time, an interrupt can be sent to the CPU. Rev. 6.00 Feb 22, 2005 page 662 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.3.6 HCAN Halt Mode The HCAN halt mode is provided to enable mailbox settings to be changed without performing an HCAN hardware or software reset. Figure 16-12 shows a flowchart of the HCAN halt mode. MCR1 = 1 Bus idle? Yes MBCR setting No MCR1 = 0 : Settings by user CAN bus communication possible : Processing by hardware Figure 16-12 HCAN Halt Mode Flowchart HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control register (MCR). However, if the CAN bus is operating at the time of a transition, the transition to HCAN ALT mode is delayed until the bus becomes idle. HCAN halt mode is cleared by clearing MCR1 to 0. 16.3.7 Interrupt Interface There are 12 HCAN interrupt sources, to which five independent interrupt vectors are assigned. Table 16-5 lists the HCAN interrupt sources. With the exception of the reset processing vector (IRR0), these sources can be masked. Masking is implemented using the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR). Rev. 6.00 Feb 22, 2005 page 663 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Table 16-5 HCAN Interrupt Sources Channel HCAN0 IPR Bits IPRM (2 to 0) Vector ERS0 Vector Number IRR Bit 108 IRR5 IRR6 OVR0 108 IRR0 IRR2 IRR3 IRR4 IRR7 IRR9 IRR12 RM0 RM1 SLE0 HCAN1 IPRM (6 to 4) ERS0 109 108 108 106 IRR1 IRR1 IRR8 IRR5 IRR6 OVR0 106 IRR0 IRR2 IRR3 IRR4 IRR7 IRR9 IRR12 RM0 RM1 SLE0 107 106 106 IRR1 IRR1 IRR8 Description Error passive interrupt (TEC 128 or REC 128) Bus off interrupt (TEC 256) Hardware reset processing interrupt Remote frame reception interrupt Error warning interrupt (TEC 96) Error warning interrupt (REC 96) Overload frame transmission interrupt Unread message overwrite interrupt HCAN sleep mode CAN bus operation interrupt Mailbox 0 message reception interrupt Mailbox 1 to 15 message reception interrupt Message transmission/cancellation interrupt Error passive interrupt (TEC 128 or REC 128) Bus off interrupt (TEC 256) Hardware reset processing interrupt Remote frame reception interrupt Error warning interrupt (TEC 96) Error warning interrupt (REC 96) Overload frame transmission interrupt Unread message overwrite interrupt HCAN sleep mode CAN bus operation interrupt Mailbox 0 message reception interrupt Mailbox 1 to 15 message reception interrupt Message transmission/cancellation interrupt Rev. 6.00 Feb 22, 2005 page 664 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.3.8 DTC Interface* Note: * The DTC is not implemented in the H8S/2635 and H8S/2634. The DTC can be activated by reception of a message in the HCAN's mailbox 0. When DTC transfer ends after DTC activation has been set, the RXPR0 and RFPR0 flags are acknowledge signal automatically. An interrupt request due to a receive interrupt from the HCAN cannot be sent to the CPU in this case. Figure 16-13 shows a DTC transfer flowchart. DTC initialization DTC enable register setting DTC register information setting Message reception in HCAN's mailbox 0 DTC activation End of DTC transfer? Yes RXPR and RFPR clearing No Transfer counter = 0 or DISEL = 1? Yes Interrupt to CPU No : Settings by user End : Processing by hardware Figure 16-13 DTC Transfer Flowchart Rev. 6.00 Feb 22, 2005 page 665 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.4 CAN Bus Interface A bus transceiver IC is necessary to connect the chip to a CAN bus. A HA13721 transceiver IC, or compatible device, is recommended. Figure 16-14 shows a sample connection diagram. 120 Vcc HA13721 Port HRxD HTxD NC MODE Vcc RxD CANH TxD CANL NC GND CAN bus Chip 120 Note: NC: No Connection Figure 16-14 High-Speed Interface Using HA13721 Rev. 6.00 Feb 22, 2005 page 666 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) 16.5 Usage Notes (1) Reset The HCAN is reset by a reset, and in hardware standby mode and software standby mode. All the registers are initialized in a reset, but mailboxes (message control (MCx[x])/message data (MDx[x]) are not. However, after powering on, mailboxes (message control (MCx[x])/message data (MDx[x]) are initialized, and their values are undefined. Therefore, mailbox initialization must always be carried out after a reset or a transition to hardware standby mode or software standby mode. Also, the reset interrupt flag (IRR0) is always set after reset input or recovery from software standby mode. As this bit cannot be masked in the interrupt mask register (IMR), if HCAN interrupts are set as enabled by the interrupt controller without this flag having been cleared, an HCAN interrupt will be initiated immediately. IRR0 must therefore be cleared during initialization. (2) HCAN sleep mode The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by bus operation in HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate sleep mode release. Also note that the reset status bit (GSR3) in the general status register (GSR) is set in sleep mode. (3) Interrupts When the mailbox interrupt mask register (MBIMR) is set, the interrupt register (IRR8,2,1) is not set by reception completion, transmission completion, or transmission cancellation for the set mailboxes. (4) Error counters In the case of error active and error passive, REC and TEC normally count up and down. In the bus off state, 11-bit recessive sequences are counted (REC + 1) using REC. If REC reaches 96 during the count, IRR4 and GSR1 are set. (5) Register access Byte or word access can be used on all HCAN registers. Longword access cannot be used. (6) HCAN medium-speed mode HCAN registers cannot be read or written to in medium-speed mode. Rev. 6.00 Feb 22, 2005 page 667 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) (7) Register retention during standby All HCAN registers are initialized in hardware standby mode and software standby mode. (8) Usage of bit manipulation instructions The HCAN status flags are cleared by writing 1, so do not use a bit manipulation instruction to clear a flag. When clearing a flag, use the MOV instruction to write 1 to only the bit that is to be cleared. (9) Operation of TXCR in HCAN 1. When the transmit wait cancel register (TXCR) is used to cancel messages awaiting transmission from a mailbox waiting to transmit, the bits corresponding to TXCR and the transmit wait register (TXPR) are sometimes not cleared in spite of the fact that transmission was cancelled. This situation can arise when all of the following conditions are met. * The HRxD pin is stuck at 1 because of a CAN bus error, etc. * One or more mailboxes are waiting to transmit (or transmitting). * Transmission of a message in a mailbox that is transmitting is cancelled using TXCR. When this situation occurs the message is not cancelled. However, since TXPR and TXCR continue to incorrectly display the status of the message as in the process of being cancelled, it is not possible to restart transmission even when the HRxD pin is no longer stuck at 1 and the CAN bus is restored to normal status. If there are two or more messages to be transmitted, those messages that are not in the process of being sent are cancelled and the messages in the process of being sent remain in that status. To avoid the situation described above, either of the following two countermeasures should be implemented. * Do not use TXCR to cancel transmission of messages. This will ensure that TXPR is cleared and HCAN operates normally after transmission completes normally following recovery by the CAN bus. * If it is necessary to cancel transmission of a message, write continuously to bit 1 corresponding to TXCR until the bits corresponding to TXCR become 0. This will ensure that TXPR and TXCR are cleared and that HCAN is restored to normal operation. 2. If TXPR is set, resulting in transmission wait status, when a transition to bus off status takes place, cancellation cannot be performed even if TXCR is set during bus off status because the internal state machine does not operate. After recovery from bus off status, the message is cancelled after one message is either sent or generates a transmission error. The following countermeasure should be taken with regard to clearing messages following recovery from bus off status. Rev. 6.00 Feb 22, 2005 page 668 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) * Clear the messages awaiting transmission by resetting the HCAN module during bus off status. To reset the HCAN module, set and then clear the module stop bits (MSTPC3 and MSTPC2 in MSTPCRC). Note that this will reset all internal values in the HCAN module, so it will be necessary to perform the initial settings once again. (10) HCAN Transmit Procedure When transmission is set while the bus is in the idle state, if the next transmission is set or the set transmission is canceled under the following conditions within 50 s, the transmit message ID of being set may be damaged. * When the second transmission has the message whose priority is higher than the first one. * When the message of the highest priority is canceled in the first transmission. Make whichever setting shown below to avoid the message IDs from being damaged. * Set transmission in one TXPR. After transmission of all transmit messages is completed, set transmission again (mass transmission setting). The interval between transmission settings should be 50 s or longer. * Make the transmission setting according to the priority of transmit messages. * Set the interval to be 50 s or longer between TXPR and another TXPR or between TXPR and TXCR. Table 16-6 Interval Limitation between TXPR and TXPR or between TXPR and TXCR Baud Rate (bps) 1M 500 k 250 k Set Interval (s) 50 50 50 (11) Canceling HCAN Reset and HCAN Sleep Before canceling the software reset or sleep mode for HCAN (MCR0 = 0 or MCR5 = 0), confirm that the reset status bit (GSR3) is set to 1. (12) Accessing Mailbox in HCAN Sleep Mode The mailboxes should not be accessed in HCAN sleep mode. If mailboxes are accessed in HCAN sleep mode, the CPU may stop. When registers are accessed in HCAN sleep mode, the CPU does not stop. When mailboxes are accessed in modes other than sleep mode, the CPU does not stop. Rev. 6.00 Feb 22, 2005 page 669 of 1484 REJ09B0103-0600 Section 16 Controller Area Network (HCAN) Rev. 6.00 Feb 22, 2005 page 670 of 1484 REJ09B0103-0600 Section 17 A/D Converter Section 17 A/D Converter Note: The H8S/2635 Group is not equipped with a DTC. 17.1 Overview The chip incorporates a successive approximation type 10-bit A/D converter that allows up to twelve analog input channels to be selected. 17.1.1 Features A/D converter features are listed below. * 10-bit resolution * Twelve input channels * Settable analog conversion voltage range Conversion of analog voltages with the reference voltage pin (Vref) as the analog reference voltage * High-speed conversion Minimum conversion time: 13.3 s per channel (at 20 MHz operation) * Choice of single mode or scan mode Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels * Four data registers Conversion results are held in a 16-bit data register for each channel * Sample and hold function * Three kinds of conversion start Choice of software or timer conversion start trigger (TPU), or pin * A/D conversion end interrupt generation A/D conversion end interrupt (ADI) request can be generated at the end of A/D conversion * Module stop mode can be set As the initial setting, A/D converter operation is halted. Register access is enabled by exiting module stop mode. Rev. 6.00 Feb 22, 2005 page 671 of 1484 REJ09B0103-0600 GRTDA Section 17 A/D Converter 17.1.2 Block Diagram Figure 17-1 shows a block diagram of the A/D converter. Module data bus Bus interface ADDRC ADDRD ADDRA ADDRB ADCSR ADCR Internal data bus AVCC Vref AVSS 10-bit D/A AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 Successive approximations register + Multiplexer /2 /4 Control circuit /8 /16 - Comparator Sample-andhold circuit ADI interrupt ADTRG Legend: ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: Conversion start trigger from TPU A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D Figure 17-1 Block Diagram of A/D Converter Rev. 6.00 Feb 22, 2005 page 672 of 1484 REJ09B0103-0600 Section 17 A/D Converter 17.1.3 Pin Configuration Table 17-1 summarizes the input pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin. The 12 analog input pins are divided into two channel sets and two groups, with analog input pins 0 to 7 (AN0 to AN7) comprising channel set 0, analog input pins 8 to 11 (AN8 to AN11) comprising channel set 1, analog input pins 0 to 3 and 8 to 11 (AN0 to AN3, AN8 to AN11) comprising group 0, and analog input pins 4 to 7 (AN4 to AN7) comprising group 1. Table 17-1 A/D Converter Pins Pin Name Analog power supply pin Analog ground pin Reference voltage pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 Analog input pin 8 Analog input pin 9 Analog input pin 10 Analog input pin 11 A/D external trigger input pin Symbol AVCC AVSS Vref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input External trigger input for starting A/D conversion Channel set 1 (CH3 = 1) group 0 analog inputs Channel set 0 (CH3 = 0) group 1 analog inputs Function Analog block power supply Analog block ground and reference voltage A/D conversion reference voltage Channel set 0 (CH3 = 0) group 0 analog inputs GRTDA Rev. 6.00 Feb 22, 2005 page 673 of 1484 REJ09B0103-0600 Section 17 A/D Converter 17.1.4 Register Configuration Table 17-2 summarizes the registers of the A/D converter. Table 17-2 A/D Converter Registers Name A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Module stop control register A Abbreviation ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR MSTPCRA R/W R R R R R R R R R/(W) R/W R/W *2 Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'33 H'3F Address*1 H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FDE8 Notes: 1. Lower 16 bits of the address. 2. Bit 7 can only be written with 0 for flag clearing. Rev. 6.00 Feb 22, 2005 page 674 of 1484 REJ09B0103-0600 Section 17 A/D Converter 17.2 17.2.1 Bit Register Descriptions A/D Data Registers A to D (ADDRA to ADDRD) : 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Initial value : R/W : 3/43/43/43/43/43/4 0 R 0 R 0 R 0 R 0 R 0 R 5 4 3 2 1 0 There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and stored. Bits 5 to 0 are always read as 0. The correspondence between the analog input channels and ADDR registers is shown in table 17-3. ADDR can always be read by the CPU. The upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section 17.3, Interface to Bus Master. The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop mode. Table 17-3 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel Channel Set 0 (CH3 = 0) Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 Channel Set 1 (CH3 = 1) Group 0 AN8 AN9 AN10 AN11 Group 1 Setting prohibited Setting prohibited Setting prohibited Setting prohibited A/D Data Register ADDRA ADDRB ADDRC ADDRD Rev. 6.00 Feb 22, 2005 page 675 of 1484 REJ09B0103-0600 Section 17 A/D Converter 17.2.2 Bit A/D Control/Status Register (ADCSR) : 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CH3 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Initial value : R/W : Note: * Only 0 can be written to bit 7, to clear this flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations. ADCSR is initialized to H'00 by a reset, and in hardware standby mode or module stop mode. Bit 7--A/D End Flag (ADF): Status flag that indicates the end of A/D conversion. Bit 7 ADF 0 Description [Clearing conditions] * * 1 * * When 0 is written to the ADF flag after reading ADF = 1 When the DTC is activated by an ADI interrupt and ADDR is read Single mode: When A/D conversion ends Scan mode: When A/D conversion ends on all specified channels (Initial value) [Setting conditions] Bit 6--A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests at the end of A/D conversion. Bit 6 ADIE 0 1 Description A/D conversion end interrupt (ADI) request disabled A/D conversion end interrupt (ADI) request enabled (Initial value) Rev. 6.00 Feb 22, 2005 page 676 of 1484 REJ09B0103-0600 Section 17 A/D Converter Bit 5--A/D Start (ADST): Selects starting or stopping on A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG). Bit 5 ADST 0 1 Description A/D conversion stopped (Initial value) Single mode: A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode. Bit 4--Scan Mode (SCAN): Selects single mode or scan mode as the A/D conversion operating mode. See section 17.4, Operation, for single mode and scan mode operation. Only set the SCAN bit while conversion is stopped (ADST = 0). Bit 4 SCAN 0 1 Description Single mode Scan mode (Initial value) Bit 3--Channel Select 3 (CH3): Switches the analog input pins assigned to group 0 or group 1. Setting CH3 to 1 enables AN8 to AN11 to be used instead of AN0 to AN7. Bit 3 CH3 1 0 Description AN8 to AN11 are group 0 analog input pins AN0 to AN3 are group 0 analog input pins, AN4 to AN7 are group 1 analog input pins (Initial value) Rev. 6.00 Feb 22, 2005 page 677 of 1484 REJ09B0103-0600 Section 17 A/D Converter Bits 2 to 0--Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select the analog input channels. Only set the input channel while conversion is stopped (ADST = 0). Channel Selection CH3 0 CH2 0 CH1 0 1 1 0 1 1 0 0 1 1 0 1 CH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Single Mode (SCAN = 0) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 Setting prohibited Setting prohibited Setting prohibited Setting prohibited (Initial value) Description Scan Mode (SCAN = 1) AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 AN8 AN8, AN9 AN8 to AN10 AN8 to AN11 Setting prohibited Setting prohibited Setting prohibited Setting prohibited Rev. 6.00 Feb 22, 2005 page 678 of 1484 REJ09B0103-0600 Section 17 A/D Converter 17.2.3 Bit A/D Control Register (ADCR) : 7 TRGS1 0 R/W 6 TRGS0 0 R/W 3/4 3/4 1 5 3/4 3/4 1 4 3 CKS1 0 R/W 2 CKS0 0 R/W 3/4 3/4 1 1 3/4 3/4 1 0 Initial value : R/W : ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion operations and sets the A/D conversion time. ADCR is initialized to H'33 by a reset, and in standby mode or module stop mode. Bits 7 and 6--Timer Trigger Select 1 and 0 (TRGS1, TRGS0): Select enabling or disabling of the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion is stopped (ADST = 0). Bit 7 TRGS1 0 1 Bit 6 TRGS0 0 1 0 1 Description A/D conversion start by software is enabled Setting prohibited A/D conversion start by external trigger pin (ADTRG) is enabled (Initial value) A/D conversion start by TPU conversion start trigger is enabled Bits 5, 4, 1, and 0--Reserved: These bits are reserved; they are always read as 1 and cannot be modified. Bits 3 and 2--Clock Select 1 and 0 (CKS1, CKS0): These bits select the A/D conversion time. The conversion time should be changed only when ADST = 0. Set bits CKS1 and CKS0 to give a conversion time of at least 10 s. Bit 3 CKS1 0 1 Bit 2 CKS0 0 1 0 1 Description Conversion time = 530 states (max.) Conversion time = 266 states (max.) Conversion time = 134 states (max.) Conversion time = 68 states (max.) (Initial value) Rev. 6.00 Feb 22, 2005 page 679 of 1484 REJ09B0103-0600 Section 17 A/D Converter 17.2.4 Bit Module Stop Control Register A (MSTPCRA) : 7 0 R/W 6 0 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W : MSTPCR is an 8-bit readable/writable register that performs module stop mode control. When the MSTPA1 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 23A.5, 23B.5, Module Stop Mode. MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized by a reset and in software standby mode. Bit 1--Module Stop (MSTPA1): Specifies the A/D converter module stop mode. Bit 1 MSTPA1 0 1 Description A/D converter module stop mode cleared A/D converter module stop mode set (Initial value) Rev. 6.00 Feb 22, 2005 page 680 of 1484 REJ09B0103-0600 Section 17 A/D Converter 17.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading ADDR, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 17-2 shows the data flow for ADDR access. Upper byte read Bus master (H'AA) Bus interface Module data bus TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Lower byte read Bus master (H'40) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Figure 17-2 ADDR Access Operation (Reading H'AA40) Rev. 6.00 Feb 22, 2005 page 681 of 1484 REJ09B0103-0600 Section 17 A/D Converter 17.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. 17.4.1 Single Mode (SCAN = 0) Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1, according to the software or external trigger input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADF flag is cleared by writing 0 after reading ADCSR. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 17-3 shows a timing diagram for this example. [1] Single mode is selected (SCAN = 0), input channel AN1 is selected (CH3 = 0, CH2 = 0, CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). [2] When A/D conversion is completed, the result is transferred to ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. [3] Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. [4] The A/D interrupt handling routine starts. [5] The routine reads ADCSR, then writes 0 to the ADF flag. [6] The routine reads and processes the connection result (ADDRB). [7] Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1, A/D conversion starts again and steps [2] to [7] are repeated. Rev. 6.00 Feb 22, 2005 page 682 of 1484 REJ09B0103-0600 Section 17 A/D Converter Set* ADIE ADST ADF State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) ADDRA ADDRB ADDRC ADDRD Read conversion result A/D conversion result 1 Read conversion result A/D conversion result 2 Idle Idle Idle Idle A/D conversion 1 A/D conversion starts Set* Clear* Set* Clear* Idle A/D conversion 2 Idle Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 17-3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) Rev. 6.00 Feb 22, 2005 page 683 of 1484 REJ09B0103-0600 Section 17 A/D Converter 17.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by a software, timer or external trigger input, A/D conversion starts on the first channel in the group (AN0). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the ADDR registers corresponding to the channels. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again from the first channel (AN0). The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described next. Figure 17-4 shows a timing diagram for this example. [1] Scan mode is selected (SCAN = 1), channel set 0 is selected (CH3 = 0), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1) [2] When A/D conversion of the first channel (AN0) is completed, the result is transferred to ADDRA. Next, conversion of the second channel (AN1) starts automatically. [3] Conversion proceeds in the same way through the third channel (AN2). [4] When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. [5] Steps [2] to [4] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). Rev. 6.00 Feb 22, 2005 page 684 of 1484 REJ09B0103-0600 Section 17 A/D Converter Continuous A/D conversion execution Set*1 ADST ADF State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Transfer ADDRA ADDRB ADDRC ADDRD Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored. A/D conversion result 1 A/D conversion result 4 A/D conversion result 2 A/D conversion result 3 Idle Idle Idle A/D conversion 1 Clear*1 Clear*1 A/D conversion time Idle A/D conversion 2 A/D conversion 4 Idle A/D conversion 5 *2 Idle A/D conversion 3 Idle Idle Idle Figure 17-4 Example of A/D Converter Operation (Scan Mode, 3 Channels AN0 to AN2 Selected) Rev. 6.00 Feb 22, 2005 page 685 of 1484 REJ09B0103-0600 Section 17 A/D Converter 17.4.3 Input Sampling and A/D Conversion Time The A/D converter has an on-chip sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 17-5 shows the A/D conversion timing. Table 17-4 indicates the A/D conversion time. As indicated in figure 17-5, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 17-4. In scan mode, the values given in table 17-4 apply to the first conversion time. The values given in table 17-5 apply to the second and subsequent conversions. In both cases, set bits CKS1 and CKS0 in ADCR to give a conversion time of at least 10 s. (1) Address (2) Write signal Input sampling timing ADF tD t SPL t CONV Legend: (1): ADCSR write cycle (2): ADCSR address tD: A/D conversion start delay tSPL: Input sampling time tCONV: A/D conversion time Figure 17-5 A/D Conversion Timing Rev. 6.00 Feb 22, 2005 page 686 of 1484 REJ09B0103-0600 Section 17 A/D Converter Table 17-4 A/D Conversion Time (Single Mode) CKS1 = 0 CKS0 = 0 Item CKS0 = 1 CKS1 = 0 CKS0 = 0 CKS0 = 1 Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max 18 -- -- 33 10 -- -- 63 17 -- 6 -- -- 31 9 -- 4 -- -- 15 -- 5 -- 68 A/D conversion start delay tD Input sampling time A/D conversion time tSPL tCONV 127 -- 515 -- 530 259 -- 266 131 -- 134 67 Note: Values in the table are the number of states. Table 17-5 A/D Conversion Time (Scan Mode) CKS1 0 1 CKS0 0 1 0 1 Conversion Time (State) 512 (Fixed) 256 (Fixed) 128 (Fixed) 64 (Fixed) 17.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in ADCR, external trigger input is enabled at the pin. A falling edge at the pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as if the ADST bit has been set to 1 by software. Figure 17-6 shows the timing. Rev. 6.00 Feb 22, 2005 page 687 of 1484 REJ09B0103-0600 GRTDA GRTDA Section 17 A/D Converter ADTRG Internal trigger signal ADST A/D conversion Figure 17-6 External Trigger Input Timing 17.5 Interrupts The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR. The DTC can be activated by an ADI interrupt. Having the converted data read by the DTC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. The A/D converter interrupt source is shown in table 17-6. Table 17-6 A/D Converter Interrupt Source Interrupt Source ADI Description Interrupt due to end of conversion DTC Activation Possible Rev. 6.00 Feb 22, 2005 page 688 of 1484 REJ09B0103-0600 Section 17 A/D Converter 17.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins: (1) Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVSS ANn Vref. (2) Relation between AVCC, AVSS and VCC, VSS As the relationship between AVSS and VSS, set AVSS = VSS. If the A/D converter is not used, set AVCC = VCC, and do not leave the AVCC and AVSS pins open or no account. (3) Vref input range The analog reference voltage input at the Vref pin set in the range Vref AVCC. If conditions (1), (2), and (3) above are not met, the reliability of the device may be adversely affected. Notes on Board Design: In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN11), analog reference power supply (Vref), and analog power supply (AVCC) by the analog ground (AVSS). Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS) on the board. Notes on Noise Countermeasures: A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN11) and analog reference power supply (Vref) should be connected between AVCC and AVSS as shown in figure 17-7. Also, the bypass capacitors connected to AVCC and Vref and the filter capacitor connected to AN0 to AN11 must be connected to AVSS. If a filter capacitor is connected as shown in figure 17-7, the input currents at the analog input pins (AN0 to AN11) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the Rev. 6.00 Feb 22, 2005 page 689 of 1484 REJ09B0103-0600 Section 17 A/D Converter sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC Vref Rin* 2 *1 *1 0.1 mF 100 AN0 to AN11 AVSS Notes: Values are reference values. 1. 10 mF 0.01 mF 2. Rin: Input impedance Figure 17-7 Example of Analog Input Protection Circuit Table 17-7 Analog Pin Specifications Item Analog input capacitance Permissible signal source impedance Min -- -- Max 20 5 Unit pF k Rev. 6.00 Feb 22, 2005 page 690 of 1484 REJ09B0103-0600 Section 17 A/D Converter 10 k9 AN0 to AN11 To A/D converter 20 pF Note: Values are reference values. Figure 17-8 Analog Input Pin Equivalent Circuit A/D Conversion Precision Definitions: The chip's A/D conversion precision definitions are given below. * Resolution The number of A/D converter digital output codes * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'00) to B'0000000001 (H'01) (see figure 17-10). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3E) to B'1111111111 (H'3F) (see figure 17-10). * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 17-9). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error. * Absolute precision The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. Rev. 6.00 Feb 22, 2005 page 691 of 1484 REJ09B0103-0600 Section 17 A/D Converter Digital output 111 110 101 100 011 010 001 000 Ideal A/D conversion characteristic Quantization error 1 2 1024 1024 1022 1023 1024 1024 FS Analog input voltage Figure 17-9 A/D Conversion Precision Definitions (1) Rev. 6.00 Feb 22, 2005 page 692 of 1484 REJ09B0103-0600 Section 17 A/D Converter Digital output Full-scale error Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 17-10 A/D Conversion Precision Definitions (2) Permissible Signal Source Impedance: The chip's analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k, charging may be insufficient and it may not be possible to guarantee the A/D conversion precision. However, if a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater). When converting a high-speed analog signal, a low-impedance buffer should be inserted. Rev. 6.00 Feb 22, 2005 page 693 of 1484 REJ09B0103-0600 Section 17 A/D Converter Influences on Absolute Precision: Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVSS. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. Figure 17-11 shows an example of analog input circuit. Chip Sensor output impedance to 5 kW Sensor input Low-pass filter C to 0.1 mF Cin = 15 pF A/D converter equivalent circuit 10 kW 20 pF Figure 17-11 Example of Analog Input Circuit Rev. 6.00 Feb 22, 2005 page 694 of 1484 REJ09B0103-0600 Section 18 D/A Converter Section 18 D/A Converter Note: The H8S/2635 Group is not equipped with a D/A converter. 18.1 Overview The chip has an on-chip D/A converter module with two channels. 18.1.1 Features Features of the D/A converter module are listed below. * * * * * * Eight-bit resolution Two-channel output Maximum conversion time: 10 s (with 20-pF load capacitance) Output voltage: 0 V to Vref D/A output retention in software standby mode Possible to set module stop mode Operation of D/A converter is disenabled by initial values. It is possible to access the register by canceling module stop mode. Rev. 6.00 Feb 22, 2005 page 695 of 1484 REJ09B0103-0600 Section 18 D/A Converter 18.1.2 Block Diagram Figure 18-1 shows a block diagram of the D/A converter. Module data bus Bus interface Internal data bus Vref AVCC DADR0 DADR1 DA1 DA0 AVSS 8-bit D/A Control circuit Legend: DADR: DADR0, DADR1: D/A control register D/A data register 0, 1 Figure 18-1 Block Diagram of D/A Converter Rev. 6.00 Feb 22, 2005 page 696 of 1484 REJ09B0103-0600 DACR Section 18 D/A Converter 18.1.3 Input and Output Pins Table 18-1 lists the input and output pins used by the D/A converter module. Table 18-1 Input and Output Pins of D/A Converter Module Name Analog supply voltage Analog ground Analog output 0 Analog output 1 Reference voltage Abbreviation AVCC AVSS DA0 DA1 Vref I/O Input Input Output Output Input Function Power supply for analog circuits Ground and reference voltage for analog circuits Analog output channel 0 Analog output channel 1 Reference voltage of analog section 18.1.4 Register Configuration Table 18-2 lists the registers of the D/A converter module. Table 18-2 D/A Converter Registers Channel 0, 1 Name D/A data register 0 D/A data register 1 D/A control register 01 All Module stop control register A Note: * Lower 16 bits of the address. Abbreviation DADR0 DADR1 DACR01 MSTPCRA R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'1F H'3F Address* H'FFA4 H'FFA5 H'FFA6 H'FDF8 Rev. 6.00 Feb 22, 2005 page 697 of 1484 REJ09B0103-0600 Section 18 D/A Converter 18.2 18.2.1 Bit Register Descriptions D/A Data Registers 0, 1 (DADR0, DADR1) 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Initial value Read/Write D/A data registers 0, 1 (DADR0, DADR1) are 8-bit readable/writable registers that store data to be converted. When analog output is enabled, the value in the D/A data register is converted and output continuously at the analog output pin. The D/A data registers are initialized to H'00 by a reset and in hardware standby mode. 18.2.2 Bit Initial value Read/Write D/A Control Register 01 (DACR01) 7 DAOE1 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- DACR01 is an 8-bit readable/writable register that controls the operation of the D/A converter module. DACR01 is initialized to H'1F by a reset and in hardware standby mode. Bit 7--D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output. Bit 7 DAOE1 0 1 Description Analog output DA1 is disabled D/A conversion is enabled on channel 1. Analog output DA1 is enabled (Initial value) Rev. 6.00 Feb 22, 2005 page 698 of 1484 REJ09B0103-0600 Section 18 D/A Converter Bit 6--D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6 DAOE0 0 1 Description Analog output DA0 is disabled D/A conversion is enabled on channel 0. Analog output DA0 is enabled (Initial value) Bit 5--D/A Enable (DAE): Controls D/A conversion, in combination with bits DAOE0 and DAOE1. D/A conversion is controlled independently on channels 0 and 1 when DAE = 0. Channels 0 and 1 are controlled together when DAE = 1. Output of the converted results is always controlled independently by DAOE0 and DAOE1. Bit 7 DAOE1 0 Bit 6 DAOE0 0 1 Bit 5 DAE * 0 1 1 0 0 1 1 * D/A conversion Disabled on channels 0 and 1 Enabled on channel 0 Disabled on channel 1 Enabled on channels 0 and 1 Disabled on channel 0 Enabled on channel 1 Enabled on channels 0 and 1 Enabled on channels 0 and 1 *: Don't care If the chip enters software standby mode while D/A conversion is enabled, the D/A output is retained and the analog power supply current is the same as during D/A conversion. If it is necessary to reduce the analog power supply current in software standby mode, disable D/A output by clearing both the DAOE0 and DAOE1 bits to 0. Bits 4 to 0--Reserved: These bits cannot be modified and are always read as 1. Rev. 6.00 Feb 22, 2005 page 699 of 1484 REJ09B0103-0600 Section 18 D/A Converter 18.2.3 Module Stop Control Register A (MSTPCRA) MSTPCRA Bit : 7 0 R/W 6 0 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W : MSTPCRA is an 8-bit readable/writable registers that performs module stop mode control. When the MSTPA2 is set to 1, the D/A converter halts and enters module stop mode at the end of the bus cycle. Register read/write is disenabled in module stop mode. See section 23A.5, 23B.5, Module Stop Mode, for details. MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 2--Module Stop (MSTPA2): Specifies D/A converter (channels 0 and 1) module stop mode. Bit 2 MSTPA2 0 1 Description D/A converter (channels 0 and 1) module stop mode is cleared D/A converter (channels 0 and 1) module stop mode is set (Initial value) Rev. 6.00 Feb 22, 2005 page 700 of 1484 REJ09B0103-0600 Section 18 D/A Converter 18.3 Operation The D/A converter module has one on-chip D/A converter circuits that can operate independently. D/A conversion is performed continuously whenever enabled by the D/A control register (DACR). When a new value is written in DADR0 or DADR1, conversion of the new value begins immediately. The converted result is output by setting the DAOE0 or DAOE1 bit to 1. An example of conversion on channel 0 is given next. Figure 18-2 shows the timing. * Software writes the data to be converted in DADR0. * D/A conversion begins when the DAOE0 bit in DACR is set to 1. After the elapse of the conversion time, analog output appears at the DA0 pin. Contents of DADR / 256 x Vref This output continues until a new value is written in DADR0 or the DAOE0 bit is cleared to 0. * If a new value is written in DADR0, conversion begins immediately. Output of the converted result begins after the conversion time. * When the DAOE0 bit is cleared to 0, DA0 becomes an input pin. DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle Address DADR0 Conversion data (1) Conversion data (2) DAOE0 DA0 High-impedance state t DCONV Conversion result (1) Conversion result (2) t DCONV Legend: tDCONV: D/A conversion time Figure 18-2 D/A Conversion (Example) Rev. 6.00 Feb 22, 2005 page 701 of 1484 REJ09B0103-0600 Section 18 D/A Converter Rev. 6.00 Feb 22, 2005 page 702 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer Section 19 Motor Control PWM Timer Note: The H8S/2635 Group is not equipped with a DTC. 19.1 Overview The chip has an on-chip motor control PWM (pulse width modulator) with a maximum capability of 16 pulse outputs. 19.1.1 Features Features of the motor control PWM are given below. * Maximum of 16 pulse outputs Two 10-bit PWM channels, each with eight outputs. Each channel is provided with a 10-bit counter (PWCNT) and cycle register (PWCYR). Duty and output polarity can be set for each output. * Buffered duty registers Duty registers (PWDTR) are provided with buffer registers (PWBFR), with data transferred automatically every cycle. Channel 1 has four duty registers and four buffer registers. Channel 2 has eight duty registers and four buffer registers. * 0% to 100% duty A duty cycle of 0% to 100% can be set by means of a duty register setting. * Five operating clocks There is a choice of five operating clocks (, /2, /4, /8, /16). * High-speed access via internal 16-bit-bus High-speed access is possible via a 16-bit bus interface. * Two interrupt sources An interrupt can be requested independently for each channel by a cycle register compare match. * Automatic transfer of register data Block transfer and one-word data transfer are possible by activating the data transfer controller (DTC). * Module stop mode As the initial setting, PWM operation is halted. Register access is enabled by clearing module stop mode. Rev. 6.00 Feb 22, 2005 page 703 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer 19.1.2 Block Diagram Figure 19-1 shows a block diagram of PWM channel 1. , /2, /4, /8, /16 Interrupt request PWCR1 Compare match PWCNT1 PWOCR1 Port control PWCYR1 12 9 0 PWPR1 Bus interface 12 9 0 Internal data bus PWBFR1A PWDTR1A P/N P/N P/N P/N P/N P/N P/N P/N PWM1A PWM1B PWM1C PWM1D PWM1E PWM1F PWM1G PWM1H PWBFR1C PWDTR1C PWBFR1E PWDTR1E PWBFR1G PWDTR1G Legend: PWCR1: PWOCR1: PWPR1: PWCNT1: PWCYR1: PWDTR1A, 1C, 1E, 1G: PWBFR1A, 1C, 1E, 1G: PWM control register 1 PWM output control register 1 PWM polarity register 1 PWM counter 1 PWM cycle register 1 PWM duty registers 1A, 1C, 1E, 1G PWM buffer registers 1A, 1C, 1E, 1G Figure 19-1 Block Diagram of PWM Channel 1 Rev. 6.00 Feb 22, 2005 page 704 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer Figure 19-2 shows a block diagram of PWM channel 2. , /2, /4, /8, /16 Interrupt request PWCR2 PWCNT2 PWOCR2 Port control Compare match PWCYR2 9 0 PWPR2 12 9 0 PWBFR2A PWDTR2A P/N PWM2A Internal data bus Bus interface PWBFR2B PWDTR2B P/N PWM2B PWBFR2C PWDTR2C P/N PWM2C PWBFR2D PWDTR2D PWDTR2E PWDTR2F PWDTR2G PWDTR2H P/N P/N P/N P/N P/N PWM2D PWM2E PWM2F PWM2G PWM2H Legend: PWCR2: PWOCR2: PWPR2: PWCNT2: PWCYR2: PWDTR2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H: PWBFR2A, 2B, 2C, 2D: PWM control register 2 PWM output control register 2 PWM polarity register 2 PWM counter 2 PWM cycle register 2 PWM duty registers 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H PWM buffer registers 2A, 2B, 2C, 2D Figure 19-2 Block Diagram of PWM Channel 2 Rev. 6.00 Feb 22, 2005 page 705 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer 19.1.3 Pin Configuration Table 19-1 shows the PWM pin configuration. Table 19-1 PWM Pin Configuration Name PWM output pin 1A PWM output pin 1B PWM output pin 1C PWM output pin 1D PWM output pin 1E PWM output pin 1F PWM output pin 1G PWM output pin 1H PWM output pin 2A PWM output pin 2B PWM output pin 2C PWM output pin 2D PWM output pin 2E PWM output pin 2F PWM output pin 2G PWM output pin 2H Abbrev. PWM1A PWM1B PWM1C PWM1D PWM1E PWM1F PWM1G PWM1H PWM2A PWM2B PWM2C PWM2D PWM2E PWM2F PWM2G PWM2H I/O Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Function Channel 1A PWM output Channel 1B PWM output Channel 1C PWM output Channel 1D PWM output Channel 1E PWM output Channel 1F PWM output Channel 1G PWM output Channel 1H PWM output Channel 2A PWM output Channel 2B PWM output Channel 2C PWM output Channel 2D PWM output Channel 2E PWM output Channel 2F PWM output Channel 2G PWM output Channel 2H PWM output Rev. 6.00 Feb 22, 2005 page 706 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer 19.1.4 Register Configuration Table 19-2 shows the register configuration of the PWM. Table 19-2 PWM Registers Channel 1 Name PWM control register 1 PWM output control register 1 PWM polarity register 1 PWM cycle register 1 PWM buffer register 1A PWM buffer register 1C PWM buffer register 1E PWM buffer register 1G 2 PWM control register 2 PWM output control register 2 PWM polarity register 2 PWM cycle register 2 PWM buffer register 2A PWM buffer register 2B PWM buffer register 2C PWM buffer register 2D All Note: Module stop control register D 1. Lower 16 bits of the address. Abbrev. PWCR1 PWOCR1 PWPR1 PWCYR1 PWBFR1A PWBFR1C PWBFR1E PWBFR1G PWCR2 PWOCR2 PWPR2 PWCYR2 PWBFR2A PWBFR2B PWBFR2C PWBFR2D MSTPCRD R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'C0 H'00 H'00 H'FFFF H'EC00 H'EC00 H'EC00 H'EC00 H'C0 H'00 H'00 H'FFFF H'EC00 H'EC00 H'EC00 H'EC00 B'11****** Address*1 H'FC00 H'FC02 H'FC04 H'FC06 H'FC08 H'FC0A H'FC0C H'FC0E H'FC10 H'FC12 H'FC14 H'FC16 H'FC18 H'FC1A H'FC1C H'FC1E H'FC60 Rev. 6.00 Feb 22, 2005 page 707 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer 19.2 19.2.1 Bit Register Descriptions PWM Control Registers 1 and 2 (PWCR1, PWCR2) 7 -- 1 -- 6 -- 1 -- 5 IE 0 R/W 4 CMF 0 R/W * 3 CST 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value Read/Write Note: * Only 0 can be written, to clear the flag. PWCR is an 8-bit read/write register that performs interrupt enabling, starting/stopping, and counter (PWCNT) clock selection. It also contains a flag that indicates a compare match with the cycle register (PWCYR). PWCR1 is the channel 1 register, and PWCR2 is the channel 2 register. PWCR is initialized to H'C0 upon reset, and in standby mode, watch mode*, subactive mode*, subsleep mode*, and module stop mode. Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions only. These functions cannot be used with the other versions. Bits 7 and 6--Reserved: They are always read as 1 and cannot be modified. Bit 5--Interrupt Enable (IE): Bit 5 selects enabling or disabling of an interrupt in the event of a compare match with the PWCYR register for the corresponding channel. Bit 5: IE 0 1 Description Interrupt disabled Interrupt enabled (Initial value) Rev. 6.00 Feb 22, 2005 page 708 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer Bit 4--Compare Match Flag (CMF): Bit 4 indicates the occurrence of a compare match with the PWCYR register for the corresponding channel. Bit 4: CMF 0 Description [Clearing conditions] * * 1 When 0 is written to CMF after reading CMF = 1 When the DTC is activated by a compare match interrupt, and the DISEL bit in the DTC's MRB register is 0 When PWCNT = PWCYR (Initial value) [Setting condition] * Bit 3--Counter Start (CST): Bit 3 selects starting or stopping of the PWCNT counter for the corresponding channel. Bit 3: CST 0 1 Description PWCNT is stopped PWCNT is started (Initial value) Bits 2 to 0--Clock Select (CKS): Bits 2 to 0 select the clock for the PWCNT counter in the corresponding channel. Bit 2: CKS2 0 Bit 1: CKS1 0 1 1 * Bit 0: CKS0 0 1 0 1 * Description Internal clock: counts on /1 Internal clock: counts on /2 Internal clock: counts on /4 Internal clock: counts on /8 Internal clock: counts on /16 *: Don't care (Initial value) Rev. 6.00 Feb 22, 2005 page 709 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer 19.2.2 PWOCR1 Bit PWM Output Control Registers 1 and 2 (PWOCR1, PWOCR2) 7 OE1H 0 R/W 6 OE1G 0 R/W 5 OE1F 0 R/W 4 OE1E 0 R/W 3 OE1D 0 R/W 2 OE1C 0 R/W 1 OE1B 0 R/W 0 OE1A 0 R/W Initial value Read/Write PWOCR2 Bit Initial value Read/Write 7 OE2H 0 R/W 6 OE2G 0 R/W 5 OE2F 0 R/W 4 OE2E 0 R/W 3 OE2D 0 R/W 2 OE2C 0 R/W 1 OE2B 0 R/W 0 OE2A 0 R/W PWOCR is an 8-bit read/write register that enables or disables PWM output. PWOCR1 controls outputs PWM1H to PWM1A, and PWOCR2 controls outputs PWM2H to PWM2A. PWOCR is initialized to H'00 upon reset, and in standby mode, watch mode*, subactive mode*, subsleep mode*, and module stop mode. Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used with the other versions. Bits 7 to 0--Output Enable (OE): Each of these bits enables or disables the corresponding PWM output. Bits 7 to 0: OE 0 1 Description PWM output is disabled PWM output is enabled (Initial value) Rev. 6.00 Feb 22, 2005 page 710 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer 19.2.3 PWPR1 Bit PWM Polarity Registers 1 and 2 (PWPR1, PWPR2) 7 OPS1H 0 R/W 6 OPS1G 0 R/W 5 OPS1F 0 R/W 4 OPS1E 0 R/W 3 OPS1D 0 R/W 2 OPS1C 0 R/W 1 OPS1B 0 R/W 0 OPS1A 0 R/W Initial value Read/Write PWPR2 Bit Initial value Read/Write 7 OPS2H 0 R/W 6 OPS2G 0 R/W 5 OPS2F 0 R/W 4 OPS2E 0 R/W 3 OPS2D 0 R/W 2 OPS2C 0 R/W 1 OPS2B 0 R/W 0 OPS2A 0 R/W PWPR is an 8-bit read/write register that selects the PWM output polarity. PWPR1 controls outputs PWM1H to PWM1A, and PWPR2 controls outputs PWM2H to PWM2A. PWPR is initialized to H'00 upon reset, and in standby mode, watch mode*, subactive mode*, subsleep mode*, and module stop mode. Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used with the other versions. Bits 7 to 0--Output Polarity Select (OPS): Each of these bits selects the polarity of the corresponding PWM output. Bits 7 to 0: OPS 0 1 Description PWM direct output PWM inverse output (Initial value) Rev. 6.00 Feb 22, 2005 page 711 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer 19.2.4 Bit PWM Counters 1 and 2 (PWCNT1, PWCNT2) 15 -- 1 -- 14 -- 1 -- 13 -- 1 -- 12 -- 1 -- 11 -- 1 -- 10 -- 1 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 9 8 7 6 5 4 3 2 1 0 Initial value Read/Write PWCNT is a 10-bit up-counter incremented by the input clock. The input clock is selected by clock select bits 2 to 0 (CKS2 to CKS0) in PWCR. PWCNT1 is used as the channel 1 time base, and PWCNT2 as the channel 2 time base. PWCNT is initialized to H'FC00 when the counter start bit (CST) in PWCR is cleared to 0, and also upon reset and in standby mode, watch mode*, subactive mode*, subsleep mode*, and module stop mode. Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used with the other versions. Rev. 6.00 Feb 22, 2005 page 712 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer 19.2.5 Bit PWM Cycle Registers 1 and 2 (PWCYR1, PWCYR2) 15 -- 1 -- 14 -- 1 -- 13 -- 1 -- 12 -- 1 -- 11 -- 1 -- 10 -- 1 1 1 1 1 1 1 1 1 1 1 -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 9 8 7 6 5 4 3 2 1 0 Initial value Read/Write PWCYR is a 16-bit read/write register that sets the PWM conversion cycle. When a PWCYR compare match occurs, PWCNT is cleared and data is transferred from the buffer register (PWBFR) to the duty register (PWDTR). PWCYR1 is used for the channel 1 conversion cycle setting, and PWCYR2 for the channel 2 conversion cycle setting. PWCYR should be written to only while PWCNT is stopped. A value of H'FC00 must not be set. PWCYR is initialized to H'FFFF upon reset, and in standby mode, watch mode*, subactive mode*, subsleep mode*, and module stop mode. Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used with the other versions. Compare match PWCNT (lower 10 bits) PWCYR (lower 10 bits) 0 1 Compare match N-2 N-1 0 1 N Figure 19-3 Cycle Register Compare Match Rev. 6.00 Feb 22, 2005 page 713 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer 19.2.6 Bit PWM Duty Registers 1A, 1C, 1E, 1G (PWDTR1A, 1C, 1E, 1G) 15 -- 1 -- 14 -- 1 -- 13 1 -- 12 0 -- 11 1 -- 10 1 -- 9 0 -- 8 0 -- 7 0 -- 6 0 -- 5 0 -- 4 0 -- 3 0 -- 2 0 -- 1 0 -- 0 0 -- -- OTS -- -- DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 Initial value Read/Write There are four PWDTR1x registers (PWDTR1A, 1C, 1E, 1G). PWDTR1A is used for outputs PWM1A and PWM1B, PWDTR1C for outputs PWM1C and PWM1D, PWDTR1E for outputs PWM1E and PWM1F, and PWDTR1G for outputs PWM1G and PWM1H. PWDTR1 cannot be read or written to directly. When a PWCYR1 compare match occurs, data is transferred from buffer register 1 (PWBFR1) to PWDTR1. PWDTR1x is initialized to H'EC00 when the counter start bit (CST) in PWCR1 is cleared to 0, and also upon reset and in standby mode, watch mode*, subactive mode*, subsleep mode*, and module stop mode. Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used with the other versions. Bits 15 to 13--Reserved: These bits cannot be read from or written to. Rev. 6.00 Feb 22, 2005 page 714 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer Bit 12--Output Terminal Select (OTS): Bit 12 selects the pin used for PWM output according to the value in bit 12 in the buffer register that is transferred by a PWCYR1 compare match. Unselected pins output a low level (or a high level when the corresponding bit in PWPR1 is set to 1). Register PWDTR1A PWDTR1C PWDTR1E PWDTR1G Bit 12: OTS 0 1 0 1 0 1 0 1 Description PWM1A output selected PWM1B output selected PWM1C output selected PWM1D output selected PWM1E output selected PWM1F output selected PWM1G output selected PWM1H output selected (Initial value) (Initial value) (Initial value) (Initial value) Bits 11 and 10--Reserved: These bits cannot be read from or written to. Bits 9 to 0--Duty (DT): Bits 9 to 0 set the PWM output duty according to the values in bits 9 to 0 in the buffer register that is transferred by a PWCYR1 compare match. A high level (or a low level when the corresponding bit in PWPR1 is set to 1) is output from the time PWCNT1 is cleared by a PWCYR1 compare match until a PWDTR1 compare match occurs. When all the bits are 0, there is no high-level output period (no low-level output period when the corresponding bit in PWPR1 is set to 1). Compare match PWCNT1 (lower 10 bits) PWCYR1 (lower 10 bits) PWDTR1 (lower 10 bits) PWM output on selected pin PWM output on unselected pin 0 1 M-2 M-1 M N-1 0 N M Figure 19-4 Duty Register Compare Match (OPS = 0 in PWPR1) Rev. 6.00 Feb 22, 2005 page 715 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer PWCNT1 (lower 10 bits) PWCYR1 (lower 10 bits) PWDTR1 (lower 10 bits) PWM output (M = 0) PWM output (0 < M < N) PWM output (N M) 0 1 N-2 N-1 0 N M Figure 19-5 Differences in PWM Output According to Duty Register Set Value (OPS = 0 in PWPR1) 19.2.7 Bit Initial value Read/Write PWM Buffer Registers 1A, 1C, 1E, 1G (PWBFR1A, 1C, 1E, 1G) 15 -- 1 -- 14 -- 1 -- 13 1 12 0 11 1 10 1 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 -- OTS -- -- R/W -- -- DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W There are four 16-bit read/write PWBFR1 registers (PWBFR1A, 1C, 1E, 1G). When a PWCYR1 compare match occurs, data is transferred from PWBFR1A to PWDTR1A, from PWBFR1C to PWDTR1C, from PWBFR1E to PWDTR1E, and from PWBFR1G to PWDTR1G. PWBFR1 is initialized to H'EC00 upon reset, and in standby mode, watch mode*, subactive mode*, subsleep mode*, and module stop mode. Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used with the other versions. Rev. 6.00 Feb 22, 2005 page 716 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer Bits 15 to 13--Reserved: They are always read as 1 and cannot be modified. Bit 12--Output Terminal Select (OTS): Bit 12 is the data transferred to bit 12 of PWDTR1. Bits 11 and 10--Reserved: They are always read as 1 and cannot be modified. Bits 9 to 0--Duty (DT): Bits 9 to 0 comprise the data transferred to bits 9 to 0 in PWDTR1. 19.2.8 Bit Initial value Read/Write PWM Duty Registers 2A to 2H (PWDTR2A to PWDTR2H) 15 -- 1 -- 14 -- 1 -- 13 -- 1 -- 12 -- 0 -- 11 -- 1 -- 10 1 -- 9 0 -- 8 0 -- 7 0 -- 6 0 -- 5 0 -- 4 0 -- 3 0 -- 2 0 -- 1 0 -- 0 0 -- -- DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 There are eight PWDTR2 registers (PWDTR2A to PWDTR2H). PWDTR2A is used for output PWM2A, PWDTR2B for output PWM2B, PWDTR2C for output PWM2C, PWDTR2D for output PWM2D, PWDTR2E for output PWM2E, PWDTR2F for output PWM2F, PWDTR2G for output PWM2G, and PWDTR2H for output PWM2H. PWDTR2 cannot be read or written to directly. When a PWCYR2 compare match occurs, data is transferred from buffer register 2 (PWBFR2) to PWDTR2. PWDTR2 is initialized to H'EC00 when the counter start bit (CST) in PWCR2 is cleared to 0, and also upon reset and in standby mode, watch mode*, subactive mode*, subsleep mode*, and module stop mode. Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used with the other versions. Bits 15 to 10--Reserved: These bits cannot be read from or written to. Rev. 6.00 Feb 22, 2005 page 717 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer Bits 9 to 0--Duty (DT): Bits 9 to 0 set the PWM output duty according to the values in bits 9 to 0 in the buffer register that is transferred by a PWCYR2 compare match. A high level (or a low level when the corresponding bit in PWPR2 is set to 1) is output from the time PWCNT2 is cleared by a PWCYR2 compare match until a PWDTR2 compare match occurs. When all the bits are 0, there is no high-level output period (no low-level output period when the corresponding bit in PWPR2 is set to 1). Compare match PWCNT2 (lower 10 bits) PWCYR2 (lower 10 bits) PWDTR2 (lower 10 bits) PWM output 0 1 M-2 M-1 M N-1 0 N M Figure 19-6 Duty Register Compare Match (OPS = 0 in PWPR2) PWCNT2 (lower 10 bits) PWCYR2 (lower 10 bits) PWDTR2 (lower 10 bits) PWM output (M = 0) PWM output (0 < M < N) PWM output (N M) 0 1 N-2 N-1 0 N M Figure 19-7 Differences in PWM Output According to Duty Register Set Value (OPS = 0 in PWPR2) Rev. 6.00 Feb 22, 2005 page 718 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer 19.2.9 Bit PWM Buffer Registers 2A to 2D (PWBFR2A to PWBFR2D) 15 -- 1 -- 14 -- 1 -- 13 1 12 0 11 1 10 1 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 -- TDS -- -- R/W -- -- DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value Read/Write There are four 16-bit read/write PWBFR2 registers (PWBFR2A to PWBFR2D). When a PWCYR2 compare match occurs, data is transferred from PWBFR2A to PWDTR2A or PWDTR2E, from PWBFR2B to PWDTR2B or PWDTR2F, from PWBFR2C to PWDTR2C or PWDTR2G, and from PWBFR2D to PWDTR2D or PWDTR2H. The transfer destination is determined by the value of the TDS bit. PWBFR2 is initialized to H'EC00 upon reset, and in standby mode, watch mode*, subactive mode*, subsleep mode*, and module stop mode. Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used with the other versions. Bits 15 to 13--Reserved: They are always read as 1 and cannot be modified. Bit 12--Transfer Destination Select (TDS): Bit 12 selects the PWDTR2 register to which data is to be transferred. Register PWBFR2A PWBFR2B PWBFR2C PWBFR2D Bit 12: TDS 0 1 0 1 0 1 0 1 Description PWDTR2A selected PWDTR2E selected PWDTR2B selected PWDTR2F selected PWDTR2C selected PWDTR2G selected PWDTR2D selected PWDTR2H selected (Initial value) (Initial value) (Initial value) (Initial value) Bits 11 and 10--Reserved: They are always read as 1 and cannot be modified. Bits 9 to 0--Duty (DT): Bits 9 to 0 comprise the data transferred to bits 9 to 0 in PWDTR2. Rev. 6.00 Feb 22, 2005 page 719 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer 19.2.10 Module Stop Control Register D (MSTPCRD) Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 4 3 2 1 0 MSTPD7 MSTPD6 MSTPD5 MSTPD4 MSTPD3 MSTPD2 MSTPD1 MSTPD0 undefined undefined undefined undefined undefined undefined -- -- -- -- -- -- MSTPCRD is an 8-bit read/write register that performs module stop mode control. When the MSTPD7 bit is set to 1, PWM timer operation is stopped at the end of the bus cycle, and module stop mode is entered. For details, see section 23A.5, 23B.5, Module Stop Mode. MSTPCRD is initialized by a reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bit 7--Module Stop (MSTPD7): Bit 7 specifies the PWM module stop mode. Bit 7: MSTPD7 0 1 Description PWM module stop mode is cleared PWM module stop mode is set (Initial value) Rev. 6.00 Feb 22, 2005 page 720 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer 19.3 19.3.1 Bus Master Interface 16-Bit Data Registers PWCYR1/2, PWBFR1A/C/E/G, and PWBFR2A/B/C/D are 16-bit registers. These registers are linked to the bus master by a 16-bit data bus, and can be read or written in 16-bit units. They cannot be read by 8-bit access; 16-bit access must always be used. Internal data bus H Bus master L Bus interface Module data bus PWCYR1 Figure 19-8 16-Bit Register Access Operation (Bus Master PWCYR1 (16 Bits)) 19.3.2 8-Bit Data Registers PWCR1/2, PWOCR1/2, and PWPR1/2 are 8-bit registers that can be read and written to in 8-bit units. These registers are linked to the bus master by a 16-bit data bus, and can be read or written by 16-bit access; in this case, the lower 8 bits will always be read as H'FF. Internal data bus H Bus master L Bus interface Module data bus PWCR1 Figure 19-9 8-Bit Register Access Operation (Bus Master PWCR1 (Upper 8 Bits)) Rev. 6.00 Feb 22, 2005 page 721 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer 19.4 19.4.1 Operation PWM Channel 1 Operation PWM waveforms are output from pins PWM1A to PWM1H as shown in figure 19-10. Initial Settings: Set the PWM output polarity in PWPR1; enable the pins for PWM output with PWOCR1; select the clock to be input to PWCNT1 with bits CKS2 to CKS0 in PWCR1; set the PWM conversion cycle in PWCYR1; and set the first frame of data in PWBFR1A, PWBFR1C, PWBFR1E, and PWBFR1G. Activation: When the CST bit in PWCR1 is set to 1, a compare match between PWCNT1 and PWCYR1 is generated. Data is transferred from PWBFR1A to PWDTR1A, from PWBFR1C to PWDTR1C, from PWBFR1E to PWDTR1E, and from PWBFR1G to PWDTR1G. PWCNT1 starts counting up. At the same time the CMF bit in PWCR1 is set, so that, if the IE bit in PWCR1 has been set, an interrupt can be requested or the DTC can be activated. Waveform Output: The PWM outputs selected by the OTS bits in PWDTR1A/C/E/G go high when a compare match occurs between PWCNT1 and PWCYR1. The PWM outputs not selected by the OTS bits are low. When a compare match occurs between PWCNT1 and PWDTR1A/C/E/G, the corresponding PWM output goes low. If the corresponding bit in PWPR1 is set to 1, the output is inverted. PWCYR1 PWBFR1A PWDTR1A OTS (PWDTR1A) = 0 OTS (PWDTR1A) = 1 OTS (PWDTR1A) = 0 OTS (PWDTR1A) = 1 PWM1A PWM1B Figure 19-10 PWM Channel 1 Operation Rev. 6.00 Feb 22, 2005 page 722 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer Next Frame: When a compare match occurs between PWCNT1 and PWCYR1, data is transferred from PWBFR1A to PWDTR1A, from PWBFR1C to PWDTR1C, from PWBFR1E to PWDTR1E, and from PWBFR1G to PWDTR1G. PWCNT1 is reset and starts counting up from H'000. The CMF bit in PWCR1 is set, and if the IE bit in PWCR1 has been set, an interrupt can be requested or the DTC can be activated. Stopping: When the CST bit in PWCR1 is cleared to 0, PWCNT1 is reset and stops. All PWM outputs go low (or high if the corresponding bit in PWPR1 is set to 1). 19.4.2 PWM Channel 2 Operation PWM waveforms are output from pins PWM2A to PWM2H as shown in figure 19-11. Initial Settings: Set the PWM output polarity in PWPR2; enable the pins for PWM output with PWOCR2; select the clock to be input to PWCNT2 with bits CKS2 to CKS0 in PWCR2; set the PWM conversion cycle in PWCYR2; and set the first frame of data in PWBFR2A, PWBFR2B, PWBFR2C, and PWBFR2D. Activation: When the CST bit in PWCR2 is set to 1, a compare match between PWCNT2 and PWCYR2 is generated. Data is transferred from PWBFR2A to PWDTR2A or PWDTR2E, from PWBFR2B to PWDTR2B or PWDTR2F, from PWBFR2C to PWDTR2C or PWDTR2G, and from PWBFR2D to PWDTR2D or PWDTR2H, according to the value of the TDS bit. PWCNT2 starts counting up. At the same time the CMF bit in PWCR2 is set, so that, if the IE bit in PWCR2 has been set, an interrupt can be requested or the DTC can be activated. Waveform Output: The PWM outputs go high when a compare match occurs between PWCNT2 and PWCYR2. When a compare match occurs between PWCNT2 and PWDTR2A to PWDTR2H, the corresponding PWM output goes low. If the corresponding bit in PWPR2 is set to 1, the output is inverted. Rev. 6.00 Feb 22, 2005 page 723 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer PWCYR2 PWBFR2A PWDTR2A PWDTR2E TDS (PWBFR2A) = 0 TDS (PWBFR2A) = 1 TDS (PWBFR2A) = 0 PWM2A PWM2B Figure 19-11 PWM Channel 2 Operation Next Frame: When a compare match occurs between PWCNT2 and PWCYR2, data is transferred from PWBFR2A to PWDTR2A or PWDTR2E, from PWBFR2B to PWDTR2B or PWDTR2F, from PWBFR2C to PWDTR2C or PWDTR2G, and from PWBFR2D to PWDTR2D or PWDTR2H, according to the value of the TDS bit. PWCNT2 is reset and starts counting up from H'000. The CMF bit in PWCR2 is set, and if the IE bit in PWCR2 has been set, an interrupt can be requested or the DTC can be activated. Stopping: When the CST bit in PWCR2 is cleared to 0, PWCNT2 is reset and stops. PWDTR2A to PWDTR2H are reset. All PWM outputs go low (or high if the corresponding bit in PWPR2 is set to 1). Rev. 6.00 Feb 22, 2005 page 724 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer 19.5 Usage Note Contention between Buffer Register Write and Compare Match If a PWBFR write is performed in the state immediately after a cycle register compare match, the PWM output does not change, but as the duty register is also rewritten at the same time as the buffer register, normal PWM output will not be achieved. If a PWBFR write is performed in the state immediately after a cycle register compare match, the buffer register and duty register are overwritten. PWM output changed by the cycle register compare match is not changed in the overwrite of the duty register due to contention. This may result in unanticipated duty output. In the case of channel 2, the duty register used as the transfer destination is selected by the TDS bit of the buffer register when an overwrite of the duty register occurs due to contention. This can also result in an unintended overwrite of the duty register. Buffer register rewriting must be completed before automatic transfer by the DTC* (data transfer controller), exception handling due to a compare match interrupt, or the occurrence of a cycle register compare match on detection of the rise of CMF (compare match flag) in PWCR. Note: * The DTC is not implemented in the H8S/2635 and H8S/2634. T1 Address Write signal PWCNT (lower 10 bits) PWBFR PWDTR PWM output CMF TW TW T2 Buffer register address Compare match 0 N N M M Figure 19-12 PWM Channel 1 Operation Rev. 6.00 Feb 22, 2005 page 725 of 1484 REJ09B0103-0600 Section 19 Motor Control PWM Timer Rev. 6.00 Feb 22, 2005 page 726 of 1484 REJ09B0103-0600 Section 20 RAM Section 20 RAM Note: The H8S/2635 Group is not equipped with a DTC. 20.1 Overview The H8S/2636 has 4 kbytes, and H8S/2638, H8S/2639, and H8S/2630 have 16 kbytes of on-chip high-speed static RAM. The H8S/2635 has 6 kbytes of on-chip RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. This makes it possible to perform fast word data transfer. The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the system control register (SYSCR). 20.1.1 Block Diagram Figure 20-1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FFE000 H'FFE002 H'FFE004 H'FFE001 H'FFE003 H'FFE005 H'FFEFBE H'FFFFC0 H'FFEFBF H'FFFFC1 H'FFFFFE H'FFFFFF Figure 20-1 (a) Block Diagram of RAM (H8S/2636) Rev. 6.00 Feb 22, 2005 page 727 of 1484 REJ09B0103-0600 Section 20 RAM Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FFB000 H'FFB002 H'FFB004 H'FFB001 H'FFB003 H'FFB005 H'FFBFBE H'FFFFC0 H'FFBFBF H'FFFFC1 H'FFFFFE H'FFFFFF Figure 20-1 (b) Block Diagram of RAM (H8S/2638, H8S/2639, and H8S/2630) Rev. 6.00 Feb 22, 2005 page 728 of 1484 REJ09B0103-0600 Section 20 RAM Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FFD800 H'FFD802 H'FFD804 H'FFD801 H'FFD803 H'FFD805 H'FFBFBE H'FFFFC0 H'FFBFBF H'FFFFC1 H'FFFFFE H'FFFFFF Figure 20-1 (c) Block Diagram of RAM (H8S/2635 Group) 20.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 20-1 shows the address and initial value of SYSCR. Table 20-1 RAM Register Name System control register Abbreviation SYSCR R/W R/W Initial Value H'01 Address* H'FDE5 Note: * Lower 16 bits of the address. Rev. 6.00 Feb 22, 2005 page 729 of 1484 REJ09B0103-0600 Section 20 RAM 20.2 20.2.1 Bit Register Descriptions System Control Register (SYSCR) : 7 MACS 0 R/W 3/4 3/4 0 6 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 3/4 0 R/W 2 3/4 3/4 0 1 0 RAME 1 R/W Initial value : R/W : The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in SYSCR, see section 3.2.2, System Control Register (SYSCR). Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) 20.3 Operation When the RAME bit is set to 1, accesses to addresses H'FFE000 to H'FFEFBF (for the H8S/2636), H'FFB000 to H'FFEFBF (for the H8S/2638, H8S/2639, and H8S/2630), H'FFD800 to H'FFEFBF (for the H8S/2635 Group), or H'FFFFC0 to H'FFFFFF in the chip are directed to the on-chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to and read in byte or word units. Each type of access can be performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address. Rev. 6.00 Feb 22, 2005 page 730 of 1484 REJ09B0103-0600 Section 20 RAM 20.4 Usage Notes When Using the DTC: DTC register information can be located in addresses H'FFEBC0 to H'FFEFBF. When the DTC is used, the RAME bit must not be cleared to 0. Reserved Areas: Addresses H'FFB000 to H'FFDFFF in the H8S/2636 and H'FFB000 to H'FFD7FF in the H8S/2635 Group are reserved areas that cannot be read or written to. When the RAME bit is cleared to 0, the off-chip address space is accessed. Rev. 6.00 Feb 22, 2005 page 731 of 1484 REJ09B0103-0600 Section 20 RAM Rev. 6.00 Feb 22, 2005 page 732 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) Section 21A ROM (H8S/2636 Group) 21A.1 Overview The H8S/2636 has 128 kbytes of on-chip flash memory, or 128 kbytes of on-chip mask ROM. The ROM is connected to the bus master via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching is thus speeded up, and processing speed increased. The on-chip ROM is enabled and disabled by setting the mode pins (MD2 to MD0). The flash memory version can be erased and programmed on-board, as well as with a specialpurpose PROM programmer. 21A.1.1 Block Diagram Figure 21A-1 shows a block diagram of 128-kbyte ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000002 H'000001 H'000003 H'01FFFE H'01FFFF Figure 21A-1 Block Diagram of ROM (128 kbytes) 21A.1.2 Register Configuration The H8S/2636 operating mode is controlled by the mode pins and the MDCR register. The register configuration is shown in table 21A-1. Rev. 6.00 Feb 22, 2005 page 733 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) Table 21A-1 Register Configuration Register Name Mode control register Abbreviation MDCR R/W R/W Initial Value Undefined Address* H'FDE7 Note: * Lower 16 bits of the address. 21A.2 Register Descriptions 21A.2.1 Mode Control Register (MDCR) Bit: Initial value: R/W: 7 -- 1 R/W 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 MDS2 --* R 1 MDS1 --* R 0 MDS0 --* R Note: * Determined by pins MD2 to MD0. MDCR is an 8-bit register used to monitor the current H8S/2636 Group operating mode. Bit 7--Reserved: Only 1 should be written to these bits. Bits 6 to 3--Reserved: These bits are always read as 0 and cannot be modified. Bits 2 to 0--Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD2 to MD0. MDS2 to MDS0 are read-only bits, and cannot be modified. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a reset. 21A.3 Operation The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. Word data must start at an even address. The on-chip ROM is enabled and disabled by setting the mode pins (MD2, MD1, and MD0). These settings are shown in table 21A-2. Rev. 6.00 Feb 22, 2005 page 734 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) Table 21A-2 Operating Modes and ROM (F-ZTAT Version) Mode Pins Operating Mode Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Mode 8 Mode 9 Mode 10 Mode 11 Mode 12 Mode 13 Mode 14 User program mode (advanced expanded mode with on-chip ROM enabled)*1 User program mode (advanced singlechip mode)*2 1 Boot mode (advanced expanded mode 1 with on-chip ROM enabled)* Boot mode (advanced single-chip mode)*2 -- 1 0 1 Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode -- 1 0 0 1 1 0 1 -- FWE 0 MD2 0 MD1 0 MD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Enabled (128 kbytes) Enabled (128 kbytes) Enabled (128 kbytes) Enabled (128 kbytes) -- Enabled (128 kbytes) Enabled (128 kbytes) -- Disabled On-Chip ROM -- Mode 15 1 Notes: 1. Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced expanded mode with on-chip ROM enabled. 2. Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced single-chip mode. Rev. 6.00 Feb 22, 2005 page 735 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) Table 21A-3 Operating Modes and ROM (Mask ROM Version) Mode Pins Operating Mode Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode 1 1 0 1 -- MD2 0 MD1 0 MD0 0 1 0 1 0 1 0 1 Enabled (128 kbytes) Enabled (128 kbytes) Disabled On-Chip ROM -- Rev. 6.00 Feb 22, 2005 page 736 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.4 Flash Memory Overview 21A.4.1 Features The H8S/2636 has 128 kbytes of on-chip flash memory, or 128 kbytes of on-chip mask ROM. The features of the flash memory are summarized below. * Four flash memory operating modes Program mode Erase mode Program-verify mode Erase-verify mode * Programming/erase methods The flash memory is programmed 128 bytes at a time. Block erase (in single-block units) can be performed. To erase the entire flash memory, each block must be erased in turn. Blocks of 1 kbyte, 8 kbytes, 16 kbytes, 28 kbytes, and 32 kbytes can be erased as required. * Programming/erase times The flash memory programming time is 10 ms (typ.) for simultaneous 128-byte programming, equivalent to 80 s (typ.) per byte, and the erase time is 100 ms (typ.). * Reprogramming capability The flash memory can be reprogrammed up to 100 times. * On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: Boot mode User program mode * Automatic bit rate adjustment With data transfer in boot mode, the LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. * Flash memory emulation in RAM Flash memory programming can be emulated in real time by overlapping a part of RAM onto flash memory. * Protect modes There are two protect modes, hardware and software, which allow protected status to be designated for flash memory program/erase/verify operations. Rev. 6.00 Feb 22, 2005 page 737 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) * Programmer mode Flash memory can be programmed/erased in programmer mode, using a PROM programmer, as well as in on-board programming mode. 21A.4.2 Block Diagram Internal address bus Internal data bus (16 bits) Module bus FLMCR1 FLMCR2 EBR1 EBR2 RAMER FLPWCR Bus interface/controller Operating mode FWE pin Mode pin Flash memory (128 kbytes) Legend: FLMCR1: FLMCR2: EBR1: EBR2: RAMER: FLPWCR: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Flash memory power control register Figure 21A-2 Block Diagram of Flash Memory Rev. 6.00 Feb 22, 2005 page 738 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.4.3 Mode Transitions When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the microcomputer enters an operating mode as shown in figure 21A-3. In user mode, flash memory can be read but not programmed or erased. The boot, user program and programmer modes are provided as modes to write and erase the flash memory. MD1 = 1, MD2 = 1, FWE = 0 Reset state *1 User mode (on-chip ROM enabled) 4-5 = 0 MD1 = 1, MD2 = 1, FWE = 1 4-5 = 0 4-5 = 0 MD2 = 0, MD1 = 1, FWE = 1 *2 FWE = 1 FWE = 0 4-5 = 0 Programmer mode User program mode *1 Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. RAM emulation possible 2. MD0 = 0, MD1 = 0, MD2 = 0, P14 = 0, P16 = 0, PF0 = 1 Figure 21A-3 Flash Memory State Transitions Rev. 6.00 Feb 22, 2005 page 739 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.4.4 On-Board Programming Modes Boot Mode 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host Host Programming control program New application program New application program Chip Boot program Flash memory RAM SCI Chip Boot program Flash memory RAM Boot program area SCI Application program (old version) Application program (old version) Programming control program 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, total flash memory erasure is performed, without regard to blocks. Host 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host New application program Chip Boot program Flash memory RAM Boot program area Flash memory preprogramming erase Programming control program Chip SCI Boot program Flash memory RAM Boot program area New application program Programming control program SCI Program execution state Rev. 6.00 Feb 22, 2005 page 740 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) User Program Mode 1. Initial state The FWE assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory. Host Programming/ erase control program New application program New application program 2. Programming/erase control program transfer When user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to RAM. Host Chip Boot program Flash memory FWE assessment program Chip SCI RAM Boot program Flash memory FWE assessment program SCI RAM Transfer program Transfer program Programming/ erase control program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. Host 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host New application program Chip Boot program Flash memory FWE assessment program Chip SCI RAM Boot program Flash memory FWE assessment program Transfer program Programming/ erase control program Programming/ erase control program SCI RAM Transfer program Flash memory erase New application program Program execution state Rev. 6.00 Feb 22, 2005 page 741 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.4.5 Flash Memory Emulation in RAM Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. SCI Flash memory Emulation block RAM Overlap RAM (emulation is performed on data written in RAM) Application program Execution state Figure 21A-4 Reading Overlap RAM Data in User Mode or User Program Mode When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten. Rev. 6.00 Feb 22, 2005 page 742 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) SCI Flash memory Programming data RAM Overlap RAM (programming data) Programming control program execution state Application program Figure 21A-5 Writing Overlap RAM Data in User Program Mode 21A.4.6 Differences between Boot Mode and User Program Mode Table 21A-4 Differences between Boot Mode and User Program Mode Boot Mode Total erase Block erase Programming control program* Yes No (2) User Program Mode Yes Yes (1) (2) (3) (1) Erase/erase-verify (2) Program/program-verify (3) Emulation Note: * To be provided by the user, in accordance with the recommended algorithm. Rev. 6.00 Feb 22, 2005 page 743 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.4.7 Block Configuration The flash memory is divided into two 32 kbytes blocks, one 28 kbytes block, one 16 kbytes block, two 8 kbytes blocks, and four 1 kbyte blocks. Address H'00000 1 kbyte x 4 28 kbytes 16 kbytes 8 kbytes 128 kbytes 8 kbytes 32 kbytes 32 kbytes Address H'1FFFF Figure 21A-6 Block Configuration Rev. 6.00 Feb 22, 2005 page 744 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.5 Pin Configuration The flash memory is controlled by means of the pins shown in table 21A-5. Table 21A-5 Pin Configuration Pin Name Reset Flash write enable Mode 2 Mode 1 Mode 0 Port F0 Port 16 Port 14 Transmit data Receive data Abbreviation I/O Input Input Input Input Input Input Input Input Output Input Function Reset Flash program/erase protection by hardware Sets LSI operating mode Sets LSI operating mode Sets LSI operating mode Sets LSI operating mode when MD2 = MD1 = MD0 = 0 Sets LSI operating mode when MD2 = MD1 = MD0 = 0 Sets LSI operating mode when MD2 = MD1 = MD0 = 0 Serial transmit data output Serial receive data input FWE MD2 MD1 MD0 PF0 P16 P14 TxD1 RxD1 SER Rev. 6.00 Feb 22, 2005 page 745 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.6 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 21A-6. Table 21A-6 Register Configuration Register Name Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Abbreviation FLMCR1*4 FLMCR2*4 EBR1*4 EBR2*4 RAMER *4 R/W R/W R R/W R/W R/W R/W Initial Value H'00*2 H'00 H'00*3 H'00*3 H'00 H'00*3 Address*1 H'FFA8 H'FFA9 H'FFAA H'FFAB H'FEDB H'FFAC Flash memory power control register FLPWCR*4 Notes: 1. Lower 16 bits of the address. 2. When a high level is input to the FWE pin, the initial value is H'80. 3. When a low level is input to the FWE pin, or if a high level is input and the SWE1 bit in FLMCR1 is not set, these registers are initialized to H'00. 4. FLMCR1, FLMCR2, EBR1, and EBR2, RAMER, and FLPWCR are 8-bit registers. Use byte access on these registers. Rev. 6.00 Feb 22, 2005 page 746 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.7 Register Descriptions 21A.7.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for on-chip flash memory is entered by setting SWE bit to 1 when FWE = 1, then setting the PV or EV bit. Program mode for on-chip flash memory is entered by setting SWE bit to 1 when FWE = 1, then setting the PSU bit, and finally setting the P bit. Erase mode for onchip flash memory is entered by setting SWE bit to 1 when FWE = 1, then setting the ESU bit, and finally setting the E bit. FLMCR1 is initialized by a reset, and in hardware standby mode and software standby mode. Its initial value is H'80 when a high level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes are enabled only in the following cases: Writes to bit SWE of FLMCR1 enabled when FWE = 1, to bits ESU, PSU, EV, and PV when FWE = 1 and SWE = 1, to bit E when FWE = 1, SWE = 1 and ESU = 1, and to bit P when FWE = 1, SWE = 1, and PSU = 1. Bit: Initial value: R/W: 7 FWE --* R 6 SWE 0 R/W 5 ESU 0 R/W 4 PSU 0 R/W 3 EV 0 R/W 2 PV 0 R/W 1 E 0 R/W 0 P 0 R/W Note: * Determined by the state of the FWE pin. Bit 7--Flash Write Enable Bit (FWE): Sets hardware protection against flash memory programming/erasing. Bit 7: FWE 0 1 Description When a low level is input to the FWE pin (hardware-protected state) When a high level is input to the FWE pin Rev. 6.00 Feb 22, 2005 page 747 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) Bit 6--Software Write Enable Bit (SWE): Enables or disables flash memory programming and erasing. Set this bit when setting bits 5 to 0, bits 7 to 0 of EBR1, and bits 1 and 0 of EBR2. Bit 6: SWE 0 1 Description Writes disabled Writes enabled [Setting condition] * When FWE = 1 (Initial value) Bit 5--Erase Setup Bit (ESU): Prepares for a transition to erase mode. Set this bit to 1 before setting the E bit in FLMCR1 to 1. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time. Bit 5: ESU 0 1 Description Erase setup cleared Erase setup [Setting condition] * When FWE = 1 and SWE = 1 (Initial value) Bit 4--Program Setup Bit (PSU): Prepares for a transition to program mode. Set this bit to 1 before setting the P bit in FLMCR1 to 1. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time. Bit 4: PSU 0 1 Description Program setup cleared Program setup [Setting condition] * When FWE = 1 and SWE = 1 (Initial value) Bit 3--Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3: EV 0 1 Description Erase-verify mode cleared Transition to erase-verify mode [Setting condition] * When FWE = 1 and SWE = 1 (Initial value) Rev. 6.00 Feb 22, 2005 page 748 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) Bit 2--Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time. Bit 2: PV 0 1 Description Program-verify mode cleared Transition to program-verify mode [Setting condition] * When FWE = 1 and SWE = 1 (Initial value) Bit 1--Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time. Bit 1: E 0 1 Description Erase mode cleared Transition to erase mode [Setting condition] * When FWE = 1, SWE = 1, and ESU = 1 (Initial value) Bit 0--Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU, ESU, EV, PV, or E bit at the same time. Bit 0: P 0 1 Description Program mode cleared Transition to program mode [Setting condition] * When FWE = 1, SWE = 1, and PSU = 1 (Initial value) Rev. 6.00 Feb 22, 2005 page 749 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.7.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is an 8-bit register used for flash memory operating mode control. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00. Bit: Initial value: R/W: 7 FLER 0 R 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 -- 0 -- 0 -- 0 -- Note: FLMCR2 is a read-only register, and should not be written to. Bit 7--Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state. Bit 7: FLER 0 Description Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] * 1 Reset or hardware standby mode An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] * See section 21A.10.3, Error Protection (Initial value) Bits 6 to 0--Reserved: These bits always read 0. Rev. 6.00 Feb 22, 2005 page 750 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.7.3 Erase Block Register 1 (EBR1) EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be automatically cleared to 0. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 21A-6. Bit: Initial value: R/W: 7 EB7 0 R/W 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W 3 EB3 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W 0 EB0 0 R/W 21A.7.4 Erase Block Register 2 (EBR2) EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin. Bit 0 will be initialized to 0 if bit SWE of FLMCR1 is not set, even though a high level is input to pin FWE. When a bit in EBR2 is set to 1, the corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be automatically cleared to 0. Bits 7 to 2 are reserved and must only be written with 0. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 21A-7. Bit: Initial value: R/W: 7 -- 0 R/W 6 -- 0 R/W 5 -- 0 R/W 4 -- 0 R/W 3 -- 0 R/W 2 -- 0 R/W 1 EB9 0 R/W 0 EB8 0 R/W Rev. 6.00 Feb 22, 2005 page 751 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) Table 21A-7 Flash Memory Erase Blocks (H8S/2636) Block (Size) EB0 (1 kbyte) EB1 (1 kbyte) EB2 (1 kbyte) EB3 (1 kbyte) EB4 (28 kbytes) EB5 (16 kbytes) EB6 (8 kbytes) EB7 (8 kbytes) EB8 (32 kbytes) EB9 (32 kbytes) Addresses H'000000 to H'0003FF H'000400 to H'0007FF H'000800 to H'000BFF H'000C00 to H'000FFF H'001000 to H'007FFF H'008000 to H'00BFFF H'00C000 to H'00DFFF H'00E000 to H'00FFFF H'010000 to H'017FFF H'018000 to H'01FFFF 21A.7.5 RAM Emulation Register (RAMER) RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER initialized to H'00 by a reset and in hardware standby mode. It is not initialized by software standby mode. RAMER settings should be made in user mode or user program mode. Flash memory area divisions are shown in table 21A-8. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bit: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 -- 0 R/W 4 -- 0 R/W 3 RAMS 0 R/W 2 RAM2 0 R/W 1 RAM1 0 R/W 0 RAM0 0 R/W Bits 7 and 6--Reserved: These bits always read 0. Bits 5 and 4--Reserved: Only 0 may be written to these bits. Rev. 6.00 Feb 22, 2005 page 752 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) Bit 3--RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory block are program/erase-protected. Bit 3: RAMS 0 1 Description Emulation not selected Program/erase-protection of all flash memory blocks is disabled Emulation selected Program/erase-protection of all flash memory blocks is enabled (Initial value) Bits 2, 1 and 0--Flash Memory Area Selection: These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM (See table 21A-7). Table 21A-8 Flash Memory Area Divisions (H8S/2636) Addresses H'FFE000 to H'FFE3FF H'000000 to H'0003FF H'000400 to H'0007FF H'000800 to H'000BFF H'000C00 to H'000FFF *: Don't care Block Name RAM area 1 kbyte EB0 (1 kbyte) EB1 (1 kbyte) EB2 (1 kbyte) EB3 (1 kbyte) RAMS 0 1 1 1 1 RAM2 * 0 0 1 1 RAM1 * 0 1 0 1 RAM0 * * * * * 21A.7.6 Flash Memory Power Control Register (FLPWCR) Bit: Initial value: R/W: 7 PDWND 0 R/W 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode*. Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask version only. These functions cannot be used with the other versions. Rev. 6.00 Feb 22, 2005 page 753 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) Bit 7--Power-Down Disable (PDWND): Enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. For details, see section 21A.14, Flash Memory and Power-Down States. The subactive mode can be used in the U-mask version only. When writing to this bit in other versions, be sure to write 0. Bit 7: PDWND 0 1 Description Transition to flash memory power-down mode enabled Transition to flash memory power-down mode disabled (Initial value) Bits 6 to 0--Reserved: These bits always read 0. 21A.8 On-Board Programming Modes When pins are set to on-board programming mode and a reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 21A-9. For a diagram of the transitions to the various flash memory modes, see figure 21A-3. Table 21A-9 Setting On-Board Programming Modes Mode Boot mode User program mode Expanded mode Single-chip mode Expanded mode Single-chip mode 1 FWE 1 MD2 0 0 1 1 MD1 1 1 1 1 MD0 0 1 0 1 Rev. 6.00 Feb 22, 2005 page 754 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.8.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The SCI channel to be used is set to asynchronous mode. When a reset-start is executed after the LSI's pins have been set to boot mode, the boot program built into the LSI is started and the programming control program prepared in the host is serially transmitted to the LSI via the SCI. In the LSI, the programming control program received via the SCI is written into the programming control program area in on-chip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 21A-7, and the boot mode execution procedure in figure 21A-8. LSI Flash memory Host Write data reception Verify data transmission RxD1 SCI1 TxD1 On-chip RAM Figure 21A-7 System Configuration in Boot Mode Rev. 6.00 Feb 22, 2005 page 755 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate Chip measures low period of H'00 data transmitted by host Chip calculates bit rate and sets value in bit rate register After bit rate adjustment, chip transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, LSI transmits one H'AA data byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte Chip transmits received number of bytes to host as verify data (echo-back) n=1 Host transmits programming control program sequentially in byte units Chip transmits received programming control program to host as verify data (echo-back) Transfer received programming control program to on-chip RAM No Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, chip transmits one H'AA data byte to host Execute programming control program transferred to on-chip RAM n+1n n = N? Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. Figure 21A-8 Boot Mode Execution Procedure Rev. 6.00 Feb 22, 2005 page 756 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) Automatic SCI Bit Rate Adjustment Start bit Stop bit D0 D1 D2 D3 D4 D5 D6 D7 Low period (9 bits) measured (H'00 data) High period (1 or more bits) When boot mode is initiated, the LSI measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The LSI calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the LSI. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host's transmission bit rate and the LSI's system clock frequency, there will be a discrepancy between the bit rates of the host and the LSI. Set the host transfer bit rate at 4,800, 9,600 or 19,200 bps to operate the SCI properly. Table 21A-10 shows host transfer bit rates and system clock frequencies for which automatic adjustment of the LSI bit rate is possible. The boot program should be executed within this system clock range. Table 21A-10 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate Is Possible Host Bit Rate 4,800 bps 9,600 bps 19,200 bps System Clock Frequency for which Automatic Adjustment of LSI Bit Rate Is Possible 4 to 20 MHz 8 to 20 HHz 16 to 20 MHz Note: The system clock frequency used in boot mode is generated by an external crystal oscillator element. PLL frequency multiplication is not used. Rev. 6.00 Feb 22, 2005 page 757 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an area used by the boot program and an area to which the programming control program is transferred via the SCI, as shown in figure 21A-9. The boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host. H'FFE000 Boot program area (2 kbytes) H'FFE7FF H'FFE800 Programming control program area (1.9 kbytes) H'FFEFBF Note: The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note also that the boot program remains in this area of the on-chip RAM even after control branches to the programming control program. Figure 21A-9 RAM Areas in Boot Mode Notes on Use of Boot Mode: * When the chip comes out of reset in boot mode, it measures the low-level period of the input at the SCI's RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes approximately 100 states before the chip is ready to measure the low-level period of the RxD1 pin. * In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. * Interrupts cannot be used while the flash memory is being programmed or erased. * The RxD1 and TxD1 pins should be pulled up on the board. Rev. 6.00 Feb 22, 2005 page 758 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) * Before branching to the programming control program (RAM area H'FFE800), the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD1, goes to the high-level output state (P33DDR = 1, P33DR = 1). The contents of the CPU's internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. The initial values of other on-chip registers are not changed. * Boot mode can be entered by making the pin settings shown in table 21A-9 and executing a reset-start. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the FWE pin and mode pins, and executing reset release*1. Boot mode can also be cleared by a WDT overflow reset. Do not change the mode pin input levels in boot mode, and do not drive the FWE pin low*3 while the boot program is being executed or while flash memory is being programmed or erased. * If the mode pin input levels are changed (for example, from low to high) during a reset, the , ) state of ports with multiplexed address functions and bus control output pins (AS, will change according to the change in the microcomputer's operating mode*2. Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS = 4 states) with respect to the reset release timing. 2. See Appendix D, Pin States. 3. For precautions on applying and disconnecting FWE, see section 21A.15, Flash Memory Programming and Erasing Precautions. 21A.8.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of FWE control and supply of programming data, and storing a program/erase control program in part of the program area as necessary. Rev. 6.00 Feb 22, 2005 page 759 of 1484 REJ09B0103-0600 RWH DR Section 21A ROM (H8S/2636 Group) To select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7), and apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 6 and 7. The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip RAM or external memory. If the program is to be located in external memory, the instruction for writing to flash memory, and the following instruction, should be placed in on-chip RAM. Figure 21A-10 shows the procedure for executing the program/erase control program when transferred to on-chip RAM. Write the FWE assessment program and transfer program (and the program/erase control program if necessary) beforehand MD2, MD1, MD0 = 110, 111 Reset-start Transfer program/erase control program to RAM Branch to program/erase control program in RAM area FWE = high* Execute program/erase control program (flash memory rewriting) Clear FWE Branch to flash memory application program Notes: Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only when the flash memory is programmed or erased. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. * For precautions on applying and disconnecting FWE, see section 21A.15, Flash Memory Programming and Erasing Precautions. Figure 21A-10 User Program Mode Execution Procedure Rev. 6.00 Feb 22, 2005 page 760 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.9 Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes for on-chip flash memory are made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1. The flash memory cannot be read while being programmed or erased. Therefore, the program (user program) that controls flash memory programming/erasing should be located and executed in on-chip RAM or external memory. If the program is to be located in external memory, the instruction for writing to flash memory, and the following instruction, should be placed in on-chip RAM. Also ensure that the DTC is not activated before or after execution of the flash memory write instruction. In the following operation descriptions, wait times after setting or clearing individual bits in FLMCR1 are given as parameters; for details of the wait times, see section 24.1.7, Flash Memory Characteristics. Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU, PSU, EV, PV, E, and P bits in FLMCR1 is executed by a program in flash memory. 2. When programming or erasing, set FWE to 1 (programming/erasing will not be executed if FWE = 0). 3. Programming must be executed in the erased state. Do not perform additional programming on addresses that have already been programmed. Rev. 6.00 Feb 22, 2005 page 761 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) *3 E=1 Erase setup state E=0 Normal mode ESU = 1 ESU = 0 Erase-verify mode Erase mode *1 FWE = 1 FWE = 0 *2 EV = 1 EV = 0 PSU = 1 PSU = 0 On-board SWE = 1 Software programming mode programming Software programming enable disable state SWE = 0 state *4 P=1 Program setup state P=0 Program mode PV = 1 PV = 0 Program-verify mode Notes: In order to perform a normal read of flash memory, SWE must be cleared to 0. Also note that verify-reads can be performed during the programming/erasing process. 1. : Normal mode : On-board programming mode 2. Do not make a state transition by setting or clearing multiple bits simultaneously. 3. After a transition from erase mode to the erase setup state, do not enter erase mode without passing through the software programming enable state. 4. After a transition from program mode to the program setup state, do not enter program mode without passing through the software programming enable state. Figure 21A-11 FLMCR1 Bit Settings and State Transitions Rev. 6.00 Feb 22, 2005 page 762 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.9.1 Program Mode When writing data or programs to flash memory, the program/program-verify flowchart shown in figure 21A-12 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a time. The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N) are shown in table 24-10 in section 24.1.7, Flash Memory Characteristics. Following the elapse of (tsswe) s or more after the SWE bit is set to 1 in FLMCR1, 128-byte data is written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00 and H'80, 128 consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. Set a value greater than (tspsu + tsp + tcp + tcpsu) s as the WDT overflow period. Preparation for entering program mode (program setup) is performed next by setting the PSU bit in FLMCR1. The operating mode is then switched to program mode by setting the P bit in FLMCR1 after the elapse of at least (tspsu) s. The time during which the P bit is set is the flash memory programming time. Make a program setting so that the time for one programming operation is within the range of (tsp) s. The wait time after P bit setting must be changed according to the degree of progress through the programming operation. For details see "Notes on Program/Program-Verify Procedure." Rev. 6.00 Feb 22, 2005 page 763 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.9.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of the given programming time, clear the P bit in FLMCR1, then wait for at least (tcp) s before clearing the PSU bit to exit program mode. After exiting program mode, the watchdog timer setting is also cleared. The operating mode is then switched to program-verify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (tspv) s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (tspvr) s after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 21A-12) and transferred to RAM. After verification of 128 bytes of data has been completed, exit program-verify mode, wait for at least (tcpv) s, then clear the SWE bit in FLMCR1. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. The maximum number of repetitions of the program/program-verify sequence is indicated by the maximum programming count (N). Leave a wait time of at least (tcswe) s after clearing SWE. Notes on Program/Program-Verify Procedure 1. In order to perform 128-byte-unit programming, the lower 8 bits of the write start address must be H'00 or H'80. 2. When performing continuous writing of 128-byte data to flash memory, byte-unit transfer should be used. 128-byte data transfer is necessary even when writing fewer than 128 bytes of data. Write H'FF data to the extra addresses. 3. Verify data is read in word units. 4. The write pulse is applied and a flash memory write executed while the P bit in FLMCR1 is set. In the chip, write pulses should be applied as follows in the program/program-verify procedure to prevent voltage stress on the device and loss of write data reliability. a. After write pulse application, perform a verify-read in program-verify mode and apply a write pulse again for any bits read as 1 (reprogramming processing). When all the 0-write bits in the 128-byte write data are read as 0 in the verify-read operation, the program/program-verify procedure is completed. In the chip, the number of loops in reprogramming processing is guaranteed not to exceed the maximum value of the maximum programming count (N). Rev. 6.00 Feb 22, 2005 page 764 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) b. After write pulse application, a verify-read is performed in program-verify mode, and programming is judged to have been completed for bits read as 0. The following processing is necessary for programmed bits. When programming is completed at an early stage in the program/program-verify procedure: If programming is completed in the 1st to 6th reprogramming processing loop, additional programming should be performed on the relevant bits. Additional programming should only be performed on bits which first return 0 in a verify-read in certain reprogramming processing. When programming is completed at a late stage in the program/program-verify procedure: If programming is completed in the 7th or later reprogramming processing loop, additional programming is not necessary for the relevant bits. c. If programming of other bits is incomplete in the 128 bytes, reprogramming processing should be executed. If a bit for which programming has been judged to be completed is read as 1 in a subsequent verify-read, a write pulse should again be applied to that bit. 5. The period for which the P bit in FLMCR1 is set (the write pulse width) should be changed according to the degree of progress through the program/program-verify procedure. For detailed wait time specifications, see section 24.1.7, Flash Memory Characteristics. Item Wait time after P bit setting Symbol tsp Item When reprogramming loop count (n) is 1 to 6 When reprogramming loop count (n) is 7 or more In case of additional programming processing* Symbol tsp30 tsp200 tsp10 Note: * Additional programming processing is necessary only when the reprogramming loop count (n) is 1 to 6. 6. The program/program-verify flowchart for the H8S/2636 is shown in figure 21A-12. To cover the points noted above, bits on which reprogramming processing is to be executed, and bits on which additional programming is to be executed, must be determined as shown below. Since reprogram data and additional-programming data vary according to the progress of the programming procedure, it is recommended that the following data storage areas (128 bytes each) be provided in RAM. Rev. 6.00 Feb 22, 2005 page 765 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) Reprogram Data Computation Table Result of Verify-Read after Write Pulse (X) Application (V) Result of Operation 0 1 0 1 1 0 1 1 (D) 0 0 1 1 Comments Programming completed: reprogramming processing not to be executed Programming incomplete: reprogramming processing to be executed Still in erased state: no action Legend: (D): Source data of bits on which programming is executed (X): Source data of bits on which reprogramming is executed Additional-Programming Data Computation Table Result of Verify-Read after Write Pulse (Y) (X') Application (V) Result of Operation 0 0 0 Comments Programming by write pulse application judged to be completed: additional programming processing to be executed Programming by write pulse application incomplete: additional programming processing not to be executed Programming already completed: additional programming processing not to be executed Still in erased state: no action 0 1 1 1 1 0 1 1 1 Legend: (Y): Data of bits on which additional programming is executed (X'): Data of bits on which reprogramming is executed in a certain reprogramming loop 7. It is necessary to execute additional programming processing during the course of the chip program/program-verify procedure. However, once 128-byte-unit programming is finished, additional programming should not be carried out on the same address area. When executing reprogramming, an erase must be executed first. Note that normal operation of reads, etc., is not guaranteed if additional programming is performed on addresses for which a program/program-verify operation has finished. Rev. 6.00 Feb 22, 2005 page 766 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) Write pulse application subroutine Start of programming START Set SWE bit in FLMCR1 Wait (tsswe) s Store 128-byte program data in program data area and reprogram data area Sub-Routine Write Pulse WDT enable Set PSU bit in FLMCR1 Wait (tspsu) s Set P bit in FLMCR1 Wait (tsp) s Clear P bit in FLMCR1 Wait (tcp) s Clear PSU bit in FLMCR1 Wait (tcpsu) s Disable WDT Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. *7 *4 *7 Start of programming n=1 m=0 *5*7 End of programming Write 128-byte data in RAM reprogram data area consecutively to flash memory *1 Sub-Routine-Call *7 Write pulse See Note 6 for pulse width Set PV bit in FLMCR1 *7 Wait (tspv) s H'FF dummy write to verify address *7 Wait (tspvr) s End Sub Increment address Note: 6 Write Pulse Width Number of Writes n Write Time (tsp) sec Write data = verify data? Read verify data *7 *2 No m=1 No nn+1 1 2 3 4 5 6 7 8 9 10 11 12 13 30 30 30 30 30 30 200 200 200 200 200 200 200 Yes 6n? Yes Additional-programming data computation Transfer additional-programming data to additional-programming data area Reprogram data computation *4 *3 *4 Transfer reprogram data to reprogram data area 128-byte data verification completed? No 998 999 1000 200 200 200 Yes Clear PV bit in FLMCR1 Reprogram Wait (tcpv) s 6 n? No Note: Use a 10 s write pulse for additional programming. *7 RAM Program data storage area (128 bytes) Yes Successively write 128-byte data from additional1 programming data area in RAM to flash memory * Sub-Routine-Call Write Pulse (Additional programming) Reprogram data storage area (128 bytes) m=0? Yes Clear SWE bit in FLMCR1 Wait (tcswe) s End of programming No n (N)? *7 No Additional-programming data storage area (128 bytes) Yes Clear SWE bit in FLMCR1 Wait (tcswe) s Programming failure *7 Notes: 1. 2. 3. 4. 5. 7. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Verify data is read in 16-bit (word) units. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM. The contents of the reprogram data area and additional data area are modified as programming proceeds. A write pulse of 30 s or 200 s is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths. When writing of additional-programming data is executed, a 10 s write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied. The wait times and value of N are shown in section 24.1.7, Flash Memory Characteristics. Reprogram Data Computation Table Original Data Verify Data Reprogram Data Additional-Programming Data Computation Table (X) 1 0 1 1 Still in erased state; no action Comments Programming completed Programming incomplete; reprogram (D) 0 0 1 1 (V) 0 1 0 1 Reprogram Data (X') 0 0 1 1 Verify Data Additional(V) Programming Data (Y) 0 1 0 1 0 1 1 1 Comments Additional programming to be executed Additional programming not to be executed Additional programming not to be executed Additional programming not to be executed Figure 21A-12 Program/Program-Verify Flowchart Rev. 6.00 Feb 22, 2005 page 767 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.9.3 Erase Mode When erasing flash memory, the single-block erase flowchart shown in figure 21A-13 should be followed. The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and the maximum number of erase operations (N) are shown in table 24-10 in section 24.1.7, Flash Memory Characteristics. To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in erase block register 1 and 2 (EBR1, EBR2) at least (tsswe) s after setting the SWE bit to 1 in FLMCR1. Next, the watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. Set a value greater than (tse) ms + (tsesu + tce + tcesu) s as the WDT overflow period. Preparation for entering erase mode (erase setup) is performed next by setting the ESU bit in FLMCR1. The operating mode is then switched to erase mode by setting the E bit in FLMCR1 after the elapse of at least (tsesu) s. The time during which the E bit is set is the flash memory erase time. Ensure that the erase time does not exceed (tse) ms. Note: With flash memory erasing, preprogramming (setting all memory data in the memory to be erased to all 0) is not necessary before starting the erase procedure. Rev. 6.00 Feb 22, 2005 page 768 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.9.4 Erase-Verify Mode In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the fixed erase time, clear the E bit in FLMCR1, then wait for at least (tce) s before clearing the ESU bit to exit erase mode. After exiting erase mode, the watchdog timer setting is also cleared. The operating mode is then switched to erase-verify mode by setting the EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (tsev) s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (tsevr) s after the dummy write before performing this read operation. If the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. If the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is indicated by the maximum erase count (N). When verification is completed, exit erase-verify mode, and wait for at least (tcev) s. If erasure has been completed on all the erase blocks, clear the SWE bit in FLMCR1, and leave a wait time of at least (tcswe) s. If erasing multiple blocks, set a single bit in EBR1/EBR2 for the next block to be erased, and repeat the erase/erase-verify sequence as before. Rev. 6.00 Feb 22, 2005 page 769 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) Start *1 Perform erasing in block units. Set SWE bit in FLMCR1 Wait (tsswe) s n=1 Set EBR1 or EBR2 Enable WDT Set ESU bit in FLMCR1 Wait (tsesu) s Set E bit in FLMCR1 Wait (tse) ms Clear E bit in FLMCR1 Wait (tce) s Clear ESU bit in FLMCR1 Wait (tcesu) s Disable WDT Set EV bit in FLMCR1 Wait (tsev) s Set block start address as verify address *5 *5 *5 *3 *4 *5 Start of erase *5 Erase halted *5 nn+1 H'FF dummy write to verify address Wait (tsevr) s Increment address Read verify data Verify data = all 1s? Yes No Last address of block? Yes Clear EV bit in FLMCR1 Wait (tcev) s *5 *5 *2 No Clear EV bit in FLMCR1 Wait (tcev) s *5 *5 n (N)? Clear SWE bit in FLMCR1 Wait (tcswe) s End of erasing *5 No Yes Clear SWE bit in FLMCR1 Wait (tcswe) s Erase failure *5 Notes: 1. 2. 3. 4. 5. Prewriting (setting erase block data to all 0s) is not necessary. Verify data is read in 16-bit (word) units. Make only a single-bit specification in the erase block registers (EBR1 and EBR2). Two or more bits must not be set simultaneously. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn. The wait times and the value of N are shown in section 24.1.7, Flash Memory Characteristics. Figure 21A-13 Erase/Erase-Verify Flowchart Rev. 6.00 Feb 22, 2005 page 770 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.10 Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 21A.10.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase block register 2 (EBR2). The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained in the error-protected state (See table 21A-11). Table 21A-11 Hardware Protection Functions Item FWE pin protection Description * When a low level is input to the FWE pin, FLMCR1, FLMCR2, (except bit FLER) EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. In a reset (including a WDT reset) and in standby mode, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. In a reset via the pin, the reset state is not entered unless the pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the pin low for the pulse width specified in the AC Characteristics section. Program Yes Erase Yes Reset/standby protection * Yes Yes SER SER SER * SER Rev. 6.00 Feb 22, 2005 page 771 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.10.2 Software Protection Software protection can be implemented by setting the SWE bit in FLMCR1, erase block register 1 (EBR1), erase block register 2 (EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P or E bit in flash memory control register 1 (FLMCR1), does not cause a transition to program mode or erase mode (See table 21A-12). Table 21A-12 Software Protection Functions Item SWE bit protection Description * Program Erase Yes Setting bit SWE1 in FLMCR1 to 0 will place Yes area on-chip flash memory in the program/ erase-protected state (Execute the program in the on-chip RAM, external memory). Erase protection can be set for individual blocks by settings in erase block register 1 (EBR1) and erase block register 2 (EBR2). Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state. Yes Setting the RAMS bit to 1 in the RAM emulation register (RAMER) places all blocks in the program/erase-protected state. -- Block specification protection * Yes * Emulation protection * Yes 21A.10.3 Error Protection In error protection, an error is detected when chip runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the chip malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. Rev. 6.00 Feb 22, 2005 page 772 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) FLER bit setting conditions are as follows: 1. When the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) 2. Immediately after exception handling (excluding a reset) during programming/erasing 3. When a SLEEP instruction (including software standby) is executed during programming/erasing 4. When the CPU releases the bus to the DTC Error protection is released only by a reset and in hardware standby mode. Figure 21A-14 shows the flash memory state transition diagram. Program mode Erase mode RD VF PR ER FLER = 0 RES = 0 or HSTBY = 0 Reset or standby (hardware protection) RD VF PR ER FLER = 0 Error occurrence (software standby) Error occurrence RES = 0 or HSTBY = 0 RES = 0 or HSTBY = 0 FLMCR1, FLMCR2, EBR1, EBR2 initialization state Error protection mode RD VF PR ER FLER = 1 Software standby mode Software standby mode release Error protection mode (software standby) RD VF PR ER FLER = 1 FLMCR1, FLMCR2, (except bit FLER) EBR1, EBR2 initialization state Legend: RD: Memory read possible VF: Verify-read possible PR: Programming possible ER: Erasing possible RD: VF: PR: ER: Memory read not possible Verify-read not possible Programming not possible Erasing not possible Figure 21A-14 Flash Memory State Transitions Rev. 6.00 Feb 22, 2005 page 773 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.11 Flash Memory Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses cannot be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 21A-15 shows an example of emulation of real-time flash memory programming. Start of emulation program Set RAMER Write tuning data to overlap RAM Execute application program No Tuning OK? Yes Clear RAMER Write to flash memory emulation block End of emulation program Figure 21A-15 Flowchart for Flash Memory Emulation in RAM Rev. 6.00 Feb 22, 2005 page 774 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) This area can be accessed from both the RAM area and flash memory area H'000000 H'000400 H'000800 H'000C00 H'001000 EB0 EB1 EB2 EB3 Flash memory EB4 to EB9 H'FFE000 H'FFE3FF On-chip RAM H'FFEFBF H'01FFFF Figure 21A-16 Example of RAM Overlap Operation Example in which Flash Memory Block Area EB0 is Overlapped 1. Set bits RAMS, RAM2 to RAM0 in RAMER to 1, 0, 0, 0, to overlap part of RAM onto the area (EB0) for which real-time programming is required. 2. Real-time programming is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space (EB0). Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of RAM2 to RAM0 (emulation protection). In this state, setting the P or E bit in flash memory control register 1 (FLMCR1), will not cause a transition to program mode or erase mode. When actually programming or erasing a flash memory area, the RAMS bit should be cleared to 0. 2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. 3. Block area EB0 contains the vector table. When performing RAM emulation, the vector table is needed in the overlap RAM. Rev. 6.00 Feb 22, 2005 page 775 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.12 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI interrupt is disabled when flash memory is being programmed or erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode*1, to give priority to the program or erase operation. There are three reasons for this: 1. Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. In the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly*2, possibly resulting in MCU runaway. 3. If interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. For these reasons, in on-board programming mode alone there are conditions for disabling interrupt, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or MCU operation. All requests, including NMI interrupt, must therefore be restricted inside and outside the MCU when programming or erasing flash memory. NMI interrupt is also disabled in the error-protection state while the P or E bit remains set in FLMCR1. Notes: 1. Interrupt requests must be disabled inside and outside the MCU until the programming control program has completed programming. 2. The vector may not be read correctly in this case for the following two reasons: * If flash memory is read while being programmed or erased (while the P or E bit is set in FLMCR1), correct read data will not be obtained (undetermined values will be returned). * If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. Rev. 6.00 Feb 22, 2005 page 776 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.13 Flash Memory Programmer Mode Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, flash memory read mode, auto-program mode, autoerase mode, and status read mode are supported. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. In programmer mode, set the mode pins to programmer mode (see table 21A-13) and input a 12 MHz input clock. Table 21A-13 shows the pin settings for programmer mode. Table 21A-13 Pin Names Mode pins: MD2, MD1, MD0 Mode setting pins: PF0, P16, P14 FWE pin pin Programmer Mode Pin Settings Settings Low level input to MD2, MD1, and MD0. High level input to PF0, low level input to P16 and P14 High level input (in auto-program and auto-erase modes) Reset circuit Oscillator circuit Internal voltage step-down circuit 21A.13.1 Socket Adapter and Memory Map In programmer mode in which the PROM writer is used, reading from memory (verification), writing, and initializing the flash memory (erasing all of its contents) are enabled. At this time, a dedicated conversion socket adapter must be attached to a general-purpose PROM writer. Table 21A-14 shows the types of the socket adapters. For programmer mode on this LSI, one of the socket adapters listed in table 21A-14 should be used. Table 21A-14 Product Name HD64F2636UF HD64F2636F SER VCL XTAL, EXTAL, PLLCAP, PLLVSS pins Type of Socket Adapter Package Type 128 pin QFP (FP-128B) Socket Adapter Type ME2636ESHF1H HF2636Q128D4001 Manufacturer Minato Electronics Inc. Data I/O Japan Corporation Rev. 6.00 Feb 22, 2005 page 777 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) The memory map of on-chip ROM is shown in figure 21A-17 Addresses in MCU mode H'000000 Addresses in programmer mode H'00000 On-chip ROM space (128 kbytes) H'01FFFF H'1FFFF Figure 21A-17 On-Chip ROM Memory Map 21A.13.2 Programmer Mode Operation Table 21A-15 shows how the different operating modes are set when using programmer mode, and table 21A-16 lists the commands used in programmer mode. Details of each mode are given below. * Memory Read Mode Memory read mode supports byte reads. * Auto-Program Mode Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. * Auto-Erase Mode Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-programming. * Status Read Mode Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the I/O6 signal. In status read mode, error information is output if an error occurs. Rev. 6.00 Feb 22, 2005 page 778 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) Table 21A-15 Settings for Various Operating Modes in Programmer Mode Pin Names Read Output disable Command write Chip disable*1 H or L H or L H or L*3 H or L L L H L X L L H H H X H Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2. Ain indicates that there is also address input in auto-program mode. 3. For command writes in auto-program and auto-erase modes, input a high level to the FWE pin. Table 21A-16 Programmer Mode Commands Number of Cycles 1+n 129 2 2 1st Cycle Mode Write Write Write Write Address X X X X Data H'00 H'40 H'20 H'71 Mode Read Write Write Write 2nd Cycle Address RA WA X X Data Dout Din H'20 H'71 Command Name Memory read mode Auto-program mode Auto-erase mode Status read mode Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n). 21A.13.3 Memory Read Mode 1. After completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. When reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. 2. In memory read mode, command writes can be performed in the same way as in the command wait state. 3. Once memory read mode has been entered, consecutive reads can be performed. 4. After powering on, memory read mode is entered. Rev. 6.00 Feb 22, 2005 page 779 of 1484 REJ09B0103-0600 EW EO EC Mode FWE I/O7 to I/O0 Data output Hi-Z Data input Hi-Z A18 to A0 Ain*2 X Ain*2 X Section 21A ROM (H8S/2636 Group) Table 21A-17 AC Characteristics in Transition to Memory Read Mode Conditions: VCC = 5.0 V 0.5 V, VSS = 0 V, Ta = 25C 5C Item Command write cycle hold time setup time Symbol tnxtc tceh tces tdh tds twep tr tf Min. 20 0 0 50 50 70 -- -- Max. -- -- -- -- -- -- 30 30 Unit s ns ns ns ns ns ns ns Rev. 6.00 Feb 22, 2005 page 780 of 1484 REJ09B0103-0600 EW EW EC EC Data hold time Data setup time Write pulse width rise time fall time Command write A18 to A0 tces CE tceh tnxtc Memory read mode Address stable OE tf WE twep tr tds I/O7 to I/O0 tdh Note: Data is latched on the rising edge of WE. Figure 21A-18 Timing Waveforms for Memory Read after Memory Write Section 21A ROM (H8S/2636 Group) Table 21A-18 AC Characteristics in Transition from Memory Read Mode to Another Mode Conditions: VCC = 5.0 V 0.5 V, VSS = 0 V, Ta = 25C 5C Item Command write cycle hold time setup time Symbol tnxtc tceh tces tdh tds twep tr tf Min. 20 0 0 50 50 70 -- -- Max. -- -- -- -- -- -- 30 30 Unit s ns ns ns ns ns ns ns EW EW EC EC Data hold time Data setup time Write pulse width rise time fall time Memory read mode A18 to A0 Address stable tnxtc CE Other mode command write tces tceh OE tf WE twep tr tds I/O7 to I/O0 Note: Do not enable WE and OE at the same time. tdh Figure 21A-19 Timing Waveforms in Transition from Memory Read Mode to Another Mode Rev. 6.00 Feb 22, 2005 page 781 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) Table 21A-19 AC Characteristics in Memory Read Mode Conditions: VCC = 5.0 V 0.5 V, VSS = 0 V, Ta = 25C 5C Item Access time output delay time output delay time Symbol tacc tce toe tdf toh Min. -- -- -- -- 5 Max. 20 150 150 100 -- Unit s ns ns ns ns A18 to A0 CE Address stable tce toe OE WE VIH tacc toh I/O7 to I/O0 tdf tacc toh Rev. 6.00 Feb 22, 2005 page 782 of 1484 REJ09B0103-0600 EO EC Figure 21A-21 and EO EC EO EC Output disable delay time Data output hold time A18 to A0 Address stable Address stable CE OE WE I/O7 to I/O0 VIL VIL VIH tacc toh tacc toh Figure 21A-20 and Enable State Read Timing Waveforms Address stable tce toe tdf Clock System Read Timing Waveforms Section 21A ROM (H8S/2636 Group) 21A.13.4 Auto-Program Mode 1. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. 2. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. The lower 7 bits of the transfer address must be low. If a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. 4. Memory address transfer is performed in the second cycle (figure 21A-22). Do not perform transfer after the third cycle. 5. Do not perform a command write during a programming operation. 6. Perform one auto-program operation for a 128-byte block for each address. Two or more additional programming operations cannot be performed on a previously programmed address block. 7. Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-program operation end decision pin). 8. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling and . Rev. 6.00 Feb 22, 2005 page 783 of 1484 REJ09B0103-0600 EC EO Section 21A ROM (H8S/2636 Group) Table 21A-20 AC Characteristics in Auto-Program Mode Conditions: VCC = 5.0 V 0.5 V, VSS = 0 V, Ta = 25C 5C Item Command write cycle hold time setup time Symbol tnxtc tceh tces tdh tds twep twsts tspa tas tah twrite tpns tpnh tr tf Min. 20 0 0 50 50 70 1 -- 0 60 1 100 100 -- -- Max. -- -- -- -- -- -- -- 150 -- -- 3000 -- -- 30 30 Unit s ns ns ns ns ns ms ns ns ns ms ns ns ns ns Rev. 6.00 Feb 22, 2005 page 784 of 1484 REJ09B0103-0600 EW EW EC EC Data hold time Data setup time Write pulse width Status polling start time Status polling access time Address setup time Address hold time Memory write time Write setup time Write end setup time rise time fall time FWE tpnh Address stable tpns tces tceh tnxtc tnxtc A18 to A0 CE OE tf twep tr tas tah Data transfer 1 to 128 bytes twsts tspa WE tds tdh twrite Write operation end decision signal I/O7 I/O6 I/O5 to I/O0 Write normal end decision signal H'40 H'00 Figure 21A-22 Auto-Program Mode Timing Waveforms Section 21A ROM (H8S/2636 Group) 21A.13.5 Auto-Erase Mode 1. Auto-erase mode supports only entire memory erasing. 2. Do not perform a command write during auto-erasing. 3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin). 4. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling and . Table 21A-21 AC Characteristics in Auto-Erase Mode Conditions: VCC = 5.0 V 0.5 V, VSS = 0 V, Ta = 25C 5C Item Command write cycle hold time setup time Symbol tnxtc tceh tces tdh tds twep tests tspa terase tens tenh tr tf Min. 20 0 0 50 50 70 1 -- 100 100 100 -- -- Max. -- -- -- -- -- -- -- 150 40000 -- -- 30 30 Unit s ns ns ns ns ns ms ns ms ns ns ns ns Data hold time Data setup time Write pulse width Status polling start time Status polling access time Memory erase time Erase setup time Erase end setup time rise time fall time Rev. 6.00 Feb 22, 2005 page 785 of 1484 REJ09B0103-0600 EC EO EW EW EC EC Section 21A ROM (H8S/2636 Group) FWE tenh A18 to A0 tens tces tceh tnxtc tnxtc CE OE tf twep tr tests tspa WE tds tdh terase Erase end decision signal I/O7 I/O6 I/O5 to I/O0 Erase normal end decision signal H'20 H'20 H'00 Figure 21A-23 Auto-Erase Mode Timing Waveforms Rev. 6.00 Feb 22, 2005 page 786 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.13.6 Status Read Mode 1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. The return code is retained until a command write other than a status read mode command write is executed. Table 21A-22 AC Characteristics in Status Read Mode Conditions: VCC = 5.0 V 0.5 V, VSS = 0 V, Ta = 25C 5C Item Read time after command write hold time setup time Symbol tstd tceh tces tdh tds twep toe tdf tce tr tf Min. 20 0 0 50 50 70 -- -- -- -- -- Max. -- -- -- -- -- -- Unit s ns ns ns ns ns ns ns ns ns ns EW EW EC EO EC EC Data hold time Data setup time Write pulse width output delay time output delay time rise time fall time Disable delay time 150 100 150 30 30 A18 to A0 tces tceh tnxtc tces tceh tnxtc tnxtc CE tce OE tf twep tr tf twep tr toe WE tds tdh H'71 tds H'71 tdh tdf I/O7 to I/O0 Note: I/O2 and I/O3 are undefined. Figure 21A-24 Status Read Mode Timing Waveforms Rev. 6.00 Feb 22, 2005 page 787 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) Table 21A-23 Status Read Mode Return Commands Pin Name I/O7 Attribute Normal end decision I/O6 Command error I/O5 Programming error I/O4 Erase error I/O3 -- I/O2 -- I/O1 I/O0 ProgramEffective ming or address erase count error exceeded 0 0 Count Effective exceeded: 1 address Otherwise: 0 error: 1 Otherwise: 0 Initial value 0 Indications Normal end: 0 Abnormal end: 1 0 Command error: 1 0 0 0 0 -- ProgramErasing -- ming error: 1 Otherwise: 0 error: 1 Otherwise: 0 Otherwise: 0 Note: I/O2 and I/O3 are undefined. 21A.13.7 Status Polling 1. The I/O7 status polling flag indicates the operating status in auto-program/auto-erase mode. 2. The I/O6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase mode. Table 21A-24 Status Polling Output Truth Table Pin Name I/O7 I/O6 I/O0 to I/O5 During Internal Operation 0 0 0 Abnormal End 1 0 0 -- 0 1 0 Normal End 1 1 0 21A.13.8 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 21A-25 Stipulated Transition Times to Command Wait State Item Standby release (oscillation stabilization time) Programmer mode setup time VCC hold time Symbol tosc1 tbmv tdwn Min. 30 10 0 Max. -- -- -- Unit ms ms ms Rev. 6.00 Feb 22, 2005 page 788 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) tosc1 VCC tbmv Memory read mode Command Auto-program mode wait state Auto-erase mode Command wait state Normal/abnormal end decision tdwn 4-5 FWE Note: When using other than the automatic write mode and automatic erase mode, drive the FWE input pin low. Figure 21A-25 Oscillation Stabilization Time, Boot Program Transfer Time, and Power-Down Sequence 21A.13.9 Notes on Memory Programming 1. When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. 2. When performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level. 2. Auto-programming should be performed once only on the same address block. Additional programming cannot be performed on previously programmed address blocks. Rev. 6.00 Feb 22, 2005 page 789 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 21A.14 Flash Memory and Power-Down States In addition to its normal operating state, the flash memory has power-down states in which power consumption is reduced by halting part or all of the internal power supply circuitry. There are three flash memory operating states: (1) Normal operating mode: The flash memory can be read and written to. (2) Power-down mode: Part of the power supply circuitry is halted, and the flash memory can be read when the LSI is operating on the subclock*. (3) Standby mode: All flash memory circuits are halted, and the flash memory cannot be read or written to. States (2) and (3) are flash memory power-down states. Table 21A-26 shows the correspondence between the operating states of the LSI and the flash memory. Table 21A-26 Flash Memory Operating States Flash Memory Operating State Normal mode (read/write) LSI Operating State High-speed mode Medium-speed mode Sleep mode Subactive mode* Subsleep mode* Watch mode* Software standby mode Hardware standby mode When PDWND = 0: Power-down mode (read-only) When PDWND = 1: Normal mode (read-only) Standby mode Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask version only. These functions cannot be used with the other versions. 21A.14.1 Notes on Power-Down States 1. When the flash memory is in a power-down state, part or all of the internal power supply circuitry is halted. Therefore, a power supply circuit stabilization period must be provided when returning to normal operation. When the flash memory returns to its normal operating state from a power-down state, bits STS2 to STS0 in SBYCR must be set to provide a wait time of at least 20 s (power supply stabilization time), even if an oscillation stabilization period is not necessary. Rev. 6.00 Feb 22, 2005 page 790 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 2. In a power-down state, FLMCR1, FLMCR2, EBR1, EBR2, RAMER, and FLPWCR cannot be read from or written to. 21A.15 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode, the RAM emulation function, and programmer mode are summarized below. 1. Use the specified voltages and timing for programming and erasing. Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas Technology microcomputer device type with 128-kbyte on-chip flash memory. Only use the specified socket adapter. Failure to observe these points may result in damage to the device. 2. Powering on and off (see figures 21A-26 to 21A-28) Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low before turning off VCC. When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. 3. FWE application/disconnection (see figures 21A-26 to 21A-28) FWE application should be carried out when MCU operation is in a stable condition. If MCU operation is not stable, fix the FWE pin low and set the protection state. The following points must be observed concerning FWE application and disconnection to prevent unintentional programming or erasing of flash memory: * Apply FWE when the VCC voltage has stabilized within its rated voltage range. Apply FWE when oscillation has stabilized (after the elapse of the oscillation settling time). * In boot mode, apply and disconnect FWE during a reset. * In user program mode, FWE can be switched between high and low level regardless of a reset state. FWE input can also be switched during execution of a program in flash memory. * Do not apply FWE if program runaway has occurred. Rev. 6.00 Feb 22, 2005 page 791 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) * Disconnect FWE only when the SWE, ESU, PSU, EV, PV, P, and E bits in FLMCR1 are cleared. Make sure that the SWE, ESU, PSU, EV, PV, P, and E bits are not set by mistake when applying or disconnecting FWE. 4. Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. 5. Use the recommended algorithm when programming and erasing flash memory. The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. 6. Do not set or clear the SWE bit during execution of a program in flash memory. Do not set or clear the SWE bit during execution of a program in flash memory. Wait for at least 100 s after clearing the SWE bit before executing a program or reading data in flash memory. When the SWE bit is set, data in flash memory can be rewritten, but when SWE = 1, flash memory can only be read in program-verify or erase-verify mode. Access flash memory only for verify operations (verification during programming/erasing). Do not clear the SWE bit during programming, erasing, or verifying. Similarly, when using the RAM emulation function while a high level is being input to the FWE pin, the SWE bit must be cleared before executing a program or reading data in flash memory. However, the RAM area overlapping flash memory space can be read and written to regardless of whether the SWE bit is set or cleared. 7. Do not use interrupts while flash memory is being programmed or erased. All interrupt requests, including NMI, should be disabled during FWE application to give priority to program/erase operations. 8. Do not perform additional programming. Erase the memory before reprogramming. In on-board programming, perform only one programming operation on a 128-byte programming unit block. In programmer mode, also, perform only one programming operation on a 128-byte programming unit block. Further programming must only be executed after this programming unit block has been erased. Rev. 6.00 Feb 22, 2005 page 792 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) 9. Before programming, check that the chip is correctly mounted in the PROM programmer. Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. 10. Do not touch the socket adapter or chip during programming. Touching either of these can cause contact faults and write errors. Programming/ erasing possible Wait time: x Wait time: 100 s tOSC1 VCC tMDS*3 Min. 0 s Min. 0 s FWE MD2 to MD0*1 tMDS*3 RES SWE set SWE bit SWE cleared Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD2-MD0) must be fixed until poweroff by pulling the pins up or down. 2. See section 24.1.7, Flash Memory Characteristics. 3. Mode programming setup time tMDS (min.) = 200 ns Figure 21A-26 Power-On/Off Timing (Boot Mode) Rev. 6.00 Feb 22, 2005 page 793 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) Wait time: x Programming/ erasing possible Wait time: 100 s tOSC1 VCC Min. 0 s FWE MD2 to MD0*1 tMDS*3 RES SWE set SWE bit SWE cleared Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD2-MD0) must be fixed until poweroff by pulling the pins up or down. 2. See section 24.1.7, Flash Memory Characteristics. 3. Mode programming setup time tMDS (min.) = 200 ns Figure 21A-27 Power-On/Off Timing (User Program Mode) Rev. 6.00 Feb 22, 2005 page 794 of 1484 REJ09B0103-0600 Section 21A ROM (H8S/2636 Group) Wait time: 100 s Wait time: x Programming/ erasing possible Wait time: 100 s Wait time: x Programming/ erasing possible Wait time: 100 s Wait time: x Programming/ erasing possible tOSC1 VCC Min. 0s FWE tMDS tMDS*2 MD2 to MD0 tMDS tRESW RES SWE set SWE cleared SWE bit Mode change*1 Boot mode Mode User change*1 mode User program mode User mode User program mode Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*3 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried out by means of RES input. The state of ports with multiplexed address functions and bus control output pins (AS, RD, WR) will change during this switchover interval (the interval during which the RES pin input is low), and therefore these pins should not be used as output signals during this time. 2. When making a transition from boot mode to another mode, a mode programming setup time, tMDS (min.), of 200 ns is necessary with respect to the RES clearance timing. 3. See section 24.1.7, Flash Memory Characteristics. Figure 21A-28 Mode Transition Timing (Example: Boot Mode User Mode User Program Mode) Rev. 6.00 Feb 22, 2005 page 795 of 1484 REJ09B0103-0600 Programming/ erasing possible Wait time: x Wait time: 100 s Section 21A ROM (H8S/2636 Group) 21A.16 Note on Switching from F-ZTAT Version to Mask ROM Version The mask ROM version does not have the internal registers for flash memory control that are provided in the F-ZTAT version. Table 21A-27 lists the registers that are present in the F-ZTAT version but not in the mask ROM version. If a register listed in table 21A-27 is read in the mask ROM version, an undefined value will be returned. Therefore, if application software developed on the F-ZTAT version is switched to a mask ROM version product, it must be modified to ensure that the registers in table 21A-27 have no effect. Table 21A-27 Registers Present in F-ZTAT Version but Absent in Mask ROM Version Register Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Abbreviation FLMCR1 FLMCR2 EBR1 EBR2 RAMER Address H'FFA8 H'FFA9 H'FFAA H'FFAB H'FEDB Rev. 6.00 Feb 22, 2005 page 796 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.1 Overview The H8S/2638 and H8S/2639 have 256 kbytes of on-chip flash memory, or 256 kbytes or 384 kbytes of on-chip mask ROM. The H8S/2630 has 384 kbytes of on-chip flash memory, or 384 kbytes of on-chip mask ROM. The ROM is connected to the bus master via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching is thus speeded up, and processing speed increased. The on-chip ROM is enabled and disabled by setting the mode pins (MD2 to MD0). The flash memory version can be erased and programmed on-board, as well as with a specialpurpose PROM programmer. 21B.1.1 Block Diagram Figure 21B-1 shows a block diagram of 256-kbyte and 384-kbyte ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000002 H'000001 H'000003 H'03FFFE (H'05FFFE)* H'03FFFF (H'05FFFF)* Note: * ROM addresses for the H8S/2638 and H8S/2639 extend from H'000000 to H'03FFFF (256 kbytes), and for the H8S/2630 from H'000000 to H'05FFFF (384 kbytes). Figure 21B-1 Block Diagram of ROM 256 kbytes (384 kbytes)* Rev. 6.00 Feb 22, 2005 page 797 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.1.2 Register Configuration The H8S/2638 and H8S/2639 operating mode is controlled by the mode pins and the MDCR register. The register configuration is shown in table 21B-1. Table 21B-1 Register Configuration Register Name Mode control register Abbreviation MDCR R/W R/W Initial Value Undefined Address* H'FDE7 Note: * Lower 16 bits of the address. 21B.2 Register Descriptions 21B.2.1 Mode Control Register (MDCR) Bit: Initial value: R/W: 7 -- 1 R/W 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 MDS2 --* R 1 MDS1 --* R 0 MDS0 --* R Note: * Determined by pins MD2 to MD0. MDCR is an 8-bit register used to monitor the current H8S/2638 Group, H8S/2639 Group, and H8S/2630 Group operating mode. Bit 7--Reserved: Only 1 should be written to these bits. Bits 6 to 3--Reserved: These bits are always read as 0 and cannot be modified. Bits 2 to 0--Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD2 to MD0. MDS2 to MDS0 are read-only bits, and cannot be modified. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a reset. 21B.3 Operation The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. Word data must start at an even address. Rev. 6.00 Feb 22, 2005 page 798 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) The on-chip ROM is enabled and disabled by setting the mode pins (MD2, MD1, and MD0). These settings are shown in table 21B-2. Table 21B-2 Operating Modes and ROM (F-ZTAT Version) Mode Pins Operating Mode Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode 1 1 0 1 -- FWE 0 MD2 0 MD1 0 MD0 0 1 0 1 0 1 0 Enabled (256 kbytes/ 384 kbytes)*3 Enabled (256 kbytes/ 384 kbytes)*3 -- Enabled (256 kbytes/ 384 kbytes)*3 Enabled (256 kbytes/ 384 kbytes)*3 -- Enabled (256 kbytes/ 384 kbytes)*3 Enabled (256 kbytes/ 3 384 kbytes)* Disabled On-Chip ROM -- Mode 7 1 Mode 8 Mode 9 Mode 10 -- Boot mode (advanced expanded mode with on-chip ROM enabled)*1 Boot mode (advanced single-chip 2 mode)* -- User program mode (advanced expanded mode with on-chip ROM enabled)*1 User program mode (advanced single2 chip mode)* 1 0 0 1 0 1 0 Mode 11 1 Mode 12 Mode 13 Mode 14 1 0 1 0 1 0 Mode 15 1 Notes: 1. Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced expanded mode with on-chip ROM enabled. 2. Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced single-chip mode. Rev. 6.00 Feb 22, 2005 page 799 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 3. The H8S/2638 and H8S/2639 have 256 kbytes of on-chip ROM. The H8S/2630 has 384 kbytes of on-chip ROM. Table 21B-3 Operating Modes and ROM (Mask ROM Version) Mode Pins Operating Mode Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode 1 1 0 1 -- MD2 0 MD1 0 MD0 0 1 0 1 0 1 0 Enabled (256 kbytes/ 384 kbytes)* Enabled (256 kbytes/ 384 kbytes)* Disabled On-Chip ROM -- Mode 7 1 Note: * The H8S/2638 and H8S/2639 have 256 kbytes of on-chip ROM. The H8S/2630 has 384 kbytes of on-chip ROM. Rev. 6.00 Feb 22, 2005 page 800 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.4 Flash Memory Overview 21B.4.1 Features The H8S/2638 and H8S/2639 have 256 kbytes of on-chip flash memory, or 256 kbytes of on-chip mask ROM. The H8S/2630 has 384 kbytes of on-chip flash memory, or 384 kbytes of on-chip mask ROM. The features of the flash memory are summarized below. * Four flash memory operating modes Program mode Erase mode Program-verify mode Erase-verify mode * Programming/erase methods The flash memory is programmed 128 bytes at a time. Block erase (in single-block units) can be performed. To erase the entire flash memory, each block must be erased in turn. Block erasing can be performed as required on 4 kbytes, 32 kbytes, and 64 kbytes blocks. * Programming/erase times The flash memory programming time is 10 ms (typ.) for simultaneous 128-byte programming, equivalent to 80 s (typ.) per byte, and the erase time is 100 ms (typ.). * Reprogramming capability The flash memory can be reprogrammed up to 100 times. * On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: Boot mode User program mode * Automatic bit rate adjustment With data transfer in boot mode, the LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. * Flash memory emulation in RAM Flash memory programming can be emulated in real time by overlapping a part of RAM onto flash memory. * Protect modes There are three protect modes, hardware, software, and error protection, which allow protected status to be designated for flash memory program/erase/verify operations. Rev. 6.00 Feb 22, 2005 page 801 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) * Programmer mode Flash memory can be programmed/erased in programmer mode, using a PROM programmer, as well as in on-board programming mode. 21B.4.2 Block Diagram Internal address bus Internal data bus (16 bits) Module bus FLMCR1 FLMCR2 EBR1 EBR2 RAMER FLPWCR Flash memory (256 kbytes/ 384 kbytes) Bus interface/controller Operating mode FWE pin Mode pin Legend: FLMCR1: FLMCR2: EBR1: EBR2: RAMER: FLPWCR: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Flash memory power control register Figure 21B-2 Block Diagram of Flash Memory Rev. 6.00 Feb 22, 2005 page 802 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.4.3 Mode Transitions When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the microcomputer enters an operating mode as shown in figure 21B-3. In user mode, flash memory can be read but not programmed or erased. The boot, user program and programmer modes are provided as modes to write and erase the flash memory. MD1 = 1, MD2 = 1, FWE = 0 User mode (on-chip ROM enabled) *1 RES = 0 Reset state RES = 0 MD1 = 1, MD2 = 1, FWE = 1 RES = 0 MD2 = 0, MD1 = 1, FWE = 1 RES = 0 Programmer mode *2 FWE = 1 FWE = 0 *1 User program mode Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. RAM emulation possible 2. MD0 = 0, MD1 = 0, MD2 = 0, P14 = 0, P16 = 0, PF0 = 1 Figure 21B-3 Flash Memory State Transitions Rev. 6.00 Feb 22, 2005 page 803 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.4.4 On-Board Programming Modes Boot Mode 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host Host Programming control program New application program New application program Chip Boot program Flash memory RAM SCI Chip Boot program Flash memory RAM Boot program area SCI Application program (old version) Application program (old version) Programming control program 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, total flash memory erasure is performed, without regard to blocks. Host 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host New application program Chip Boot program Flash memory RAM Boot program area Flash memory preprogramming erase Programming control program Chip SCI Boot program Flash memory RAM Boot program area New application program Programming control program SCI Program execution state Rev. 6.00 Feb 22, 2005 page 804 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) User Program Mode 1. Initial state The FWE assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory. Host Programming/ erase control program New application program New application program 2. Programming/erase control program transfer When user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to RAM. Host Chip Boot program Flash memory FWE assessment program Chip SCI RAM Boot program Flash memory FWE assessment program SCI RAM Transfer program Transfer program Programming/ erase control program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. Host 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host New application program Chip Boot program Flash memory FWE assessment program Chip SCI RAM Boot program Flash memory FWE assessment program Transfer program Programming/ erase control program Programming/ erase control program SCI RAM Transfer program Flash memory erase New application program Program execution state Rev. 6.00 Feb 22, 2005 page 805 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.4.5 Flash Memory Emulation in RAM Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. SCI Flash memory Emulation block RAM Overlap RAM (emulation is performed on data written in RAM) Application program Execution state Figure 21B-4 Reading Overlap RAM Data in User Mode or User Program Mode When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten. Rev. 6.00 Feb 22, 2005 page 806 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) SCI Flash memory Programming data RAM Application program Overlap RAM (programming data) Programming control program execution state Figure 21B-5 Writing Overlap RAM Data in User Program Mode 21B.4.6 Differences between Boot Mode and User Program Mode Table 21B-4 Differences between Boot Mode and User Program Mode Boot Mode Total erase Block erase Programming control program* Yes No Program/program-verify User Program Mode Yes Yes Erase/erase-verify Program/program-verify Emulation Note: * To be provided by the user, in accordance with the recommended algorithm. Rev. 6.00 Feb 22, 2005 page 807 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.4.7 Block Configuration The H8S/2638 and H8S/2639 have 256 kbytes of flash memory, which is divided into three 64kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. The H8S/2630 has 384 kbytes of flash memory, which is divided into five 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. H8S/2638, H8S/2639 Address H'00000 4 kbytes 8 32 kbytes H8S/2630 4 kbytes 8 32 kbytes 64 kbytes 256 kbytes 64 kbytes 384 kbytes 64 kbytes 64 kbytes 64 kbytes Address H'3FFFF 64 kbytes 64 kbytes 64 kbytes Address H'5FFFF Figure 21B-6 Flash Memory Block Configuration Rev. 6.00 Feb 22, 2005 page 808 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.5 Pin Configuration The flash memory is controlled by means of the pins shown in table 21B-5. Table 21B-5 Pin Configuration Pin Name Reset Flash write enable Mode 2 Mode 1 Mode 0 Port F0 Port 16 Port 14 Transmit data Receive data Abbreviation I/O Input Input Input Input Input Input Input Input Output Input Function Reset Flash memory program/erase protection by hardware Sets MCU operating mode Sets MCU operating mode Sets MCU operating mode Sets MCU operating mode in programmer mode Sets MCU operating mode in programmer mode Sets MCU operating mode in programmer mode Serial transmit data output Serial receive data input MD2 MD1 MD0 PF0 P16 P14 TxD1 RxD1 SER FWE Rev. 6.00 Feb 22, 2005 page 809 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.6 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 21B-6. Table 21B-6 Register Configuration Register Name Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Abbreviation FLMCR1*4 FLMCR2*4 EBR1*4 EBR2*4 RAMER *4 R/W R/W R R/W R/W R/W R/W Initial Value H'00*2 H'00 H'00*3 H'00*3 H'00 H'00*3 Address*1 H'FFA8 H'FFA9 H'FFAA H'FFAB H'FEDB H'FFAC Flash memory power control register FLPWCR*4 Notes: 1. Lower 16 bits of the address. 2. When a high level is input to the FWE pin, the initial value is H'80. 3. When a low level is input to the FWE pin, or if a high level is input and the SWE1 bit in FLMCR1 is not set, these registers are initialized to H'00. 4. FLMCR1, FLMCR2, EBR1, and EBR2, RAMER, and FLPWCR are 8-bit registers. Use byte access on these registers. Rev. 6.00 Feb 22, 2005 page 810 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.7 Register Descriptions 21B.7.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for on-chip flash memory is entered by setting SWE bit to 1 when FWE = 1, then setting the PV or EV bit. Program mode for on-chip flash memory is entered by setting SWE bit to 1 when FWE = 1, then setting the PSU bit, and finally setting the P bit. Erase mode for onchip flash memory is entered by setting SWE bit to 1 when FWE = 1, then setting the ESU bit, and finally setting the E bit. FLMCR1 is initialized by a reset, and in hardware standby mode and software standby mode. Its initial value is H'80 when a high level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes are enabled only in the following cases: Writes to bit SWE of FLMCR1 enabled when FWE = 1, to bits ESU, PSU, EV, and PV when FWE = 1 and SWE = 1, to bit E when FWE = 1, SWE = 1 and ESU = 1, and to bit P when FWE = 1, SWE = 1, and PSU = 1. Bit: Initial value: R/W: 7 FWE --* R 6 SWE 0 R/W 5 ESU 0 R/W 4 PSU 0 R/W 3 EV 0 R/W 2 PV 0 R/W 1 E 0 R/W 0 P 0 R/W Note: * Determined by the state of the FWE pin. Bit 7--Flash Write Enable Bit (FWE): Sets hardware protection against flash memory programming/erasing. Bit 7 FWE 0 1 Description When a low level is input to the FWE pin (hardware-protected state) When a high level is input to the FWE pin Rev. 6.00 Feb 22, 2005 page 811 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) Bit 6--Software Write Enable Bit (SWE): This bit selects write and erase valid/invalid of the flash memory. Set it when setting bits 5 to 0, bits 7 to 0 of EBR1, and bits 5 to 0* of EBR2. Bit 6 SWE 0 1 Description Writes disabled Writes enabled [Setting condition] * When FWE = 1 Note: * Bits 3 to 0 of EBR2 for the H8S/2638 and H8S/2639. (Initial value) Bit 5--Erase Setup Bit (ESU): Prepares for a transition to erase mode. Set this bit to 1 before setting the E bit in FLMCR1 to 1. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time. Bit 5 ESU 0 1 Description Erase setup cleared Erase setup [Setting condition] * When FWE = 1 and SWE = 1 (Initial value) Bit 4--Program Setup Bit (PSU): Prepares for a transition to program mode. Set this bit to 1 before setting the P bit in FLMCR1 to 1. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time. Bit 4 PSU 0 1 Description Program setup cleared Program setup [Setting condition] * When FWE = 1 and SWE = 1 (Initial value) Rev. 6.00 Feb 22, 2005 page 812 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) Bit 3--Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3 EV 0 1 Description Erase-verify mode cleared Transition to erase-verify mode [Setting condition] * When FWE = 1 and SWE = 1 (Initial value) Bit 2--Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time. Bit 2 PV 0 1 Description Program-verify mode cleared Transition to program-verify mode [Setting condition] * When FWE = 1 and SWE = 1 (Initial value) Bit 1--Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time. Bit 1 E 0 1 Description Erase mode cleared Transition to erase mode [Setting condition] * When FWE = 1, SWE = 1, and ESU = 1 (Initial value) Bit 0--Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU, ESU, EV, PV, or E bit at the same time. Rev. 6.00 Feb 22, 2005 page 813 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) Bit 0 P 0 1 Description Program mode cleared Transition to program mode [Setting condition] * When FWE = 1, SWE = 1, and PSU = 1 (Initial value) 21B.7.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is an 8-bit register used for flash memory operating mode control. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00. Bit: Initial value: R/W: 7 FLER 0 R 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 -- 0 -- 0 -- 0 -- Note: FLMCR2 is a read-only register, and should not be written to. Bit 7--Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state. Bit 7 FLER 0 Description Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] * 1 Reset or hardware standby mode An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] * See section 21B.10.3, Error Protection (Initial value) Bits 6 to 0--Reserved: These bits always read 0. Rev. 6.00 Feb 22, 2005 page 814 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.7.3 Erase Block Register 1 (EBR1) EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be automatically cleared to 0. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory erase block configuration is shown in table 21B-7. Bit: Initial value: R/W: 7 EB7 0 R/W 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W 3 EB3 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W 0 EB0 0 R/W 21B.7.4 Erase Block Register 2 (EBR2) EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin. Bit 0 will be initialized to 0 if bit SWE of FLMCR1 is not set, even though a high level is input to pin FWE. When a bit in EBR2 is set to 1, the corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be automatically cleared to 0. On the H8S/2638 and H8S/2639 bits 7 to 4 are reserved, and on the H8S/2630 bits 7 and 6 are reserved. Only 0 may be written to these reserved bits. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory erase block configuration is shown in table 21B-7. Bit: Initial value: R/W: 7 -- 0 R/W 6 -- 0 R/W 5 EB13* 0 R/W 4 EB12* 0 R/W 3 EB11 0 R/W 2 EB10 0 R/W 1 EB9 0 R/W 0 EB8 0 R/W Note: * Valid on the H8S/2630. On the H8S/2638 and H8S/2639 these bits are reserved and only 0 may be written to them. Rev. 6.00 Feb 22, 2005 page 815 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) Table 21B-7 Flash Memory Erase Blocks Block (Size) EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) EB8 (32 kbytes) EB9 (64 kbytes) EB10 (64 kbytes) EB11 (64 kbytes) EB12 (64 kbytes)* EB13 (64 kbytes))* Addresses H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF H'008000 to H'00FFFF H'010000 to H'01FFFF H'020000 to H'02FFFF H'030000 to H'03FFFF H'040000 to H'04FFFF H'050000 to H'05FFFF Note: * This function is not available in the H8S/2638 and H8S/2639. 21B.7.5 RAM Emulation Register (RAMER) RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. RAMER settings should be made in user mode or user program mode. Flash memory area divisions are shown in table 21B-8. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bit: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 -- 0 R/W 4 -- 0 R/W 3 RAMS 0 R/W 2 RAM2 0 R/W 1 RAM1 0 R/W 0 RAM0 0 R/W Rev. 6.00 Feb 22, 2005 page 816 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) Bits 7 and 6--Reserved: These bits always read 0. Bits 5 and 4--Reserved: Only 0 may be written to these bits. Bit 3--RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory block are program/erase-protected. Bit 3 RAMS 0 1 Description Emulation not selected Program/erase-protection of all flash memory blocks is disabled Emulation selected Program/erase-protection of all flash memory blocks is enabled (Initial value) Bits 2 to 0--Flash Memory Area Selection: These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM. (See table 21B-8.) Table 21B-8 Flash Memory Area Divisions Addresses H'FFD000 to H'FFDFFF H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF Block Name RAM area 4 kbytes EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) RAMS 0 1 1 1 1 1 1 1 1 RAM1 * 0 0 0 0 1 1 1 1 RAM1 * 0 0 1 1 0 0 1 1 RAM0 * 0 1 0 1 0 1 0 1 *: Don't care Rev. 6.00 Feb 22, 2005 page 817 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.7.6 Flash Memory Power Control Register (FLPWCR) Bit: Initial value: R/W: 7 PDWND 0 R/W 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode*. Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are not available in versions other than the U-mask and W-mask versions. Bit 7--Power-Down Disable (PDWND): The subactive mode is not available in versions other than the U-mask and W-mask versions. Only 0 should be written to this bit in the case of versions other than the U-mask and W-mask versions. See section 21.B.14, Flash Memory and Power-Down States, for more information. Bit 7 PDWND 0 1 Description Transition to flash memory power-down mode enabled Transition to flash memory power-down mode disabled (Initial value) Bits 6 to 0--Reserved: These bits always read 0. Rev. 6.00 Feb 22, 2005 page 818 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.8 On-Board Programming Modes When pins are set to on-board programming mode and a reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 21B-9. For a diagram of the transitions to the various flash memory modes, see figure 21B-3. Table 21B-9 Setting On-Board Programming Modes Mode Boot mode User program mode Expanded mode Single-chip mode Expanded mode Single-chip mode 1 FWE 1 MD2 0 0 1 1 MD1 1 1 1 1 MD0 0 1 0 1 Rev. 6.00 Feb 22, 2005 page 819 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.8.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The SCI channel to be used is set to asynchronous mode. When a reset-start is executed after the H8S/2638', H8S/2639', and H8S/2630' pins have been set to boot mode, the boot program built into the H8S/2638, H8S/2639, and H8S/2630 are started and the programming control program prepared in the host is serially transmitted to the H8S/2638, H8S/2639, and H8S/2630 via the SCI. In the H8S/2638, H8S/2639, and H8S/2630, the programming control program received via the SCI is written into the programming control program area in on-chip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 21B-7, and the boot mode execution procedure in figure 21B-8. LSI Flash memory Host Write data reception Verify data transmission RxD1 SCI1 TxD1 On-chip RAM Figure 21B-7 System Configuration in Boot Mode Rev. 6.00 Feb 22, 2005 page 820 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate Chip measures low period of H'00 data transmitted by host Chip calculates bit rate and sets value in bit rate register After bit rate adjustment, chip transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, LSI transmits one H'AA data byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte Chip transmits received number of bytes to host as verify data (echo-back) n=1 Host transmits programming control program sequentially in byte units Chip transmits received programming control program to host as verify data (echo-back) Transfer received programming control program to on-chip RAM No Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, chip transmits one H'AA data byte to host Execute programming control program transferred to on-chip RAM n+1n n = N? Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. Figure 21B-8 Boot Mode Execution Procedure Rev. 6.00 Feb 22, 2005 page 821 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) Automatic SCI Bit Rate Adjustment Start bit Stop bit D0 D1 D2 D3 D4 D5 D6 D7 Low period (9 bits) measured (H'00 data) High period (1 or more bits) When boot mode is initiated, the LSI measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The LSI calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the LSI. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host's transmission bit rate and the LSI's system clock frequency, there will be a discrepancy between the bit rates of the host and the LSI. Set the host transfer bit rate at 4,800, 9,600 or 19,200 bps to operate the SCI properly. Table 21B-10 shows host transfer bit rates and system clock frequencies for which automatic adjustment of the LSI bit rate is possible. The boot program should be executed within this system clock range. Table 21B-10 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate Is Possible Host Bit Rate 4,800 bps 9,600 bps 19,200 bps System Clock Frequency for which Automatic Adjustment of LSI Bit Rate Is Possible 4 to 20 MHz 8 to 20 MHz 16 to 20 MHz Note: The system clock frequency used in boot mode is generated by an external crystal oscillator element. PLL frequency multiplication is not used. Rev. 6.00 Feb 22, 2005 page 822 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an area used by the boot program and an area to which the programming control program is transferred via the SCI, as shown in figure 21B-9. The boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host. H'FFC000 Programming control program area (8 kbytes) H'FFDFFF H'FFE000 Boot program area (4 kbytes) H'FFEFBF Note: The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note also that the boot program remains in this area of the on-chip RAM even after control branches to the programming control program. Figure 21B-9 RAM Areas in Boot Mode Notes on Use of Boot Mode: * When the chip comes out of reset in boot mode, it measures the low-level period of the input at the SCI's RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes approximately 100 states before the chip is ready to measure the low-level period of the RxD1 pin. * In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. * Interrupts cannot be used while the flash memory is being programmed or erased. * The RxD1 and TxD1 pins should be pulled up on the board. * Before branching to the programming control program (RAM area H'FFC000), the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE Rev. 6.00 Feb 22, 2005 page 823 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD1, goes to the high-level output state (P33DDR = 1, P33DR = 1). The contents of the CPU's internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. The initial values of other on-chip registers are not changed. * Boot mode can be entered by making the pin settings shown in table 21B-9 and executing a reset-start. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the FWE pin and mode pins, and executing reset release*1. Boot mode can also be cleared by a WDT overflow reset. Do not change the mode pin input levels in boot mode, and do not drive the FWE pin low while the boot program is being executed or while flash memory is being programmed or erased*2. * If the mode pin input levels are changed (for example, from low to high) during a reset, the , ) state of ports with multiplexed address functions and bus control output pins (AS, will change according to the change in the microcomputer's operating mode*3. Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS = 4 states) with respect to the reset release timing. 2. For precautions on applying and disconnecting FWE, see section 21B.15, Flash Memory Programming and Erasing Precautions. 3. See Appendix D, Pin States. 21B.8.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of FWE control and supply of programming data, and storing a program/erase control program in part of the program area as necessary. Rev. 6.00 Feb 22, 2005 page 824 of 1484 REJ09B0103-0600 RWH DR Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) To select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7), and apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 6 and 7. The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip RAM or external memory. If the program is to be located in external memory, the instruction for writing to flash memory, and the following instruction, should be placed in on-chip RAM. Figure 21B-10 shows the procedure for executing the program/erase control program when transferred to on-chip RAM. Write the FWE assessment program and transfer program (and the program/erase control program if necessary) beforehand MD2, MD1, MD0 = 110, 111 Reset-start Transfer program/erase control program to RAM Branch to program/erase control program in RAM area FWE = high* Execute program/erase control program (flash memory rewriting) Clear FWE* Branch to flash memory application program Notes: Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only when the flash memory is programmed or erased. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. * For further information on FWE application and disconnection, see section 21B.15, Flash Memory Programming and Erasing Precautions. Figure 21B-10 User Program Mode Execution Procedure Rev. 6.00 Feb 22, 2005 page 825 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.9 Programming/Erasing Flash Memory A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes are made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1 for on-chip flash memory. The flash memory cannot be read while it is being written or erased. The flash memory cannot be read while being programmed or erased. Therefore, the program (user program) that controls flash memory programming/erasing should be located and executed in on-chip RAM or external memory. If the program is to be located in external memory, the instruction for writing to flash memory, and the following instruction, should be placed in on-chip RAM. Also ensure that the DTC is not activated before or after execution of the flash memory write instruction. In the following operation descriptions, wait times after setting or clearing individual bits in FLMCR1 are given as parameters; for details of the wait times, see section 24.2.7 and 24.3.7, Flash Memory Characteristics. Notes: 1. Operation is not guaranteed if bits SWE, ESU, PSU, EV, PV, E, and P of FLMCR1 are set/reset by a program in flash memory in the corresponding address areas. 2. When programming or erasing, set FWE to 1 (programming/erasing will not be executed if FWE = 0). 3. Programming should be performed in the erased state. Do not perform additional programming on previously programmed addresses. Rev. 6.00 Feb 22, 2005 page 826 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) *3 E=1 Erase setup state E=0 Normal mode ESU = 1 ESU = 0 Erase-verify mode Erase mode *1 FWE = 1 FWE = 0 *2 EV = 1 EV = 0 PSU = 1 PSU = 0 On-board SWE = 1 Software programming mode programming Software programming enable disable state SWE = 0 state *4 Program setup state P=1 Program mode P=0 PV = 0 PV = 1 Program-verify mode Notes: In order to perform a normal read of flash memory, SWE must be cleared to 0. Also note that verify-reads can be performed during the programming/erasing process. 1. : Normal mode : On-board programming mode 2. Do not make a state transition by setting or clearing multiple bits simultaneously. 3. After a transition from erase mode to the erase setup state, do not enter erase mode without passing through the software programming enable state. 4. After a transition from program mode to the program setup state, do not enter program mode without passing through the software programming enable state. Figure 21B-11 FLMCR1 Bit Settings and State Transitions Rev. 6.00 Feb 22, 2005 page 827 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.9.1 Program Mode When writing data or programs to flash memory, the program/program-verify flowchart shown in figure 21B-12 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a time. The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N) are shown in table 24-22 in section 24.2.7, and in table 24-34 in section 24.3.7, and in table 24-46 in section 24.4.7, Flash Memory Characteristics. Following the elapse of (tsswe) s or more after the SWE bit is set to 1 in FLMCR1, 128-byte data is written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00 and H'80, 128 consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. Set a value greater than (tspsu + tsp + tcp + tcpsu) s as the WDT overflow period. Preparation for entering program mode (program setup) is performed next by setting the PSU bit in FLMCR1. The operating mode is then switched to program mode by setting the P bit in FLMCR1 after the elapse of at least (tspsu) s. The time during which the P bit is set is the flash memory programming time. Make a program setting so that the time for one programming operation is within the range of (tsp) s. The wait time after P bit setting must be changed according to the degree of progress through the programming operation. For details see "Notes on Program/Program-Verify Procedure." Rev. 6.00 Feb 22, 2005 page 828 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.9.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of the given programming time, clear the P bit in FLMCR1, then wait for at least (tcp) s before clearing the PSU bit to exit program mode. After exiting program mode, the watchdog timer setting is also cleared. The operating mode is then switched to program-verify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (tspv) s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (tspvr) s after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 21B-12) and transferred to RAM. After verification of 128 bytes of data has been completed, exit program-verify mode, wait for at least (tcpv) s, then clear the SWE bit in FLMCR1. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. The maximum number of repetitions of the program/program-verify sequence is indicated by the maximum programming count (N). Leave a wait time of at least (tcswe) s after clearing SWE. Notes on Program/Program-Verify Procedure 1. In order to perform 128-byte-unit programming, the lower 8 bits of the write start address must be H'00 or H'80. 2. When performing continuous writing of 128-byte data to flash memory, byte-unit transfer should be used. 128-byte data transfer is necessary even when writing fewer than 128 bytes of data. Write H'FF data to the extra addresses. 3. Verify data is read in word units. 4. The write pulse is applied and a flash memory write executed while the P bit in FLMCR1 is set. In the chip, write pulses should be applied as follows in the program/program-verify procedure to prevent voltage stress on the device and loss of write data reliability. a. After write pulse application, perform a verify-read in program-verify mode and apply a write pulse again for any bits read as 1 (reprogramming processing). When all the 0-write bits in the 128-byte write data are read as 0 in the verify-read operation, the program/program-verify procedure is completed. In the chip, the number of loops in reprogramming processing is guaranteed not to exceed the maximum value of the maximum programming count (N). Rev. 6.00 Feb 22, 2005 page 829 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) b. After write pulse application, a verify-read is performed in program-verify mode, and programming is judged to have been completed for bits read as 0. The following processing is necessary for programmed bits. When programming is completed at an early stage in the program/program-verify procedure: If programming is completed in the 1st to 6th reprogramming processing loop, additional programming should be performed on the relevant bits. Additional programming should only be performed on bits which first return 0 in a verify-read in certain reprogramming processing. When programming is completed at a late stage in the program/program-verify procedure: If programming is completed in the 7th or later reprogramming processing loop, additional programming is not necessary for the relevant bits. c. If programming of other bits is incomplete in the 128 bytes, reprogramming processing should be executed. If a bit for which programming has been judged to be completed is read as 1 in a subsequent verify-read, a write pulse should again be applied to that bit. 5. The period for which the P bit in FLMCR1 is set (the write pulse width) should be changed according to the degree of progress through the program/program-verify procedure. For detailed wait time specifications, see section 24.2.7, 24.3.7, and 24.4.7, Flash Memory Characteristics. Item Wait time after P bit setting Symbol tsp Item When reprogramming loop count (n) is 1 to 6 When reprogramming loop count (n) is 7 or more In case of additional programming processing* Symbol tsp30 tsp200 tsp10 Note: * Additional programming processing is necessary only when the reprogramming loop count (n) is 1 to 6. 6. The program/program-verify flowchart for the H8S/2638, H8S/2639, and H8S/2630 are shown in figure 21B-12. To cover the points noted above, bits on which reprogramming processing is to be executed, and bits on which additional programming is to be executed, must be determined as shown below. Since reprogram data and additional-programming data vary according to the progress of the programming procedure, it is recommended that the following data storage areas (128 bytes each) be provided in RAM. Rev. 6.00 Feb 22, 2005 page 830 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) Reprogram Data Computation Table Result of Verify-Read after Write Pulse (X) Application (V) Result of Operation 0 1 0 1 1 0 1 1 (D) 0 0 1 1 Comments Programming completed: reprogramming processing not to be executed Programming incomplete: reprogramming processing to be executed Still in erased state: no action Legend: (D): Source data of bits on which programming is executed (X): Source data of bits on which reprogramming is executed Additional-Programming Data Computation Table Result of Verify-Read after Write Pulse (Y) (X') Application (V) Result of Operation 0 0 0 Comments Programming by write pulse application judged to be completed: additional programming processing to be executed Programming by write pulse application incomplete: additional programming processing not to be executed Programming already completed: additional programming processing not to be executed Still in erased state: no action 0 1 1 1 1 0 1 1 1 Legend: (Y): Data of bits on which additional programming is executed (X'): Data of bits on which reprogramming is executed in a certain reprogramming loop 7. It is necessary to execute additional programming processing during the course of the chip program/program-verify procedure. However, once 128-byte-unit programming is finished, additional programming should not be carried out on the same address area. When executing reprogramming, an erase must be executed first. Note that normal operation of reads, etc., is not guaranteed if additional programming is performed on addresses for which a program/program-verify operation has finished. Rev. 6.00 Feb 22, 2005 page 831 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) Write pulse application subroutine Start of programming START Set SWE bit in FLMCR1 Wait (tsswe) s Store 128-byte program data in program data area and reprogram data area Sub-Routine Write Pulse WDT enable Set PSU bit in FLMCR1 Wait (tspsu) s Set P bit in FLMCR1 Wait (tsp) s Clear P bit in FLMCR1 Wait (tcp) s Clear PSU bit in FLMCR1 Wait (tcpsu) s Disable WDT Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. *7 *4 *7 Start of programming n=1 m=0 *5*7 End of programming Write 128-byte data in RAM reprogram data area consecutively to flash memory *1 Sub-Routine-Call *7 Write pulse See Note 6 for pulse width Set PV bit in FLMCR1 *7 Wait (tspv) s H'FF dummy write to verify address *7 Wait (tspvr) s End Sub Increment address Note: 6 Write Pulse Width Number of Writes n Write Time (tsp) sec Write data = verify data? Read verify data *7 *2 No m=1 No nn+1 1 2 3 4 5 6 7 8 9 10 11 12 13 30 30 30 30 30 30 200 200 200 200 200 200 200 Yes 6n? Yes Additional-programming data computation Transfer additional-programming data to additional-programming data area Reprogram data computation *4 *3 *4 Transfer reprogram data to reprogram data area 128-byte data verification completed? No 998 999 1000 200 200 200 Yes Clear PV bit in FLMCR1 Reprogram Wait (tcpv) s 6 n? No Note: Use a 10 s write pulse for additional programming. *7 RAM Program data storage area (128 bytes) Yes Successively write 128-byte data from additional1 programming data area in RAM to flash memory * Sub-Routine-Call Write Pulse (Additional programming) Reprogram data storage area (128 bytes) m=0? Yes Clear SWE bit in FLMCR1 Wait (tcswe) s End of programming No n (N)? *7 No Additional-programming data storage area (128 bytes) Yes Clear SWE bit in FLMCR1 Wait (tcswe) s Programming failure *7 Notes: 1. 2. 3. 4. 5. 7. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Verify data is read in 16-bit (word) units. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM. The contents of the reprogram data area and additional data area are modified as programming proceeds. A write pulse of 30 s or 200 s is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths. When writing of additional-programming data is executed, a 10 s write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied. The wait times and value of N are shown in section 24.2.7, 24.3.7, and 24.4.7, Flash Memory Characteristics. Reprogram Data Computation Table Original Data Verify Data Reprogram Data Additional-Programming Data Computation Table (X) 1 0 1 1 Still in erased state; no action Comments Programming completed Programming incomplete; reprogram (D) 0 0 1 1 (V) 0 1 0 1 Reprogram Data (X') 0 0 1 1 Verify Data Additional(V) Programming Data (Y) 0 1 0 1 0 1 1 1 Comments Additional programming to be executed Additional programming not to be executed Additional programming not to be executed Additional programming not to be executed Figure 21B-12 Program/Program-Verify Flowchart Rev. 6.00 Feb 22, 2005 page 832 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.9.3 Erase Mode When erasing flash memory, the single-block erase flowchart shown in figure 21B-13 should be followed. The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and the maximum number of erase operations (N) are shown in table 24-10 in section 24.2.7 and 24.3.7, Flash Memory Characteristics. To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in erase block register 1 and 2 (EBR1, EBR2) at least (tsswe) s after setting the SWE bit to 1 in FLMCR1. Next, the watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. Set a value greater than (tse) ms + (tsesu + tce + tcesu) s as the WDT overflow period. Preparation for entering erase mode (erase setup) is performed next by setting the ESU bit in FLMCR1. The operating mode is then switched to erase mode by setting the E bit in FLMCR1 after the elapse of at least (tsesu) s. The time during which the E bit is set is the flash memory erase time. Ensure that the erase time does not exceed (tse) ms. Note: With flash memory erasing, preprogramming (setting all memory data in the memory to be erased to all 0) is not necessary before starting the erase procedure. 21B.9.4 Erase-Verify Mode In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the fixed erase time, clear the E bit in FLMCR1, then wait for at least (tce) s before clearing the ESU bit to exit erase mode. After exiting erase mode, the watchdog timer setting is also cleared. The operating mode is then switched to erase-verify mode by setting the EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (tsev) s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (tsevr) s after the dummy write before performing this read operation. If the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. If the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is indicated by the maximum erase count (N). When verification is completed, exit erase-verify mode, and wait for at least (tcev) s. If erasure has been completed on all the erase blocks, clear the SWE bit in FLMCR1, and leave a wait time of at least (tcswe) s. Rev. 6.00 Feb 22, 2005 page 833 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) If erasing multiple blocks, set a single bit in EBR1/EBR2 for the next block to be erased, and repeat the erase/erase-verify sequence as before. Start *1 Perform erasing in block units. Set SWE bit in FLMCR1 Wait (tsswe) s n=1 Set EBR1 or EBR2 Enable WDT Set ESU bit in FLMCR1 Wait (tsesu) s Set E bit in FLMCR1 Wait (tse) ms Clear E bit in FLMCR1 Wait (tce) s Clear ESU bit in FLMCR1 Wait (tcesu) s Disable WDT Set EV bit in FLMCR1 Wait (tsev) s Set block start address as verify address *5 *5 *5 *3 *4 *5 Start of erase *5 Erase halted *5 nn+1 H'FF dummy write to verify address Wait (tsevr) s Increment address Read verify data Verify data = all 1s? Yes No Last address of block? Yes Clear EV bit in FLMCR1 Wait (tcev) s *5 *5 *2 No Clear EV bit in FLMCR1 Wait (tcev) s *5 *5 n (N)? Clear SWE bit in FLMCR1 Wait (tcswe) s End of erasing *5 No Yes Clear SWE bit in FLMCR1 Wait (tcswe) s Erase failure *5 Notes: 1. 2. 3. 4. 5. Prewriting (setting erase block data to all 0s) is not necessary. Verify data is read in 16-bit (word) units. Make only a single-bit specification in the erase block registers (EBR1 and EBR2). Two or more bits must not be set simultaneously. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn. The wait times and the value of N are shown in section 24.2.7, 24.3.7, and 24.4.7, Flash Memory Characteristics. Figure 21B-13 Erase/Erase-Verify Flowchart Rev. 6.00 Feb 22, 2005 page 834 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.10 Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 21B.10.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase block register 2 (EBR2). The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained in the error-protected state (See table 21B-11). Table 21B-11 Hardware Protection Functions Item FWE pin protection Description * When a low level is input to the FWE pin, FLMCR1, FLMCR2, (except bit FLER) EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. In a reset (including a WDT reset) and in standby mode, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. In a reset via the pin, the reset state is not entered unless the pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the pin low for the pulse width specified in the AC Characteristics section. Program Yes Erase Yes Reset/standby protection * Yes Yes SER SER SER * SER Rev. 6.00 Feb 22, 2005 page 835 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.10.2 Software Protection Software protection can be implemented by setting the SWE bit in FLMCR1, erase block register 1 (EBR1), erase block register 2 (EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P or E bit in flash memory control register 1 (FLMCR1), does not cause a transition to program mode or erase mode (See table 21B-12). Table 21B-12 Software Protection Functions Item SWE bit protection Description * Program Erase Yes Setting bit SWE in FLMCR1 to 0 will place Yes area on-chip flash memory in the program/ erase-protected state (Execute the program in the on-chip RAM, external memory). Erase protection can be set for individual blocks by settings in erase block register 1 (EBR1) and erase block register 2 (EBR2). Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state. Yes Setting the RAMS bit to 1 in the RAM emulation register (RAMER) places all blocks in the program/erase-protected state. -- Block specification protection * Yes * Emulation protection * Yes Rev. 6.00 Feb 22, 2005 page 836 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.10.3 Error Protection In error protection, an error is detected when chip runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the chip malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. FLER bit setting conditions are as follows: 1. When the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) 2. Immediately after exception handling (excluding a reset) during programming/erasing 3. When a SLEEP instruction (including software standby) is executed during programming/erasing 4. When the CPU releases the bus to the DTC Error protection is released only by a reset and in hardware standby mode. Rev. 6.00 Feb 22, 2005 page 837 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) Figure 21B-14 shows the flash memory state transition diagram. Program mode Erase mode RD VF PR ER FLER = 0 RES = 0 or HSTBY = 0 Reset or standby (hardware protection) RD VF PR ER FLER = 0 Error occurrence (software standby) Error occurrence RES = 0 or HSTBY = 0 RES = 0 or HSTBY = 0 FLMCR1, FLMCR2, EBR1, EBR2 initialization state Error protection mode RD VF PR ER FLER = 1 Software standby mode Software standby mode release Error protection mode (software standby) RD VF PR ER FLER = 1 FLMCR1, FLMCR2, (except bit FLER) EBR1, EBR2 initialization state Legend: RD: Memory read possible VF: Verify-read possible PR: Programming possible ER: Erasing possible RD: VF: PR: ER: Memory read not possible Verify-read not possible Programming not possible Erasing not possible Figure 21B-14 Flash Memory State Transitions Rev. 6.00 Feb 22, 2005 page 838 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.11 Flash Memory Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses cannot be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 21B-15 shows an example of emulation of real-time flash memory programming. Start of emulation program Set RAMER Write tuning data to overlap RAM Execute application program No Tuning OK? Yes Clear RAMER Write to flash memory emulation block End of emulation program Figure 21B-15 Flowchart for Flash Memory Emulation in RAM Rev. 6.00 Feb 22, 2005 page 839 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) This area can be accessed from both the RAM area and flash memory area H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 EB1 EB2 EB3 EB4 EB5 EB6 EB7 EB0 H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 H'FFD000 H'FFDFFF On-chip RAM H'FFEFBF H'3FFFF H'5FFFF EB1 EB2 EB3 EB4 EB5 EB6 EB7 EB0 This area can be accessed from both the RAM area and flash memory area Flash memory EB8 to EB11 Flash memory EB8 to EB13 On-chip RAM H'FFD000 H'FFDFFF H'FFEFBF H8S/2638, H8S/2639 H8S/2630 Figure 21B-16 Example of RAM Overlap Operation Example in which Flash Memory Block Area EB0 is Overlapped 1. Set bits RAMS, RAM2 to RAM0 in RAMER to 1, 0, 0, 0, to overlap part of RAM onto the area (EB0) for which real-time programming is required. 2. Real-time programming is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space (EB0). Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of RAM2 to RAM0 (emulation protection). In this state, setting the P or E bit in flash memory control register 1 (FLMCR1), will not cause a transition to program mode or erase mode. When actually programming or erasing a flash memory area, the RAMS bit should be cleared to 0. 2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. 3. Block area EB0 contains the vector table. When performing RAM emulation, the vector table is needed in the overlap RAM. Rev. 6.00 Feb 22, 2005 page 840 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.12 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI interrupt is disabled when flash memory is being programmed or erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode*1, to give priority to the program or erase operation. There are three reasons for this: 1. Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. In the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly*2, possibly resulting in MCU runaway. 3. If interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. For these reasons, in on-board programming mode alone there are conditions for disabling interrupt, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or MCU operation. All requests, including NMI interrupt, must therefore be restricted inside and outside the MCU when programming or erasing flash memory. NMI interrupt is also disabled in the error-protection state while the P or E bit remains set in FLMCR1. Notes: 1. Interrupt requests must be disabled inside and outside the MCU until the programming control program has completed programming. 2. The vector may not be read correctly in this case for the following two reasons: * If flash memory is read while being programmed or erased (while the P or E bit is set in FLMCR1), correct read data will not be obtained (undetermined values will be returned). * If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. 21B.13 Flash Memory Programmer Mode Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, flash memory read mode, auto-program mode, autoerase mode, and status read mode are supported. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. In programmer mode, set the mode pins to programmer mode (see table 21B-13) and input a 12 MHz input clock. Rev. 6.00 Feb 22, 2005 page 841 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) Table 21B-13 shows the pin settings for programmer mode. Table 21B-13 Pin Names Mode pins: MD2, MD1, MD0 Mode setting pins: PF0, P16, P14 FWE pin pin Programmer Mode Pin Settings Settings Low level input to MD2, MD1, and MD0. High level input to PF0, low level input to P16 and P14 High level input (in auto-program and auto-erase modes) Reset circuit Oscillator circuit Internal voltage step-down circuit 21B.13.1 Socket Adapter and Memory Map In programmer mode in which the PROM writer is used, reading from memory (verification), writing, and initializing the flash memory (erasing all of its contents) are enabled. At this time, a dedicated conversion socket adapter must be attached to a general-purpose PROM writer. Table 21B-14 shows the types of the socket adapters. For programmer mode on this LSI, one of the socket adapters listed in table 21B-14 should be used. Table 21B-14 Product Name HD64F2638F HD64F2638UF HD64F2638WF HD64F2639UF HD64F2639WF HD64F2630F* HD64F2630UF* HD64F2630WF* Note: * Under development Rev. 6.00 Feb 22, 2005 page 842 of 1484 REJ09B0103-0600 SER VCL XTAL, EXTAL, PLLCAP, PLLVSS pins Type of Socket Adapter Package Type 128 pin QFP (FP-128B) Socket Adapter Type ME2636ESHF1H HF2636Q128D4001 Manufacturer Minato Electronics Inc. Data I/O Japan Corporation Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) Addresses in MCU mode H'000000 Addresses in programmer mode H'00000 Addresses in MCU mode H'000000 Addresses in programmer mode H'00000 On-chip ROM space 256 kbytes (H8S/2638, H8S/2639) On-chip ROM space 384 kbytes (H8S/2630) H'03FFFF H'3FFFF H'05FFFF H'5FFFF Figure 21B-17 On-Chip ROM Memory Map 21B.13.2 Programmer Mode Operation Table 21B-15 shows how the different operating modes are set when using programmer mode, and table 21B-16 lists the commands used in programmer mode. Details of each mode are given below. * Memory Read Mode Memory read mode supports byte reads. * Auto-Program Mode Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. * Auto-Erase Mode Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-programming. * Status Read Mode Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the I/O6 signal. In status read mode, error information is output if an error occurs. Rev. 6.00 Feb 22, 2005 page 843 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) Table 21B-15 Settings for Various Operating Modes in Programmer Mode Pin Names Read Output disable Command write Chip disable*1 H or L H or L H or L*3 H or L L L H L X L L H H H X H Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2. Ain indicates that there is also address input in auto-program mode. 3. For command writes in auto-program and auto-erase modes, input a high level to the FWE pin. Table 21B-16 Programmer Mode Commands Number of Cycles 1+n 129 2 2 1st Cycle Mode Write Write Write Write Address X X X X Data H'00 H'40 H'20 H'71 Mode Read Write Write Write 2nd Cycle Address RA WA X X Data Dout Din H'20 H'71 Command Name Memory read mode Auto-program mode Auto-erase mode Status read mode Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n). 21B.13.3 Memory Read Mode 1. After completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. When reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. 2. In memory read mode, command writes can be performed in the same way as in the command wait state. 3. Once memory read mode has been entered, consecutive reads can be performed. 4. After powering on, memory read mode is entered. Rev. 6.00 Feb 22, 2005 page 844 of 1484 REJ09B0103-0600 EW EO EC Mode FWE I/O7 to I/O0 Data output Hi-Z Data input Hi-Z A18 to A0 Ain*2 X Ain*2 X Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) Table 21B-17 AC Characteristics in Transition to Memory Read Mode Conditions: VCC = 5.0 V 0.5 V, VSS = 0 V, Ta = 25C 5C Item Command write cycle hold time setup time Symbol tnxtc tceh tces tdh tds twep tr tf Min. 20 0 0 50 50 70 -- -- Max. -- -- -- -- -- -- 30 30 Unit s ns ns ns ns ns ns ns EW EW EC EC Data hold time Data setup time Write pulse width rise time fall time Command write A18 to A0 tces CE tceh tnxtc Memory read mode Address stable OE tf WE twep tr tds I/O7 to I/O0 tdh Note: Data is latched on the rising edge of WE. Figure 21B-18 Timing Waveforms for Memory Read after Memory Write Rev. 6.00 Feb 22, 2005 page 845 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) Table 21B-18 AC Characteristics in Transition from Memory Read Mode to Another Mode Conditions: VCC = 5.0 V 0.5 V, VSS = 0 V, Ta = 25C 5C Item Command write cycle hold time setup time Symbol tnxtc tceh tces tdh tds twep tr tf Min. 20 0 0 50 50 70 -- -- Max. -- -- -- -- -- -- 30 30 Unit s ns ns ns ns ns ns ns EW EW EC EC Data hold time Data setup time Write pulse width rise time fall time Memory read mode A18 to A0 Address stable tnxtc CE Other mode command write tces tceh OE tf WE twep tr tds I/O7 to I/O0 Note: Do not enable WE and OE at the same time. tdh Figure 21B-19 Timing Waveforms in Transition from Memory Read Mode to Another Mode Rev. 6.00 Feb 22, 2005 page 846 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) Table 21B-19 AC Characteristics in Memory Read Mode Conditions: VCC = 5.0 V 0.5 V, VSS = 0 V, Ta = 25C 5C Item Access time output delay time output delay time Symbol tacc tce toe tdf toh Min. -- -- -- -- 5 Max. 20 150 150 100 -- Unit s ns ns ns ns A18 to A0 CE Address stable tce toe OE WE VIH tacc toh I/O7 to I/O0 tdf tacc toh EO EC Figure 21B-21 and EO EC EO EC Output disable delay time Data output hold time A18 to A0 Address stable Address stable CE OE WE I/O7 to I/O0 VIL VIL VIH tacc toh tacc toh Figure 21B-20 and Enable State Read Timing Waveforms Address stable tce toe tdf Clock System Read Timing Waveforms Rev. 6.00 Feb 22, 2005 page 847 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.13.4 Auto-Program Mode 1. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. 2. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. The lower 7 bits of the transfer address must be low. If a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. 4. Memory address transfer is performed in the second cycle (figure 21B-22). Do not perform transfer after the third cycle. 5. Do not perform a command write during a programming operation. 6. Perform one auto-program operation for a 128-byte block for each address. Two or more additional programming operations cannot be performed on a previously programmed address block. 7. Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-program operation end decision pin). 8. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling and . Rev. 6.00 Feb 22, 2005 page 848 of 1484 REJ09B0103-0600 EC EO Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) Table 21B-20 AC Characteristics in Auto-Program Mode Conditions: VCC = 5.0 V 0.5 V, VSS = 0 V, Ta = 25C 5C Item Command write cycle hold time setup time Symbol tnxtc tceh tces tdh tds twep twsts tspa tas tah twrite tpns tpnh tr tf Min. 20 0 0 50 50 70 1 -- 0 60 1 100 100 -- -- Max. -- -- -- -- -- -- -- 150 -- -- 3000 -- -- 30 30 Unit s ns ns ns ns ns ms ns ns ns ms ns ns ns ns EW EW EC EC Data hold time Data setup time Write pulse width Status polling start time Status polling access time Address setup time Address hold time Memory write time Write setup time Write end setup time rise time fall time FWE tpnh Address stable tpns tces tceh tnxtc tnxtc A18 to A0 CE OE tf twep tr tas tah Data transfer 1 to 128 bytes twsts tspa WE tds tdh twrite Write operation end decision signal I/O7 I/O6 I/O5 to I/O0 Write normal end decision signal H'40 H'00 Figure 21B-22 Auto-Program Mode Timing Waveforms Rev. 6.00 Feb 22, 2005 page 849 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.13.5 Auto-Erase Mode 1. Auto-erase mode supports only entire memory erasing. 2. Do not perform a command write during auto-erasing. 3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin). 4. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling and . Table 21B-21 AC Characteristics in Auto-Erase Mode Conditions: VCC = 5.0 V 0.5 V, VSS = 0 V, Ta = 25C 5C Item Command write cycle hold time setup time Symbol tnxtc tceh tces tdh tds twep tests tspa terase tens tenh tr tf Min. 20 0 0 50 50 70 1 -- 100 100 100 -- -- Max. -- -- -- -- -- -- -- 150 40000 -- -- 30 30 Unit s ns ns ns ns ns ms ns ms ns ns ns ns Data hold time Data setup time Write pulse width Status polling start time Status polling access time Memory erase time Erase setup time Erase end setup time rise time fall time Rev. 6.00 Feb 22, 2005 page 850 of 1484 REJ09B0103-0600 EC EO EW EW EC EC Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) FWE tenh A18 to A0 tens tces tceh tnxtc tnxtc CE OE tf twep tr tests tspa WE tds tdh terase Erase end decision signal Erase normal end decision signal I/O7 I/O6 I/O5 to I/O0 H'20 H'20 H'00 Figure 21B-23 Auto-Erase Mode Timing Waveforms Rev. 6.00 Feb 22, 2005 page 851 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.13.6 Status Read Mode 1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. The return code is retained until a command write other than a status read mode command write is executed. Table 21B-22 AC Characteristics in Status Read Mode Conditions: VCC = 5.0 V 0.5 V, VSS = 0 V, Ta = 25C 5C Item Read time after command write hold time setup time Symbol tnxtc tceh tces tdh tds twep toe tdf tce tr tf Min. 20 0 0 50 50 70 -- -- -- -- -- Max. -- -- -- -- -- -- 150 100 150 30 30 Unit s ns ns ns ns ns ns ns ns ns ns Rev. 6.00 Feb 22, 2005 page 852 of 1484 REJ09B0103-0600 EW EW EC EO EC EC Data hold time Data setup time Write pulse width output delay time output delay time rise time fall time Disable delay time A18 to A0 tces tceh tnxtc tces tceh tnxtc tnxtc CE tce OE tf twep tr tf twep tr toe WE tds tdh H'71 tds H'71 tdh tdf I/O7 to I/O0 Note: I/O2 and I/O3 are undefined. Figure 21B-24 Status Read Mode Timing Waveforms Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) Table 21B-23 Pin Name I/O7 Attribute Status Read Mode Return Commands I/O6 Command error I/O5 Programming error I/O4 Erase error I/O3 -- I/O2 -- I/O1 I/O0 Normal end decision ProgramEffective ming or address erase count error exceeded 0 0 Count Effective exceeded: 1 address Otherwise: 0 error: 1 Otherwise: 0 Initial value 0 Indications Normal end: 0 Abnormal end: 1 0 Command error: 1 0 0 0 0 -- ProgramErasing -- ming error: 1 Otherwise: 0 error: 1 Otherwise: 0 Otherwise: 0 Note: I/O2 and I/O3 are undefined. 21B.13.7 Status Polling 1. The I/O7 status polling flag indicates the operating status in auto-program/auto-erase mode. 2. The I/O6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase mode. Table 21B-24 Pin Name I/O7 I/O6 I/O0 to I/O5 Status Polling Output Truth Table During Internal Operation 0 0 0 Abnormal End 1 0 0 -- 0 1 0 Normal End 1 1 0 21B.13.8 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 21B-25 Item Standby release (oscillation stabilization time) Programmer mode setup time VCC hold time Stipulated Transition Times to Command Wait State Symbol tosc1 tbmv tdwn Min. 30 10 0 Max. -- -- -- Unit ms ms ms Rev. 6.00 Feb 22, 2005 page 853 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) tosc1 VCC tbmv Memory read mode Command Auto-program mode wait state Auto-erase mode Command wait state Normal/abnormal end decision tdwn 4-5 FWE Note: When using other than the automatic write mode and automatic erase mode, drive the FWE input pin low. Figure 21B-25 Oscillation Stabilization Time, Boot Program Transfer Time, and Power-Down Sequence 21B.13.9 Notes on Memory Programming 1. When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. 2. When performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level. 2. Auto-programming should be performed once only on the same address block. Additional programming cannot be performed on previously programmed address blocks. Rev. 6.00 Feb 22, 2005 page 854 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.14 Flash Memory and Power-Down States In addition to its normal operating state, the flash memory has power-down states in which power consumption is reduced by halting part or all of the internal power supply circuitry. There are three flash memory operating states: (1) Normal operating mode: The flash memory can be read and written to. (2) Power-down mode: Part of the power supply circuitry is halted, and the flash memory can be read when the LSI is operating on the subclock. (3) Standby mode: All flash memory circuits are halted, and the flash memory cannot be read or written to. States (2) and (3) are flash memory power-down states. Table 21B-26 shows the correspondence between the operating states of the LSI and the flash memory. Table 21B-26 Flash Memory Operating States Flash Memory Operating State Normal mode (read/write) LSI Operating State High-speed mode Medium-speed mode Sleep mode Subactive mode* Subsleep mode* Watch mode* Software standby mode Hardware standby mode When PDWND = 0: Power-down mode (read-only) When PDWND = 1: Normal mode (read-only) Standby mode Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are not available in versions other than the U-mask and W-mask versions. Rev. 6.00 Feb 22, 2005 page 855 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.14.1 Notes on Power-Down States 1. When the flash memory is in a power-down state, part or all of the internal power supply circuitry is halted. Therefore, a power supply circuit stabilization period must be provided when returning to normal operation. When the flash memory returns to its normal operating state from a power-down state, bits STS2 to STS0 in SBYCR must be set to provide a wait time of at least 20 s (power supply stabilization time), even if an oscillation stabilization period is not necessary. 2. In a power-down state, FLMCR1, FLMCR2, EBR1, EBR2, RAMER, and FLPWCR cannot be read from or written to. 21B.15 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode, the RAM emulation function, and programmer mode are summarized below. Use the specified voltages and timing for programming and erasing: Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas microcomputer device type* with 256-kbyte and 512-kbyte on-chip flash memory. Only use the specified socket adapter. Failure to observe these points may result in damage to the device. Note: * The H8S/2638 and H8S/2639 are Renesas Technology microcomputer devices with 256 kbytes of on-chip flash memory. The H8S/2630 is a Renesas microcomputer device with 512 kbytes of on-chip flash memory (The H8S/2630 has 384 kbytes of PROM. The area from H'60000 to H'7FFFF should be programmed as H'FF). Powering on and off (see figures 21B-26 to 21B-28): Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low before turning off VCC. When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. Rev. 6.00 Feb 22, 2005 page 856 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) FWE application/disconnection (see figures 21B-26 to 21B-28): FWE application should be carried out when MCU operation is in a stable condition. If MCU operation is not stable, fix the FWE pin low and set the protection state. The following points must be observed concerning FWE application and disconnection to prevent unintentional programming or erasing of flash memory: * Apply FWE when the VCC voltage has stabilized within its rated voltage range. Apply FWE when oscillation has stabilized (after the elapse of the oscillation stabilization time). * In boot mode, apply and disconnect FWE during a reset. * In user program mode, FWE can be switched between high and low level regardless of the reset state. FWE input can also be switched during execution of a program in flash memory. * Do not apply FWE if program runaway has occurred. * Disconnect FWE only when the SWE, ESU, PSU, EV, PV, P, and E bits in FLMCR1 are cleared. Make sure that the SWE, ESU, PSU, EV, PV, P, and E bits are not set by mistake when applying or disconnecting FWE. Do not apply a constant high level to the FWE pin: Apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. Use the recommended algorithm when programming and erasing flash memory: The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. Do not set or clear the SWE bit during execution of a program in flash memory: Wait for at least 100 s after clearing the SWE bit before executing a program or reading data in flash memory. When the SWE bit is set, data in flash memory can be rewritten, but when SWE = 1, flash memory can only be read in program-verify or erase-verify mode. Access flash memory only for verify operations (verification during programming/erasing). Also, do not clear the SWE bit during programming, erasing, or verifying. Similarly, when using the RAM emulation function while a high level is being input to the FWE pin, the SWE bit must be cleared before executing a program or reading data in flash memory. Rev. 6.00 Feb 22, 2005 page 857 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) However, the RAM area overlapping flash memory space can be read and written to regardless of whether the SWE bit is set or cleared. Do not use interrupts while flash memory is being programmed or erased: All interrupt requests, including NMI, should be disabled during FWE application to give priority to program/erase operations. Do not perform additional programming. Erase the memory before reprogramming: In onboard programming, perform only one programming operation on a 128-byte programming unit block. In programmer mode, too, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. Before programming, check that the chip is correctly mounted in the PROM programmer: Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. Do not touch the socket adapter or chip during programming: Touching either of these can cause contact faults and write errors. Rev. 6.00 Feb 22, 2005 page 858 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) Wait time: x Programming/ erasing possible Wait time: 100 s tOSC1 VCC Min. 0 s FWE tMDS*3 Min. 0 s MD2 to MD0*1 tMDS*3 RES SWE set SWE bit SWE cleared Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-off by pulling the pins up or down. 2. See section 24.2.7, 24.3.7, and 24.4.7, Flash Memory Characteristics. 3. Mode programming setup time tMDS (min.) = 200 ns Figure 21B-26 Power-On/Off Timing (Boot Mode) Rev. 6.00 Feb 22, 2005 page 859 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) Wait time: x Programming/ erasing possible Wait time: 100 s tOSC1 VCC Min. 0 s FWE MD2 to MD0*1 tMDS*3 RES SWE set SWE bit SWE cleared Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-off by pulling the pins up or down. 2. See section 24.2.7, 24.3.7, and 24.4.7, Flash Memory Characteristics. 3. Mode programming setup time tMDS (min.) = 200 ns Figure 21B-27 Power-On/Off Timing (User Program Mode) Rev. 6.00 Feb 22, 2005 page 860 of 1484 REJ09B0103-0600 Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) Wait time: x Programming/erasing possible Wait time: 100 s Wait time: x Programming/erasing possible Wait time: 100 s Wait time: x Programming/erasing possible Programming/erasing possible Wait time: 100 s tOSC1 VCC Min. 0 s FWE tMDS tMDS*2 MD2 to MD0 tMDS tRESW RES SWE set Mode change*1 Boot mode SWE cleared Mode User change*1 mode User program mode User mode User program mode SWE bit Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*3 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried out by means of RES input. The state of ports with multiplexed address functions and bus control output pins (AS, RD, WR) will change during this switchover interval (the interval during which the RES pin input is low), and therefore these pins should not be used as output signals during this time. 2. When making a transition from boot mode to another mode, a mode programming setup time tMDS (min.) of 200 ns is necessary with respect to RES clearance timing. 3. See section 24.2.7, 24.3.7, and 24.4.7, Flash Memory Characteristics. Figure 21B-28 Mode Transition Timing (Example: Boot Mode User Mode User Program Mode) Rev. 6.00 Feb 22, 2005 page 861 of 1484 REJ09B0103-0600 Wait time: x Wait time: 100 s Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group) 21B.16 Note on Switching from F-ZTAT Version to Mask ROM Version The mask ROM version does not have the internal registers for flash memory control that are provided in the F-ZTAT version. Table 21B-24 lists the registers that are present in the F-ZTAT version but not in the mask ROM version. If a register listed in table 21B-24 is read in the mask ROM version, an undefined value will be returned. Therefore, if application software developed on the F-ZTAT version is switched to a mask ROM version product, it must be modified to ensure that the registers in table 21B-27 have no effect. Table 21B-27 Register Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Registers Present in F-ZTAT Version but Absent in Mask ROM Version Abbreviation FLMCR1 FLMCR2 EBR1 EBR2 RAMER Address H'FFA8 H'FFA9 H'FFAA H'FFAB H'FEDB Rev. 6.00 Feb 22, 2005 page 862 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) Section 21C ROM (H8S/2635 Group) 21C.1 Overview The H8S/2635 Group has 192 kbytes of on-chip flash memory, or 192 kbytes or 128 kbytes of onchip mask ROM. The ROM is connected to the bus master via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching is thus speeded up, and processing speed increased. The on-chip ROM is enabled and disabled by setting the mode pins (MD2 to MD0). The flash memory version can be erased and programmed on-board, as well as with a specialpurpose PROM programmer. 21C.1.1 Block Diagram Figure 21C-1 shows a block diagram of 192-kbyte and 128-kbyte ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000002 H'000001 H'000003 H'02FFFE (H'01FFFE)* H'02FFFF (H'01FFFF)* Note: * ROM addresses for the H8S/2635 extend from H'000000 to H'02FFFF (192 kbytes), and for the H8S/2634 from H'000000 to H'01FFFF (128 kbytes). Figure 21C-1 Block Diagram of ROM 192 kbytes (128 kbytes)* Rev. 6.00 Feb 22, 2005 page 863 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.1.2 Register Configuration The H8S/2638 and H8S/2639 operating mode is controlled by the mode pins and the MDCR register. The register configuration is shown in table 21C-1. Table 21C-1 Register Configuration Register Name Mode control register Abbreviation MDCR R/W R/W Initial Value Undefined Address* H'FDE7 Note: * Lower 16 bits of the address. 21C.2 Register Descriptions 21C.2.1 Mode Control Register (MDCR) Bit: Initial value: R/W: 7 -- 1 R/W 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 MDS2 --* R 1 MDS1 --* R 0 MDS0 --* R Note: * Determined by pins MD2 to MD0. MDCR is an 8-bit register used to monitor the current H8S/2638 Group, H8S/2639 Group, and H8S/2630 Group operating mode. Bit 7--Reserved: Only 1 should be written to these bits. Bits 6 to 3--Reserved: These bits are always read as 0 and cannot be modified. Bits 2 to 0--Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD2 to MD0. MDS2 to MDS0 are read-only bits, and cannot be modified. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a reset. 21C.3 Operation The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. Word data must start at an even address. Rev. 6.00 Feb 22, 2005 page 864 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) The on-chip ROM is enabled and disabled by setting the mode pins (MD2, MD1, and MD0). These settings are shown in table 21C-2. Table 21C-2 Operating Modes and ROM (F-ZTAT Version) Mode Pins Operating Mode Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode 1 1 0 1 -- FWE 0 MD2 0 MD1 0 MD0 0 1 0 1 0 1 0 Enabled (192 kbytes/ 128 kbytes)*3 Enabled (192 kbytes/ 128 kbytes)*3 -- Enabled (192 kbytes/ 128 kbytes)*3 Enabled (192 kbytes/ 128 kbytes)*3 -- Enabled (192 kbytes/ 128 kbytes)*3 Enabled (192 kbytes/ 3 128 kbytes)* Disabled On-Chip ROM -- Mode 7 1 Mode 8 Mode 9 Mode 10 -- Boot mode (advanced expanded mode with on-chip ROM enabled)*1 Boot mode (advanced single-chip 2 mode)* -- User program mode (advanced expanded mode with on-chip ROM enabled)*1 User program mode (advanced single2 chip mode)* 1 0 0 1 0 1 0 Mode 11 1 Mode 12 Mode 13 Mode 14 1 0 1 0 1 0 Mode 15 1 Notes: 1. Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced expanded mode with on-chip ROM enabled. 2. Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced single-chip mode. Rev. 6.00 Feb 22, 2005 page 865 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 3. The H8S/2635 has 192 kbytes of on-chip ROM. The H8S/2634 has 128 kbytes of onchip ROM. Table 21C-3 Operating Modes and ROM (Mask ROM Version) Mode Pins Operating Mode Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode 1 1 0 1 -- MD2 0 MD1 0 MD0 0 1 0 1 0 1 0 Enabled (192 kbytes/ 128 kbytes)* Enabled (192 kbytes/ 128 kbytes)* Disabled On-Chip ROM -- Mode 7 1 Note: * The H8S/2635 has 192 kbytes of on-chip ROM. The H8S/2634 has 128 kbytes of on-chip ROM. Rev. 6.00 Feb 22, 2005 page 866 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.4 Flash Memory Overview 21C.4.1 Features The H8S/2635 has 192 kbytes of on-chip flash memory, or 192 kbytes or 128 kbytes of on-chip mask ROM. The features of the flash memory are summarized below. * Four flash memory operating modes Program mode Erase mode Program-verify mode Erase-verify mode * Programming/erase methods The flash memory is programmed 128 bytes at a time. Block erase (in single-block units) can be performed. To erase the entire flash memory, each block must be erased in turn. Block erasing can be performed as required on 4 kbytes, 32 kbytes, and 64 kbytes blocks. * Programming/erase times The flash memory programming time is 10 ms (typ.) for simultaneous 128-byte programming, equivalent to 80 s (typ.) per byte, and the erase time is 100 ms (typ.). * Reprogramming capability The flash memory can be reprogrammed up to 100 times. * On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: Boot mode User program mode * Automatic bit rate adjustment With data transfer in boot mode, the LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. * Flash memory emulation in RAM Flash memory programming can be emulated in real time by overlapping a part of RAM onto flash memory. * Protect modes There are three protect modes, hardware, software, and error protection, which allow protected status to be designated for flash memory program/erase/verify operations. Rev. 6.00 Feb 22, 2005 page 867 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) * Programmer mode Flash memory can be programmed/erased in programmer mode, using a PROM programmer, as well as in on-board programming mode. 21C.4.2 Block Diagram Internal address bus Internal data bus (16 bits) Module bus FLMCR1 FLMCR2 EBR1 EBR2 RAMER FLPWCR Bus interface/controller Operating mode FWE pin Mode pin Flash memory (192 kbytes) Legend: FLMCR1: FLMCR2: EBR1: EBR2: RAMER: FLPWCR: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Flash memory power control register Figure 21C-2 Block Diagram of Flash Memory Rev. 6.00 Feb 22, 2005 page 868 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.4.3 Mode Transitions When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the microcomputer enters an operating mode as shown in figure 21C-3. In user mode, flash memory can be read but not programmed or erased. The boot, user program and programmer modes are provided as modes to write and erase the flash memory. MD1 = 1, MD2 = 1, FWE = 0 User mode (on-chip ROM enabled) *1 RES = 0 Reset state RES = 0 MD1 = 1, MD2 = 1, FWE = 1 RES = 0 MD2 = 0, MD1 = 1, FWE = 1 RES = 0 Programmer mode *2 FWE = 1 FWE = 0 *1 User program mode Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. RAM emulation possible 2. MD0 = 0, MD1 = 0, MD2 = 0, P14 = 0, P16 = 0, PF0 = 1 Figure 21C-3 Flash Memory State Transitions Rev. 6.00 Feb 22, 2005 page 869 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.4.4 On-Board Programming Modes Boot Mode 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host Host Programming control program New application program New application program Chip Boot program Flash memory RAM SCI Chip Boot program Flash memory RAM Boot program area SCI Application program (old version) Application program (old version) Programming control program 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, total flash memory erasure is performed, without regard to blocks. Host 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host New application program Chip Boot program Flash memory RAM Boot program area Flash memory preprogramming erase Programming control program Chip SCI Boot program Flash memory RAM Boot program area New application program Programming control program SCI Program execution state Rev. 6.00 Feb 22, 2005 page 870 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) User Program Mode 1. Initial state The FWE assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory. Host Programming/ erase control program New application program New application program 2. Programming/erase control program transfer When user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to RAM. Host Chip Boot program Flash memory FWE assessment program Chip SCI RAM Boot program Flash memory FWE assessment program SCI RAM Transfer program Transfer program Programming/ erase control program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. Host 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host New application program Chip Boot program Flash memory FWE assessment program Chip SCI RAM Boot program Flash memory FWE assessment program Transfer program Programming/ erase control program Programming/ erase control program SCI RAM Transfer program Flash memory erase New application program Program execution state Rev. 6.00 Feb 22, 2005 page 871 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.4.5 Flash Memory Emulation in RAM Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. SCI Flash memory Emulation block RAM Overlap RAM (emulation is performed on data written in RAM) Application program Execution state Figure 21C-4 Reading Overlap RAM Data in User Mode or User Program Mode When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten. Rev. 6.00 Feb 22, 2005 page 872 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) SCI Flash memory Programming data RAM Application program Overlap RAM (programming data) Programming control program execution state Figure 21C-5 Writing Overlap RAM Data in User Program Mode 21C.4.6 Differences between Boot Mode and User Program Mode Table 21C-4 Differences between Boot Mode and User Program Mode Boot Mode Total erase Block erase Programming control program* Yes No Program/program-verify User Program Mode Yes Yes Erase/erase-verify Program/program-verify Emulation Note: * To be provided by the user, in accordance with the recommended algorithm. Rev. 6.00 Feb 22, 2005 page 873 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.4.7 Block Configuration The H8S/2635 has 192 kbytes of flash memory, which is divided into two 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. H8S/2635 Address H'00000 4 kbytes x 8 32 kbytes 192 kbytes 64 kbytes 64 kbytes Address H'2FFFF Figure 21C-6 Flash Memory Block Configuration Rev. 6.00 Feb 22, 2005 page 874 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.5 Pin Configuration The flash memory is controlled by means of the pins shown in table 21C-5. Table 21C-5 Pin Configuration Pin Name Reset Flash write enable Mode 2 Mode 1 Mode 0 Port F0 Port 16 Port 14 Transmit data Receive data Abbreviation I/O Input Input Input Input Input Input Input Input Output Input Function Reset Flash memory program/erase protection by hardware Sets MCU operating mode Sets MCU operating mode Sets MCU operating mode Sets MCU operating mode in programmer mode Sets MCU operating mode in programmer mode Sets MCU operating mode in programmer mode Serial transmit data output Serial receive data input MD2 MD1 MD0 PF0 P16 P14 TxD1 RxD1 SER FWE Rev. 6.00 Feb 22, 2005 page 875 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.6 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 21C-6. Table 21C-6 Register Configuration Register Name Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Abbreviation FLMCR1*4 FLMCR2*4 EBR1*4 EBR2*4 RAMER *4 R/W R/W R R/W R/W R/W R/W Initial Value H'00*2 H'00 H'00*3 H'00*3 H'00 H'00*3 Address*1 H'FFA8 H'FFA9 H'FFAA H'FFAB H'FEDB H'FFAC Flash memory power control register FLPWCR*4 Notes: 1. Lower 16 bits of the address. 2. When a high level is input to the FWE pin, the initial value is H'80. 3. When a low level is input to the FWE pin, or if a high level is input and the SWE1 bit in FLMCR1 is not set, these registers are initialized to H'00. 4. FLMCR1, FLMCR2, EBR1, and EBR2, RAMER, and FLPWCR are 8-bit registers. Use byte access on these registers. Rev. 6.00 Feb 22, 2005 page 876 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.7 Register Descriptions 21C.7.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for on-chip flash memory is entered by setting SWE bit to 1 when FWE = 1, then setting the PV or EV bit. Program mode for on-chip flash memory is entered by setting SWE bit to 1 when FWE = 1, then setting the PSU bit, and finally setting the P bit. Erase mode for onchip flash memory is entered by setting SWE bit to 1 when FWE = 1, then setting the ESU bit, and finally setting the E bit. FLMCR1 is initialized by a reset, and in hardware standby mode and software standby mode. Its initial value is H'80 when a high level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes are enabled only in the following cases: Writes to bit SWE of FLMCR1 enabled when FWE = 1, to bits ESU, PSU, EV, and PV when FWE = 1 and SWE = 1, to bit E when FWE = 1, SWE = 1 and ESU = 1, and to bit P when FWE = 1, SWE = 1, and PSU = 1. Bit: Initial value: R/W: 7 FWE --* R 6 SWE 0 R/W 5 ESU 0 R/W 4 PSU 0 R/W 3 EV 0 R/W 2 PV 0 R/W 1 E 0 R/W 0 P 0 R/W Note: * Determined by the state of the FWE pin. Bit 7--Flash Write Enable Bit (FWE): Sets hardware protection against flash memory programming/erasing. Bit 7 FWE 0 1 Description When a low level is input to the FWE pin (hardware-protected state) When a high level is input to the FWE pin Rev. 6.00 Feb 22, 2005 page 877 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) Bit 6--Software Write Enable Bit (SWE): This bit selects write and erase valid/invalid of the flash memory. Set it when setting bits 5 to 0, bits 7 to 0 of EBR1, and bits 2 to 0 of EBR2. Bit 6 SWE 0 1 Description Writes disabled Writes enabled [Setting condition] * When FWE = 1 (Initial value) Bit 5--Erase Setup Bit (ESU): Prepares for a transition to erase mode. Set this bit to 1 before setting the E bit in FLMCR1 to 1. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time. Bit 5 ESU 0 1 Description Erase setup cleared Erase setup [Setting condition] * When FWE = 1 and SWE = 1 (Initial value) Bit 4--Program Setup Bit (PSU): Prepares for a transition to program mode. Set this bit to 1 before setting the P bit in FLMCR1 to 1. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time. Bit 4 PSU 0 1 Description Program setup cleared Program setup [Setting condition] * When FWE = 1 and SWE = 1 (Initial value) Rev. 6.00 Feb 22, 2005 page 878 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) Bit 3--Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3 EV 0 1 Description Erase-verify mode cleared Transition to erase-verify mode [Setting condition] * When FWE = 1 and SWE = 1 (Initial value) Bit 2--Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time. Bit 2 PV 0 1 Description Program-verify mode cleared Transition to program-verify mode [Setting condition] * When FWE = 1 and SWE = 1 (Initial value) Bit 1--Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time. Bit 1 E 0 1 Description Erase mode cleared Transition to erase mode [Setting condition] * When FWE = 1, SWE = 1, and ESU = 1 (Initial value) Bit 0--Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU, ESU, EV, PV, or E bit at the same time. Rev. 6.00 Feb 22, 2005 page 879 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) Bit 0 P 0 1 Description Program mode cleared Transition to program mode [Setting condition] * When FWE = 1, SWE = 1, and PSU = 1 (Initial value) 21C.7.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is an 8-bit register used for flash memory operating mode control. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00. Bit: Initial value: R/W: 7 FLER 0 R 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 -- 0 -- 0 -- 0 -- Note: FLMCR2 is a read-only register, and should not be written to. Bit 7--Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state. Bit 7 FLER 0 Description Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] * 1 Reset or hardware standby mode An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] * See section 21C.10.3, Error Protection (Initial value) Bits 6 to 0--Reserved: These bits always read 0. Rev. 6.00 Feb 22, 2005 page 880 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.7.3 Erase Block Register 1 (EBR1) EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be automatically cleared to 0. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory erase block configuration is shown in table 21C-7. Bit: Initial value: R/W: 7 EB7 0 R/W 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W 3 EB3 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W 0 EB0 0 R/W 21C.7.4 Erase Block Register 2 (EBR2) EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin. Bit 0 will be initialized to 0 if bit SWE of FLMCR1 is not set, even though a high level is input to pin FWE. When a bit in EBR2 is set to 1, the corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be automatically cleared to 0. On the H8S/2635 bits 7 to 3 are reserved. Only 0 may be written to these reserved bits. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory erase block configuration is shown in table 21C-7. Bit: Initial value: R/W: 7 -- 0 R/W 6 -- 0 R/W 5 -- 0 R/W 4 -- 0 R/W 3 -- 0 R/W 2 EB10 0 R/W 1 EB9 0 R/W 0 EB8 0 R/W Note: Bits 7 to 3 are reserved and only 0 may be written to them. Rev. 6.00 Feb 22, 2005 page 881 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) Table 21C-7 Flash Memory Erase Blocks Block (Size) EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) EB8 (32 kbytes) EB9 (64 kbytes) EB10 (64 kbytes) Addresses H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF H'008000 to H'00FFFF H'010000 to H'01FFFF H'020000 to H'02FFFF 21C.7.5 RAM Emulation Register (RAMER) RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. RAMER settings should be made in user mode or user program mode. Flash memory area divisions are shown in table 21C-8. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bit: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 -- 0 R/W 4 -- 0 R/W 3 RAMS 0 R/W 2 RAM2 0 R/W 1 RAM1 0 R/W 0 RAM0 0 R/W Rev. 6.00 Feb 22, 2005 page 882 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) Bits 7 and 6--Reserved: These bits always read 0. Bits 5 and 4--Reserved: Only 0 may be written to these bits. Bit 3--RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory block are program/erase-protected. Bit 3 RAMS 0 1 Description Emulation not selected Program/erase-protection of all flash memory blocks is disabled Emulation selected Program/erase-protection of all flash memory blocks is enabled (Initial value) Bits 2 to 0--Flash Memory Area Selection: These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM. (See table 21C-8.) Table 21C-8 Flash Memory Area Divisions Addresses H'FFD800 to H'FFE7FF H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF Block Name RAM area 4 kbytes EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) RAMS 0 1 1 1 1 1 1 1 1 RAM1 * 0 0 0 0 1 1 1 1 RAM1 * 0 0 1 1 0 0 1 1 RAM0 * 0 1 0 1 0 1 0 1 *: Don't care Rev. 6.00 Feb 22, 2005 page 883 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.7.6 Flash Memory Power Control Register (FLPWCR) Bit: Initial value: R/W: 7 PDWND 0 R/W 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. Bit 7--Power-Down Disable (PDWND): The subactive mode is not available in versions other than the U-mask and W-mask versions. Only 0 should be written to this bit in the case of versions other than the U-mask and W-mask versions. See section 21.B.14, Flash Memory and Power-Down States, for more information. Bit 7 PDWND 0 1 Description Transition to flash memory power-down mode enabled Transition to flash memory power-down mode disabled (Initial value) Bits 6 to 0--Reserved: These bits always read 0. Rev. 6.00 Feb 22, 2005 page 884 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.8 On-Board Programming Modes When pins are set to on-board programming mode and a reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 21C-9. For a diagram of the transitions to the various flash memory modes, see figure 21C-3. Table 21C-9 Setting On-Board Programming Modes Mode Boot mode User program mode Expanded mode Single-chip mode Expanded mode Single-chip mode 1 FWE 1 MD2 0 0 1 1 MD1 1 1 1 1 MD0 0 1 0 1 Rev. 6.00 Feb 22, 2005 page 885 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.8.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The SCI channel to be used is set to asynchronous mode. When a reset-start is executed after the H8S/2635 Group's pins have been set to boot mode, the boot program built into the H8S/2635 Group are started and the programming control program prepared in the host is serially transmitted to the H8S/2635 Group via the SCI. In the H8S/2635 Group, the programming control program received via the SCI is written into the programming control program area in on-chip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 21C-7, and the boot mode execution procedure in figure 21C-8. LSI Flash memory Host Write data reception Verify data transmission RxD1 SCI1 TxD1 On-chip RAM Figure 21C-7 System Configuration in Boot Mode Rev. 6.00 Feb 22, 2005 page 886 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate Chip measures low period of H'00 data transmitted by host Chip calculates bit rate and sets value in bit rate register After bit rate adjustment, chip transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, LSI transmits one H'AA data byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte Chip transmits received number of bytes to host as verify data (echo-back) n=1 Host transmits programming control program sequentially in byte units Chip transmits received programming control program to host as verify data (echo-back) Transfer received programming control program to on-chip RAM No Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, chip transmits one H'AA data byte to host Execute programming control program transferred to on-chip RAM n+1n n = N? Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. Figure 21C-8 Boot Mode Execution Procedure Rev. 6.00 Feb 22, 2005 page 887 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) Automatic SCI Bit Rate Adjustment Start bit Stop bit D0 D1 D2 D3 D4 D5 D6 D7 Low period (9 bits) measured (H'00 data) High period (1 or more bits) When boot mode is initiated, the LSI measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The LSI calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the LSI. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host's transmission bit rate and the LSI's system clock frequency, there will be a discrepancy between the bit rates of the host and the LSI. Set the host transfer bit rate at 4,800, 9,600 or 19,200 bps to operate the SCI properly. Table 21C-10 shows host transfer bit rates and system clock frequencies for which automatic adjustment of the LSI bit rate is possible. The boot program should be executed within this system clock range. Table 21C-10 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate Is Possible Host Bit Rate 4,800 bps 9,600 bps 19,200 bps System Clock Frequency for which Automatic Adjustment of LSI Bit Rate Is Possible 4 to 20 MHz 8 to 20 MHz 16 to 20 MHz Note: The system clock frequency used in boot mode is generated by an external crystal oscillator element. PLL frequency multiplication is not used. Rev. 6.00 Feb 22, 2005 page 888 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an area used by the boot program and an area to which the programming control program is transferred via the SCI, as shown in figure 21C-9. The boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host. H'FFE000 Programming control program area (2 kbytes) H'FFE7FF H'FFE800 Boot program area (1.9 kbytes) H'FFEFBF Note: The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note also that the boot program remains in this area of the on-chip RAM even after control branches to the programming control program. Figure 21C-9 RAM Areas in Boot Mode Notes on Use of Boot Mode: * When the chip comes out of reset in boot mode, it measures the low-level period of the input at the SCI's RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes approximately 100 states before the chip is ready to measure the low-level period of the RxD1 pin. * In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. * Interrupts cannot be used while the flash memory is being programmed or erased. * The RxD1 and TxD1 pins should be pulled up on the board. Rev. 6.00 Feb 22, 2005 page 889 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) * Before branching to the programming control program (RAM area H'FFE000), the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD1, goes to the high-level output state (P33DDR = 1, P33DR = 1). The contents of the CPU's internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. The initial values of other on-chip registers are not changed. * Boot mode can be entered by making the pin settings shown in table 21C-9 and executing a reset-start. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the FWE pin and mode pins, and executing reset release*1. Boot mode can also be cleared by a WDT overflow reset. Do not change the mode pin input levels in boot mode, and do not drive the FWE pin low while the boot program is being executed or while flash memory is being programmed or erased*2. * If the mode pin input levels are changed (for example, from low to high) during a reset, the , ) state of ports with multiplexed address functions and bus control output pins (AS, will change according to the change in the microcomputer's operating mode*3. Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS = 4 states) with respect to the reset release timing. 2. For precautions on applying and disconnecting FWE, see section 21C.15, Flash Memory Programming and Erasing Precautions. 3. See Appendix D, Pin States. 21C.8.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of FWE control and supply of programming data, and storing a program/erase control program in part of the program area as necessary. Rev. 6.00 Feb 22, 2005 page 890 of 1484 REJ09B0103-0600 RWH DR Section 21C ROM (H8S/2635 Group) To select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7), and apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 6 and 7. The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip RAM or external memory. If the program is to be located in external memory, the instruction for writing to flash memory, and the following instruction, should be placed in on-chip RAM. Figure 21C-10 shows the procedure for executing the program/erase control program when transferred to on-chip RAM. Write the FWE assessment program and transfer program (and the program/erase control program if necessary) beforehand MD2, MD1, MD0 = 110, 111 Reset-start Transfer program/erase control program to RAM Branch to program/erase control program in RAM area FWE = high* Execute program/erase control program (flash memory rewriting) Clear FWE* Branch to flash memory application program Notes: Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only when the flash memory is programmed or erased. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. * For further information on FWE application and disconnection, see section 21B.15, Flash Memory Programming and Erasing Precautions. Figure 21C-10 User Program Mode Execution Procedure Rev. 6.00 Feb 22, 2005 page 891 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.9 Programming/Erasing Flash Memory A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes are made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1 for on-chip flash memory. The flash memory cannot be read while it is being written or erased. The flash memory cannot be read while being programmed or erased. Therefore, the program (user program) that controls flash memory programming/erasing should be located and executed in on-chip RAM or external memory. If the program is to be located in external memory, the instruction for writing to flash memory, and the following instruction, should be placed in on-chip RAM. Also ensure that the DTC is not activated before or after execution of the flash memory write instruction. In the following operation descriptions, wait times after setting or clearing individual bits in FLMCR1 are given as parameters; for details of the wait times, see section 24.2.7 and 24.3.7, Flash Memory Characteristics. Notes: 1. Operation is not guaranteed if bits SWE, ESU, PSU, EV, PV, E, and P of FLMCR1 are set/reset by a program in flash memory in the corresponding address areas. 2. When programming or erasing, set FWE to 1 (programming/erasing will not be executed if FWE = 0). 3. Programming should be performed in the erased state. Do not perform additional programming on previously programmed addresses. Rev. 6.00 Feb 22, 2005 page 892 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) *3 E=1 Erase setup state E=0 Normal mode ESU = 1 ESU = 0 Erase-verify mode Erase mode *1 FWE = 1 FWE = 0 *2 EV = 1 EV = 0 PSU = 1 PSU = 0 On-board SWE = 1 Software programming mode programming Software programming enable disable state SWE = 0 state *4 P=1 Program setup state P=0 Program mode PV = 1 PV = 0 Program-verify mode Notes: In order to perform a normal read of flash memory, SWE must be cleared to 0. Also note that verify-reads can be performed during the programming/erasing process. 1. : Normal mode : On-board programming mode 2. Do not make a state transition by setting or clearing multiple bits simultaneously. 3. After a transition from erase mode to the erase setup state, do not enter erase mode without passing through the software programming enable state. 4. After a transition from program mode to the program setup state, do not enter program mode without passing through the software programming enable state. Figure 21C-11 FLMCR1 Bit Settings and State Transitions Rev. 6.00 Feb 22, 2005 page 893 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.9.1 Program Mode When writing data or programs to flash memory, the program/program-verify flowchart shown in figure 21C-12 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a time. The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N) are shown in table 24-22 in section 24.2.7, and in table 24-34 in section 24.3.7, and in table 24-46 in section 24.4.7, Flash Memory Characteristics. Following the elapse of (tsswe) s or more after the SWE bit is set to 1 in FLMCR1, 128-byte data is written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00 and H'80, 128 consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. Set a value greater than (tspsu + tsp + tcp + tcpsu) s as the WDT overflow period. Preparation for entering program mode (program setup) is performed next by setting the PSU bit in FLMCR1. The operating mode is then switched to program mode by setting the P bit in FLMCR1 after the elapse of at least (tspsu) s. The time during which the P bit is set is the flash memory programming time. Make a program setting so that the time for one programming operation is within the range of (tsp) s. The wait time after P bit setting must be changed according to the degree of progress through the programming operation. For details see "Notes on Program/Program-Verify Procedure." Rev. 6.00 Feb 22, 2005 page 894 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.9.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of the given programming time, clear the P bit in FLMCR1, then wait for at least (tcp) s before clearing the PSU bit to exit program mode. After exiting program mode, the watchdog timer setting is also cleared. The operating mode is then switched to program-verify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (tspv) s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (tspvr) s after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 21C-12) and transferred to RAM. After verification of 128 bytes of data has been completed, exit program-verify mode, wait for at least (tcpv) s, then clear the SWE bit in FLMCR1. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. The maximum number of repetitions of the program/program-verify sequence is indicated by the maximum programming count (N). Leave a wait time of at least (tcswe) s after clearing SWE. Notes on Program/Program-Verify Procedure 1. In order to perform 128-byte-unit programming, the lower 8 bits of the write start address must be H'00 or H'80. 2. When performing continuous writing of 128-byte data to flash memory, byte-unit transfer should be used. 128-byte data transfer is necessary even when writing fewer than 128 bytes of data. Write H'FF data to the extra addresses. 3. Verify data is read in word units. 4. The write pulse is applied and a flash memory write executed while the P bit in FLMCR1 is set. In the chip, write pulses should be applied as follows in the program/program-verify procedure to prevent voltage stress on the device and loss of write data reliability. a. After write pulse application, perform a verify-read in program-verify mode and apply a write pulse again for any bits read as 1 (reprogramming processing). When all the 0-write bits in the 128-byte write data are read as 0 in the verify-read operation, the program/program-verify procedure is completed. In the chip, the number of loops in reprogramming processing is guaranteed not to exceed the maximum value of the maximum programming count (N). Rev. 6.00 Feb 22, 2005 page 895 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) b. After write pulse application, a verify-read is performed in program-verify mode, and programming is judged to have been completed for bits read as 0. The following processing is necessary for programmed bits. When programming is completed at an early stage in the program/program-verify procedure: If programming is completed in the 1st to 6th reprogramming processing loop, additional programming should be performed on the relevant bits. Additional programming should only be performed on bits which first return 0 in a verify-read in certain reprogramming processing. When programming is completed at a late stage in the program/program-verify procedure: If programming is completed in the 7th or later reprogramming processing loop, additional programming is not necessary for the relevant bits. c. If programming of other bits is incomplete in the 128 bytes, reprogramming processing should be executed. If a bit for which programming has been judged to be completed is read as 1 in a subsequent verify-read, a write pulse should again be applied to that bit. 5. The period for which the P bit in FLMCR1 is set (the write pulse width) should be changed according to the degree of progress through the program/program-verify procedure. For detailed wait time specifications, see section 24.2.7, 24.3.7, and 24.4.7, Flash Memory Characteristics. Item Wait time after P bit setting Symbol tsp Item When reprogramming loop count (n) is 1 to 6 When reprogramming loop count (n) is 7 or more In case of additional programming processing* Symbol tsp30 tsp200 tsp10 Note: * Additional programming processing is necessary only when the reprogramming loop count (n) is 1 to 6. 6. The program/program-verify flowchart for the H8S/2638, H8S/2639, and H8S/2630 are shown in figure 21C-12. To cover the points noted above, bits on which reprogramming processing is to be executed, and bits on which additional programming is to be executed, must be determined as shown below. Since reprogram data and additional-programming data vary according to the progress of the programming procedure, it is recommended that the following data storage areas (128 bytes each) be provided in RAM. Rev. 6.00 Feb 22, 2005 page 896 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) Reprogram Data Computation Table Result of Verify-Read after Write Pulse (X) Application (V) Result of Operation 0 1 0 1 1 0 1 1 (D) 0 0 1 1 Comments Programming completed: reprogramming processing not to be executed Programming incomplete: reprogramming processing to be executed Still in erased state: no action Legend: (D): Source data of bits on which programming is executed (X): Source data of bits on which reprogramming is executed Additional-Programming Data Computation Table Result of Verify-Read after Write Pulse (Y) (X') Application (V) Result of Operation 0 0 0 Comments Programming by write pulse application judged to be completed: additional programming processing to be executed Programming by write pulse application incomplete: additional programming processing not to be executed Programming already completed: additional programming processing not to be executed Still in erased state: no action 0 1 1 1 1 0 1 1 1 Legend: (Y): Data of bits on which additional programming is executed (X'): Data of bits on which reprogramming is executed in a certain reprogramming loop 7. It is necessary to execute additional programming processing during the course of the chip program/program-verify procedure. However, once 128-byte-unit programming is finished, additional programming should not be carried out on the same address area. When executing reprogramming, an erase must be executed first. Note that normal operation of reads, etc., is not guaranteed if additional programming is performed on addresses for which a program/program-verify operation has finished. Rev. 6.00 Feb 22, 2005 page 897 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) Write pulse application subroutine Start of programming START Set SWE bit in FLMCR1 Wait (tsswe) s Store 128-byte program data in program data area and reprogram data area Sub-Routine Write Pulse WDT enable Set PSU bit in FLMCR1 Wait (tspsu) s Set P bit in FLMCR1 Wait (tsp) s Clear P bit in FLMCR1 Wait (tcp) s Clear PSU bit in FLMCR1 Wait (tcpsu) s Disable WDT Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. *7 *4 *7 Start of programming n=1 m=0 *5*7 End of programming Write 128-byte data in RAM reprogram data area consecutively to flash memory *1 Sub-Routine-Call *7 Write pulse See Note 6 for pulse width Set PV bit in FLMCR1 *7 Wait (tspv) s H'FF dummy write to verify address *7 Wait (tspvr) s End Sub Increment address Note: 6 Write Pulse Width Number of Writes n Write Time (tsp) sec Write data = verify data? Read verify data *7 *2 No m=1 No nn+1 1 2 3 4 5 6 7 8 9 10 11 12 13 30 30 30 30 30 30 200 200 200 200 200 200 200 Yes 6n? Yes Additional-programming data computation Transfer additional-programming data to additional-programming data area Reprogram data computation *4 *3 *4 Transfer reprogram data to reprogram data area 128-byte data verification completed? No 998 999 1000 200 200 200 Yes Clear PV bit in FLMCR1 Reprogram Wait (tcpv) s 6 n? No Note: Use a 10 s write pulse for additional programming. *7 RAM Program data storage area (128 bytes) Yes Successively write 128-byte data from additional1 programming data area in RAM to flash memory * Sub-Routine-Call Write Pulse (Additional programming) Reprogram data storage area (128 bytes) m=0? Yes Clear SWE bit in FLMCR1 Wait (tcswe) s End of programming No n (N)? *7 No Additional-programming data storage area (128 bytes) Yes Clear SWE bit in FLMCR1 Wait (tcswe) s Programming failure *7 Notes: 1. 2. 3. 4. 5. 7. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Verify data is read in 16-bit (word) units. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM. The contents of the reprogram data area and additional data area are modified as programming proceeds. A write pulse of 30 s or 200 s is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths. When writing of additional-programming data is executed, a 10 s write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied. The wait times and value of N are shown in section 24.2.7, 24.3.7, and 24.4.7, Flash Memory Characteristics. Reprogram Data Computation Table Original Data Verify Data Reprogram Data Additional-Programming Data Computation Table (X) 1 0 1 1 Still in erased state; no action Comments Programming completed Programming incomplete; reprogram (D) 0 0 1 1 (V) 0 1 0 1 Reprogram Data (X') 0 0 1 1 Verify Data Additional(V) Programming Data (Y) 0 1 0 1 0 1 1 1 Comments Additional programming to be executed Additional programming not to be executed Additional programming not to be executed Additional programming not to be executed Figure 21C-12 Program/Program-Verify Flowchart Rev. 6.00 Feb 22, 2005 page 898 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.9.3 Erase Mode When erasing flash memory, the single-block erase flowchart shown in figure 21C-13 should be followed. The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and the maximum number of erase operations (N) are shown in table 24-10 in section 24.2.7 and 24.3.7, Flash Memory Characteristics. To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in erase block register 1 and 2 (EBR1, EBR2) at least (tsswe) s after setting the SWE bit to 1 in FLMCR1. Next, the watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. Set a value greater than (tse) ms + (tsesu + tce + tcesu) s as the WDT overflow period. Preparation for entering erase mode (erase setup) is performed next by setting the ESU bit in FLMCR1. The operating mode is then switched to erase mode by setting the E bit in FLMCR1 after the elapse of at least (tsesu) s. The time during which the E bit is set is the flash memory erase time. Ensure that the erase time does not exceed (tse) ms. Note: With flash memory erasing, preprogramming (setting all memory data in the memory to be erased to all 0) is not necessary before starting the erase procedure. 21C.9.4 Erase-Verify Mode In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the fixed erase time, clear the E bit in FLMCR1, then wait for at least (tce) s before clearing the ESU bit to exit erase mode. After exiting erase mode, the watchdog timer setting is also cleared. The operating mode is then switched to erase-verify mode by setting the EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (tsev) s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (tsevr) s after the dummy write before performing this read operation. If the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. If the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is indicated by the maximum erase count (N). When verification is completed, exit erase-verify mode, and wait for at least (tcev) s. If erasure has been completed on all the erase blocks, clear the SWE bit in FLMCR1, and leave a wait time of at least (tcswe) s. Rev. 6.00 Feb 22, 2005 page 899 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) If erasing multiple blocks, set a single bit in EBR1/EBR2 for the next block to be erased, and repeat the erase/erase-verify sequence as before. Start *1 Perform erasing in block units. Set SWE bit in FLMCR1 Wait (tsswe) s n=1 Set EBR1 or EBR2 Enable WDT Set ESU bit in FLMCR1 Wait (tsesu) s Set E bit in FLMCR1 Wait (tse) ms Clear E bit in FLMCR1 Wait (tce) s Clear ESU bit in FLMCR1 Wait (tcesu) s Disable WDT Set EV bit in FLMCR1 Wait (tsev) s Set block start address as verify address *5 *5 *5 *3 *4 *5 Start of erase *5 Erase halted *5 nn+1 H'FF dummy write to verify address Wait (tsevr) s Increment address Read verify data Verify data = all 1s? Yes No Last address of block? Yes Clear EV bit in FLMCR1 Wait (tcev) s *5 *5 *2 No Clear EV bit in FLMCR1 Wait (tcev) s *5 *5 n (N)? Clear SWE bit in FLMCR1 Wait (tcswe) s End of erasing *5 No Yes Clear SWE bit in FLMCR1 Wait (tcswe) s Erase failure *5 Notes: 1. 2. 3. 4. 5. Prewriting (setting erase block data to all 0s) is not necessary. Verify data is read in 16-bit (word) units. Make only a single-bit specification in the erase block registers (EBR1 and EBR2). Two or more bits must not be set simultaneously. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn. The wait times and the value of N are shown in section 24.2.7, 24.3.7, and 24.4.7, Flash Memory Characteristics. Figure 21C-13 Erase/Erase-Verify Flowchart Rev. 6.00 Feb 22, 2005 page 900 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.10 Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 21C.10.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase block register 2 (EBR2). The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained in the error-protected state (See table 21C-11). Table 21C-11 Hardware Protection Functions Item FWE pin protection Description * When a low level is input to the FWE pin, FLMCR1, FLMCR2, (except bit FLER) EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. In a reset (including a WDT reset) and in standby mode, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. In a reset via the pin, the reset state is not entered unless the pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the pin low for the pulse width specified in the AC Characteristics section. Program Yes Erase Yes Reset/standby protection * Yes Yes SER SER SER * SER Rev. 6.00 Feb 22, 2005 page 901 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.10.2 Software Protection Software protection can be implemented by setting the SWE bit in FLMCR1, erase block register 1 (EBR1), erase block register 2 (EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P or E bit in flash memory control register 1 (FLMCR1), does not cause a transition to program mode or erase mode (See table 21C-12). Table 21C-12 Software Protection Functions Item SWE bit protection Description * Program Erase Yes Setting bit SWE in FLMCR1 to 0 will place Yes area on-chip flash memory in the program/ erase-protected state (Execute the program in the on-chip RAM, external memory). Erase protection can be set for individual blocks by settings in erase block register 1 (EBR1) and erase block register 2 (EBR2). Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state. Yes Setting the RAMS bit to 1 in the RAM emulation register (RAMER) places all blocks in the program/erase-protected state. -- Block specification protection * Yes * Emulation protection * Yes Rev. 6.00 Feb 22, 2005 page 902 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.10.3 Error Protection In error protection, an error is detected when chip runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the chip malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. FLER bit setting conditions are as follows: 1. When the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) 2. Immediately after exception handling (excluding a reset) during programming/erasing 3. When a SLEEP instruction (including software standby) is executed during programming/erasing Error protection is released only by a reset and in hardware standby mode. Rev. 6.00 Feb 22, 2005 page 903 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) Figure 21C-14 shows the flash memory state transition diagram. Program mode Erase mode RD VF PR ER FLER = 0 RES = 0 or HSTBY = 0 Reset or standby (hardware protection) RD VF PR ER FLER = 0 Error occurrence (software standby) Error occurrence RES = 0 or HSTBY = 0 RES = 0 or HSTBY = 0 FLMCR1, FLMCR2, EBR1, EBR2 initialization state Error protection mode RD VF PR ER FLER = 1 Software standby mode Software standby mode release Error protection mode (software standby) RD VF PR ER FLER = 1 FLMCR1, FLMCR2, (except bit FLER) EBR1, EBR2 initialization state Legend: RD: Memory read possible VF: Verify-read possible PR: Programming possible ER: Erasing possible RD: VF: PR: ER: Memory read not possible Verify-read not possible Programming not possible Erasing not possible Figure 21C-14 Flash Memory State Transitions Rev. 6.00 Feb 22, 2005 page 904 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.11 Flash Memory Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses cannot be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 21C-15 shows an example of emulation of real-time flash memory programming. Start of emulation program Set RAMER Write tuning data to overlap RAM Execute application program No Tuning OK? Yes Clear RAMER Write to flash memory emulation block End of emulation program Figure 21C-15 Flowchart for Flash Memory Emulation in RAM Rev. 6.00 Feb 22, 2005 page 905 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) This area can be accessed from both the RAM area and flash memory area H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 EB1 EB2 EB3 EB4 EB5 EB6 EB7 EB0 Flash memory EB8 to EB10 On-chip RAM H'FFD800 H'FFE7FF H'FFEFBF H'2FFFF H8S/2635 Figure 21C-16 Example of RAM Overlap Operation Example in which Flash Memory Block Area EB0 is Overlapped 1. Set bits RAMS, RAM2 to RAM0 in RAMER to 1, 0, 0, 0, to overlap part of RAM onto the area (EB0) for which real-time programming is required. 2. Real-time programming is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space (EB0). Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of RAM2 to RAM0 (emulation protection). In this state, setting the P or E bit in flash memory control register 1 (FLMCR1), will not cause a transition to program mode or erase mode. When actually programming or erasing a flash memory area, the RAMS bit should be cleared to 0. 2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. 3. Block area EB0 contains the vector table. When performing RAM emulation, the vector table is needed in the overlap RAM. Rev. 6.00 Feb 22, 2005 page 906 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.12 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI interrupt is disabled when flash memory is being programmed or erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode*1, to give priority to the program or erase operation. There are three reasons for this: 1. Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. In the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly*2, possibly resulting in MCU runaway. 3. If interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. For these reasons, in on-board programming mode alone there are conditions for disabling interrupt, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or MCU operation. All requests, including NMI interrupt, must therefore be restricted inside and outside the MCU when programming or erasing flash memory. NMI interrupt is also disabled in the error-protection state while the P or E bit remains set in FLMCR1. Notes: 1. Interrupt requests must be disabled inside and outside the MCU until the programming control program has completed programming. 2. The vector may not be read correctly in this case for the following two reasons: * If flash memory is read while being programmed or erased (while the P or E bit is set in FLMCR1), correct read data will not be obtained (undetermined values will be returned). * If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. 21C.13 Flash Memory Programmer Mode Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, flash memory read mode, auto-program mode, autoerase mode, and status read mode are supported. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. In programmer mode, set the mode pins to programmer mode (see table 21C-13) and input a 12 MHz input clock. Rev. 6.00 Feb 22, 2005 page 907 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) Table 21C-13 shows the pin settings for programmer mode. Table 21C-13 Pin Names Mode pins: MD2, MD1, MD0 Mode setting pins: PF0, P16, P14 FWE pin pin Programmer Mode Pin Settings Settings Low level input to MD2, MD1, and MD0. High level input to PF0, low level input to P16 and P14 High level input (in auto-program and auto-erase modes) Reset circuit Oscillator circuit Internal voltage step-down circuit 21C.13.1 Socket Adapter and Memory Map In programmer mode in which the PROM writer is used, reading from memory (verification), writing, and initializing the flash memory (erasing all of its contents) are enabled. At this time, a dedicated conversion socket adapter must be attached to a general-purpose PROM writer. Table 21C-14 shows the types of the socket adapters. For programmer mode on this LSI, one of the socket adapters listed in table 21C-14 should be used. Table 21C-14 Product Name HD64F2635F Rev. 6.00 Feb 22, 2005 page 908 of 1484 REJ09B0103-0600 SER VCL XTAL, EXTAL, PLLCAP, PLLVSS pins Type of Socket Adapter Package Type 128 pin QFP (FP-128B) Socket Adapter Type ME2636ESHF1H HF2636Q128D4001 Manufacturer Minato Electronics Inc. Data I/O Japan Corporation Section 21C ROM (H8S/2635 Group) Addresses in MCU mode H'000000 Addresses in programmer mode H'00000 On-chip ROM space 192 kbytes (H8S/2635) H'02FFFF H'2FFFF Figure 21C-17 On-Chip ROM Memory Map 21C.13.2 Programmer Mode Operation Table 21C-15 shows how the different operating modes are set when using programmer mode, and table 21C-16 lists the commands used in programmer mode. Details of each mode are given below. * Memory Read Mode Memory read mode supports byte reads. * Auto-Program Mode Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. * Auto-Erase Mode Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-programming. * Status Read Mode Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the I/O6 signal. In status read mode, error information is output if an error occurs. Rev. 6.00 Feb 22, 2005 page 909 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) Table 21C-15 Settings for Various Operating Modes in Programmer Mode Pin Names Read Output disable Command write Chip disable*1 H or L H or L H or L*3 H or L L L H L X L L H H H X H Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2. Ain indicates that there is also address input in auto-program mode. 3. For command writes in auto-program and auto-erase modes, input a high level to the FWE pin. Table 21C-16 Programmer Mode Commands Number of Cycles 1+n 129 2 2 1st Cycle Mode Write Write Write Write Address X X X X Data H'00 H'40 H'20 H'71 Mode Read Write Write Write 2nd Cycle Address RA WA X X Data Dout Din H'20 H'71 Command Name Memory read mode Auto-program mode Auto-erase mode Status read mode Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n). 21C.13.3 Memory Read Mode 1. After completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. When reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. 2. In memory read mode, command writes can be performed in the same way as in the command wait state. 3. Once memory read mode has been entered, consecutive reads can be performed. 4. After powering on, memory read mode is entered. Rev. 6.00 Feb 22, 2005 page 910 of 1484 REJ09B0103-0600 EW EO EC Mode FWE I/O7 to I/O0 Data output Hi-Z Data input Hi-Z A18 to A0 Ain*2 X Ain*2 X Section 21C ROM (H8S/2635 Group) Table 21C-17 AC Characteristics in Transition to Memory Read Mode Conditions: VCC = 5.0 V 0.5 V, VSS = 0 V, Ta = 25C 5C Item Command write cycle hold time setup time Symbol tnxtc tceh tces tdh tds twep tr tf Min. 20 0 0 50 50 70 -- -- Max. -- -- -- -- -- -- 30 30 Unit s ns ns ns ns ns ns ns EW EW EC EC Data hold time Data setup time Write pulse width rise time fall time Command write A18 to A0 tces CE tceh tnxtc Memory read mode Address stable OE tf WE twep tr tds I/O7 to I/O0 tdh Note: Data is latched on the rising edge of WE. Figure 21C-18 Timing Waveforms for Memory Read after Memory Write Rev. 6.00 Feb 22, 2005 page 911 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) Table 21C-18 AC Characteristics in Transition from Memory Read Mode to Another Mode Conditions: VCC = 5.0 V 0.5 V, VSS = 0 V, Ta = 25C 5C Item Command write cycle hold time setup time Symbol tnxtc tceh tces tdh tds twep tr tf Min. 20 0 0 50 50 70 -- -- Max. -- -- -- -- -- -- 30 30 Unit s ns ns ns ns ns ns ns EW EW EC EC Data hold time Data setup time Write pulse width rise time fall time Memory read mode A18 to A0 Address stable tnxtc CE Other mode command write tces tceh OE tf WE twep tr tds I/O7 to I/O0 Note: Do not enable WE and OE at the same time. tdh Figure 21C-19 Timing Waveforms in Transition from Memory Read Mode to Another Mode Rev. 6.00 Feb 22, 2005 page 912 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) Table 21C-19 AC Characteristics in Memory Read Mode Conditions: VCC = 5.0 V 0.5 V, VSS = 0 V, Ta = 25C 5C Item Access time output delay time output delay time Symbol tacc tce toe tdf toh Min. -- -- -- -- 5 Max. 20 150 150 100 -- Unit s ns ns ns ns A18 to A0 CE Address stable tce toe OE WE VIH tacc toh I/O7 to I/O0 tdf tacc toh EO EC Figure 21C-21 and EO EC EO EC Output disable delay time Data output hold time A18 to A0 Address stable Address stable CE OE WE I/O7 to I/O0 VIL VIL VIH tacc toh tacc toh Figure 21C-20 and Enable State Read Timing Waveforms Address stable tce toe tdf Clock System Read Timing Waveforms Rev. 6.00 Feb 22, 2005 page 913 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.13.4 Auto-Program Mode 1. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. 2. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. The lower 7 bits of the transfer address must be low. If a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. 4. Memory address transfer is performed in the second cycle (figure 21C-22). Do not perform transfer after the third cycle. 5. Do not perform a command write during a programming operation. 6. Perform one auto-program operation for a 128-byte block for each address. Two or more additional programming operations cannot be performed on a previously programmed address block. 7. Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-program operation end decision pin). 8. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling and . Rev. 6.00 Feb 22, 2005 page 914 of 1484 REJ09B0103-0600 EC EO Section 21C ROM (H8S/2635 Group) Table 21C-20 AC Characteristics in Auto-Program Mode Conditions: VCC = 5.0 V 0.5 V, VSS = 0 V, Ta = 25C 5C Item Command write cycle hold time setup time Symbol tnxtc tceh tces tdh tds twep twsts tspa tas tah twrite tpns tpnh tr tf Min. 20 0 0 50 50 70 1 -- 0 60 1 100 100 -- -- Max. -- -- -- -- -- -- -- 150 -- -- 3000 -- -- 30 30 Unit s ns ns ns ns ns ms ns ns ns ms ns ns ns ns EW EW EC EC Data hold time Data setup time Write pulse width Status polling start time Status polling access time Address setup time Address hold time Memory write time Write setup time Write end setup time rise time fall time FWE tpnh Address stable tpns tces tceh tnxtc tnxtc A18 to A0 CE OE tf twep tr tas tah Data transfer 1 to 128 bytes twsts tspa WE tds tdh twrite Write operation end decision signal I/O7 I/O6 I/O5 to I/O0 Write normal end decision signal H'40 H'00 Figure 21C-22 Auto-Program Mode Timing Waveforms Rev. 6.00 Feb 22, 2005 page 915 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.13.5 Auto-Erase Mode 1. Auto-erase mode supports only entire memory erasing. 2. Do not perform a command write during auto-erasing. 3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin). 4. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling and . Table 21C-21 AC Characteristics in Auto-Erase Mode Conditions: VCC = 5.0 V 0.5 V, VSS = 0 V, Ta = 25C 5C Item Command write cycle hold time setup time Symbol tnxtc tceh tces tdh tds twep tests tspa terase tens tenh tr tf Min. 20 0 0 50 50 70 1 -- 100 100 100 -- -- Max. -- -- -- -- -- -- -- 150 40000 -- -- 30 30 Unit s ns ns ns ns ns ms ns ms ns ns ns ns Data hold time Data setup time Write pulse width Status polling start time Status polling access time Memory erase time Erase setup time Erase end setup time rise time fall time Rev. 6.00 Feb 22, 2005 page 916 of 1484 REJ09B0103-0600 EC EO EW EW EC EC Section 21C ROM (H8S/2635 Group) FWE tenh A18 to A0 tens tces tceh tnxtc tnxtc CE OE tf twep tr tests tspa WE tds tdh terase Erase end decision signal I/O7 I/O6 I/O5 to I/O0 Erase normal end decision signal H'20 H'20 H'00 Figure 21C-23 Auto-Erase Mode Timing Waveforms Rev. 6.00 Feb 22, 2005 page 917 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.13.6 Status Read Mode 1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. The return code is retained until a command write other than a status read mode command write is executed. Table 21C-22 AC Characteristics in Status Read Mode Conditions: VCC = 5.0 V 0.5 V, VSS = 0 V, Ta = 25C 5C Item Read time after command write hold time setup time Symbol tnxtc tceh tces tdh tds twep toe tdf tce tr tf Min. 20 0 0 50 50 70 -- -- -- -- -- Max. -- -- -- -- -- -- 150 100 150 30 30 Unit s ns ns ns ns ns ns ns ns ns ns Rev. 6.00 Feb 22, 2005 page 918 of 1484 REJ09B0103-0600 EW EW EC EO EC EC Data hold time Data setup time Write pulse width output delay time output delay time rise time fall time Disable delay time A18 to A0 tces tceh tnxtc tces tceh tnxtc tnxtc CE tce OE tf twep tr tf twep tr toe WE tds tdh H'71 tds H'71 tdh tdf I/O7 to I/O0 Note: I/O2 and I/O3 are undefined. Figure 21C-24 Status Read Mode Timing Waveforms Section 21C ROM (H8S/2635 Group) Table 21C-23 Pin Name I/O7 Attribute Status Read Mode Return Commands I/O6 Command error I/O5 Programming error I/O4 Erase error I/O3 -- I/O2 -- I/O1 I/O0 Normal end decision ProgramEffective ming or address erase count error exceeded 0 0 Count Effective exceeded: 1 address Otherwise: 0 error: 1 Otherwise: 0 Initial value 0 Indications Normal end: 0 Abnormal end: 1 0 Command error: 1 0 0 0 0 -- ProgramErasing -- ming error: 1 Otherwise: 0 error: 1 Otherwise: 0 Otherwise: 0 Note: I/O2 and I/O3 are undefined. 21C.13.7 Status Polling 1. The I/O7 status polling flag indicates the operating status in auto-program/auto-erase mode. 2. The I/O6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase mode. Table 21C-24 Pin Name I/O7 I/O6 I/O0 to I/O5 Status Polling Output Truth Table During Internal Operation 0 0 0 Abnormal End 1 0 0 -- 0 1 0 Normal End 1 1 0 21C.13.8 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 21C-25 Item Standby release (oscillation stabilization time) Programmer mode setup time VCC hold time Stipulated Transition Times to Command Wait State Symbol tosc1 tbmv tdwn Min. 30 10 0 Max. -- -- -- Unit ms ms ms Rev. 6.00 Feb 22, 2005 page 919 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) tosc1 VCC tbmv Memory read mode Command Auto-program mode wait state Auto-erase mode Command wait state Normal/abnormal end decision tdwn RES FWE Note: When using other than the automatic write mode and automatic erase mode, drive the FWE input pin low. Figure 21C-25 Oscillation Stabilization Time, Boot Program Transfer Time, and Power-Down Sequence 21C.13.9 Notes on Memory Programming 1. When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. 2. When performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level. 2. Auto-programming should be performed once only on the same address block. Additional programming cannot be performed on previously programmed address blocks. Rev. 6.00 Feb 22, 2005 page 920 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.14 Flash Memory and Power-Down States In addition to its normal operating state, the flash memory has power-down states in which power consumption is reduced by halting part or all of the internal power supply circuitry. There are three flash memory operating states: (1) Normal operating mode: The flash memory can be read and written to. (2) Power-down mode: Part of the power supply circuitry is halted, and the flash memory can be read when the LSI is operating on the subclock. (3) Standby mode: All flash memory circuits are halted, and the flash memory cannot be read or written to. States (2) and (3) are flash memory power-down states. Table 21C-26 shows the correspondence between the operating states of the LSI and the flash memory. Table 21C-26 Flash Memory Operating States Flash Memory Operating State Normal mode (read/write) LSI Operating State High-speed mode Medium-speed mode Sleep mode Subactive mode Subsleep mode Watch mode Software standby mode Hardware standby mode When PDWND = 0: Power-down mode (read-only) When PDWND = 1: Normal mode (read-only) Standby mode Rev. 6.00 Feb 22, 2005 page 921 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) 21C.14.1 Notes on Power-Down States 1. When the flash memory is in a power-down state, part or all of the internal power supply circuitry is halted. Therefore, a power supply circuit stabilization period must be provided when returning to normal operation. When the flash memory returns to its normal operating state from a power-down state, bits STS2 to STS0 in SBYCR must be set to provide a wait time of at least 20 s (power supply stabilization time), even if an oscillation stabilization period is not necessary. 2. In a power-down state, FLMCR1, FLMCR2, EBR1, EBR2, RAMER, and FLPWCR cannot be read from or written to. 21C.15 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode, the RAM emulation function, and programmer mode are summarized below. Use the specified voltages and timing for programming and erasing: Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas microcomputer device type* with 256-kbyte on-chip flash memory. Only use the specified socket adapter. Failure to observe these points may result in damage to the device. Note: * The H8S/2635 is Renesas Technology microcomputer devices with 256 kbytes of on-chip flash memory. (The H8S/2635 has 192 kbytes of PROM. The area from H'30000 to H'3FFFF should be programmed as H'FF.) Powering on and off (see figures 21C-26 to 21C-28): Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low before turning off VCC. When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. Rev. 6.00 Feb 22, 2005 page 922 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) FWE application/disconnection (see figures 21C-26 to 21C-28): FWE application should be carried out when MCU operation is in a stable condition. If MCU operation is not stable, fix the FWE pin low and set the protection state. The following points must be observed concerning FWE application and disconnection to prevent unintentional programming or erasing of flash memory: * Apply FWE when the VCC voltage has stabilized within its rated voltage range. Apply FWE when oscillation has stabilized (after the elapse of the oscillation stabilization time). * In boot mode, apply and disconnect FWE during a reset. * In user program mode, FWE can be switched between high and low level regardless of the reset state. FWE input can also be switched during execution of a program in flash memory. * Do not apply FWE if program runaway has occurred. * Disconnect FWE only when the SWE, ESU, PSU, EV, PV, P, and E bits in FLMCR1 are cleared. Make sure that the SWE, ESU, PSU, EV, PV, P, and E bits are not set by mistake when applying or disconnecting FWE. Do not apply a constant high level to the FWE pin: Apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. Use the recommended algorithm when programming and erasing flash memory: The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. Do not set or clear the SWE bit during execution of a program in flash memory: Wait for at least 100 s after clearing the SWE bit before executing a program or reading data in flash memory. When the SWE bit is set, data in flash memory can be rewritten, but when SWE = 1, flash memory can only be read in program-verify or erase-verify mode. Access flash memory only for verify operations (verification during programming/erasing). Also, do not clear the SWE bit during programming, erasing, or verifying. Similarly, when using the RAM emulation function while a high level is being input to the FWE pin, the SWE bit must be cleared before executing a program or reading data in flash memory. Rev. 6.00 Feb 22, 2005 page 923 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) However, the RAM area overlapping flash memory space can be read and written to regardless of whether the SWE bit is set or cleared. Do not use interrupts while flash memory is being programmed or erased: All interrupt requests, including NMI, should be disabled during FWE application to give priority to program/erase operations. Do not perform additional programming. Erase the memory before reprogramming: In onboard programming, perform only one programming operation on a 128-byte programming unit block. In programmer mode, too, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. Before programming, check that the chip is correctly mounted in the PROM programmer: Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. Do not touch the socket adapter or chip during programming: Touching either of these can cause contact faults and write errors. Rev. 6.00 Feb 22, 2005 page 924 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) Wait time: x Programming/ erasing possible Wait time: 100 s tOSC1 VCC Min. 0 s FWE tMDS*3 Min. 0 s MD2 to MD0*1 tMDS*3 RES SWE set SWE bit SWE cleared Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-off by pulling the pins up or down. 2. See section 24.2.7, 24.3.7, and 24.4.7, Flash Memory Characteristics. 3. Mode programming setup time tMDS (min.) = 200 ns Figure 21C-26 Power-On/Off Timing (Boot Mode) Rev. 6.00 Feb 22, 2005 page 925 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) Wait time: x Programming/ erasing possible Wait time: 100 s tOSC1 VCC Min. 0 s FWE MD2 to MD0*1 tMDS*3 RES SWE set SWE bit SWE cleared Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-off by pulling the pins up or down. 2. See section 24.2.7, 24.3.7, and 24.4.7, Flash Memory Characteristics. 3. Mode programming setup time tMDS (min.) = 200 ns Figure 21C-27 Power-On/Off Timing (User Program Mode) Rev. 6.00 Feb 22, 2005 page 926 of 1484 REJ09B0103-0600 Section 21C ROM (H8S/2635 Group) Wait time: x Programming/erasing possible Wait time: 100 s Wait time: x Programming/erasing possible Wait time: 100 s Wait time: x Programming/erasing possible Programming/erasing possible Wait time: 100 s tOSC1 VCC Min. 0 s FWE tMDS tMDS*2 MD2 to MD0 tMDS tRESW RES SWE set Mode change*1 Boot mode SWE cleared Mode User change*1 mode User program mode User mode User program mode SWE bit Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*3 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried out by means of RES input. The state of ports with multiplexed address functions and bus control output pins (AS, RD, WR) will change during this switchover interval (the interval during which the RES pin input is low), and therefore these pins should not be used as output signals during this time. 2. When making a transition from boot mode to another mode, a mode programming setup time tMDS (min.) of 200 ns is necessary with respect to RES clearance timing. 3. See section 24.2.7, 24.3.7, and 24.4.7, Flash Memory Characteristics. Figure 21C-28 Mode Transition Timing (Example: Boot Mode User Mode User Program Mode) Rev. 6.00 Feb 22, 2005 page 927 of 1484 REJ09B0103-0600 Wait time: x Wait time: 100 s Section 21C ROM (H8S/2635 Group) 21C.16 Note on Switching from F-ZTAT Version to Mask ROM Version The mask ROM version does not have the internal registers for flash memory control that are provided in the F-ZTAT version. Table 21C-24 lists the registers that are present in the F-ZTAT version but not in the mask ROM version. If a register listed in table 21C-24 is read in the mask ROM version, an undefined value will be returned. Therefore, if application software developed on the F-ZTAT version is switched to a mask ROM version product, it must be modified to ensure that the registers in table 21C-27 have no effect. Table 21C-27 Register Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Registers Present in F-ZTAT Version but Absent in Mask ROM Version Abbreviation FLMCR1 FLMCR2 EBR1 EBR2 RAMER Address H'FFA8 H'FFA9 H'FFAA H'FFAB H'FEDB Rev. 6.00 Feb 22, 2005 page 928 of 1484 REJ09B0103-0600 Section 22A Clock Pulse Generator (H8S/2636 Group, H8S/2638 Group, H8S/2630 Group) Section 22A Clock Pulse Generator (H8S/2636 Group, H8S/2638 Group, H8S/2630 Group) 22A.1 Overview The chip has a built-in clock pulse generator (CPG) that generates the system clock (), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator, PLL (phase-locked loop) circuit, clock selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock oscillator, and waveform shaping circuit. The frequency can be changed by means of the PLL circuit in the CPG. Frequency changes are performed by software by means of settings in the system clock control register (SCKCR) and low-power control register (LPWRCR). 22A.1.1 Block Diagram Figure 22A-1 shows a block diagram of the clock pulse generator. LPWRCR STC1, STC0 SCKCR SCK2 to SCK0 EXTAL XTAL System clock oscillator PLL circuit (x1, x2, x4) Clock selection circuit SUB Mediumspeed clock divider /2 to /32 Bus master clock selection circuit OSC1* OSC2* Subclock oscillator Waveform Generation Circuit System clock Internal clock to to pin supporting modules Bus master clock to CPU and DTC WDT1 count clock Legend: LPWRCR: Low-power control register SCKCR: System clock control register Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions only. These functions cannot be used with the other versions. See section 22A.7, Subclock Oscillator, for the method of fixing pins OSC1 and OSC2. Figure 22A-1 Block Diagram of Clock Pulse Generator Rev. 6.00 Feb 22, 2005 page 929 of 1484 REJ09B0103-0600 Section 22A Clock Pulse Generator (H8S/2636 Group, H8S/2638 Group, H8S/2630 Group) 22A.1.2 Register Configuration The clock pulse generator is controlled by SCKCR and LPWRCR. Table 22A-1 shows the register configuration. Table 22A-1 Clock Pulse Generator Register Name System clock control register Low-power control register Abbreviation SCKCR LPWRCR R/W R/W R/W Initial Value H'00 H'00 Address* H'FDE6 H'FDEC Note:* Lower 16 bits of the address. 22A.2 Register Descriptions 22A.2.1 System Clock Control Register (SCKCR) Bit : 7 PSTOP Initial value: R/W : 0 R/W 3/4 3/4 0 6 3/4 3/4 0 5 3/4 3/4 0 4 3 STCS 0 R/W 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W SCKCR is an 8-bit readable/writable register that performs clock output control and mediumspeed mode control, selection of operation when the PLL circuit frequency multiplication factor is changed, and medium-speed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7-- Clock Output Disable (PSTOP): In combination with the DDR of the applicable port, this bit controls output. See section 23A.8, 23B.12, Clock Output Disable Function for details. Description Bit 7 PSTOP 0 1 Normal Operating State output (initial value) Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance Sleep Mode output Fixed high Bits 6 to 4--Reserved: These bits are always read as 0 and cannot be modified. Rev. 6.00 Feb 22, 2005 page 930 of 1484 REJ09B0103-0600 Section 22A Clock Pulse Generator (H8S/2636 Group, H8S/2638 Group, H8S/2630 Group) Bit 3--Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation when the PLL circuit frequency multiplication factor is changed. Bit 3 STCS 0 1 Description Specified multiplication factor is valid after transition to software standby mode, watch mode*, and subactive mode* (Initial value) Specified multiplication factor is valid immediately after STC bits are rewritten Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions only. These functions cannot be used with the other versions. Bits 2 to 0--System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master clock. Bit 2 SCK2 0 Bit 1 SCK1 0 1 1 0 1 Bit 0 SCK0 0 1 0 1 0 1 -- Description Bus master is in high-speed mode Medium-speed clock is /2 Medium-speed clock is /4 Medium-speed clock is /8 Medium-speed clock is /16 Medium-speed clock is /32 -- (Initial value) 22A.2.2 Low-Power Control Register (LPWRCR) Bit Initial value Read/Write 7 DTON 0 R/W 6 LSON 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W NESEL SUBSTP RFCUT 3/4 0 R/W 2 1 STC1 0 R/W 0 STC0 0 R/W LPWRCR is an 8-bit readable/writable register that performs power-down mode control. The following pertains to bits 1 and 0. For details of the other bits, see section 23A.2.3, 23B.2.3, Low Power Control Register (LPWRCR). LPWRCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Rev. 6.00 Feb 22, 2005 page 931 of 1484 REJ09B0103-0600 Section 22A Clock Pulse Generator (H8S/2636 Group, H8S/2638 Group, H8S/2630 Group) Bits 1 and 0--Frequency Multiplication Factor (STC1, STC0): The STC bits specify the frequency multiplication factor of the PLL circuit. Bit 1 STC1 0 1 Bit 0 STC0 0 1 0 1 Description x1 x2 x4 Setting prohibited (Initial value) Note: The multiplication factor should be set so that the clock frequency following multiplication does not exceed the maximum operating frequency of the LSI. It is possible to reduce power consumption and noise by using a setting of PLL x4 for this function and lowering the external clock frequency. 22A.3 Oscillator Clock pulses may be supplied either by connecting a crystal oscillator or inputting an external clock. In the latter case, the input clock frequency should be between 4 MHz and 20 MHz. 22A.3.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 22A-2. Select the damping resistance Rd according to table 22A-2. An AT-cut parallel-resonance crystal should be used. CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22pF Figure 22A-2 Connection of Crystal Resonator (Example) Table 22A-2 Damping Resistance Value Frequency (MHz) Rd () 4 500 8 200 12 0 16 0 20 0 Rev. 6.00 Feb 22, 2005 page 932 of 1484 REJ09B0103-0600 Section 22A Clock Pulse Generator (H8S/2636 Group, H8S/2638 Group, H8S/2630 Group) Crystal Resonator: Figure 22A-3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 22A-3. The crystal resonator frequency should not exceed 20 MHz. CL L XTAL Rs EXTAL AT-cut parallel-resonance type C0 Figure 22A-3 Crystal Resonator Equivalent Circuit Table 22A-3 Crystal Resonator Parameters Frequency (MHz) RS max () C0 max (pF) 4 120 7 8 80 7 12 60 7 16 50 7 20 40 7 Note on Board Design: When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 22A-4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Avoid CL2 XTAL EXTAL CL1 Signal A Signal B Chip Figure 22A-4 Example of Incorrect Board Design Rev. 6.00 Feb 22, 2005 page 933 of 1484 REJ09B0103-0600 Section 22A Clock Pulse Generator (H8S/2636 Group, H8S/2638 Group, H8S/2630 Group) External circuitry such as that shown below is recommended around the PLL. R1: 3 kW PLLCAP C1: 470 pF PLLVSS VCC CB: 0.1 mF* VSS (Values are preliminary recommended values.) Note: * CB is laminated ceramic capacitors. Figure 22A-5 Points for Attention when Using PLL Oscillation Circuit Place oscillation stabilization capacitor C1 and resistor R1 close to the PLLCAP pin, and ensure that no other signal lines cross this line. Supply the C1 ground from PLLVSS. Separate PLLVSS from the other VCC and VSS lines at the board power supply source, and be sure to insert bypass capacitors CB close to the pins. Rev. 6.00 Feb 22, 2005 page 934 of 1484 REJ09B0103-0600 Section 22A Clock Pulse Generator (H8S/2636 Group, H8S/2638 Group, H8S/2630 Group) 22A.3.2 External Clock Input Circuit Configuration An external clock signal can be input as shown in the examples in figure 22A-6. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode. In this case, the input clock frequency should be between 4 MHz and 20 MHz. EXTAL XTAL Open External clock input (a) XTAL pin left open EXTAL XTAL External clock input (b) Complementary clock input at XTAL pin Figure 22A-6 External Clock Input (Examples) Rev. 6.00 Feb 22, 2005 page 935 of 1484 REJ09B0103-0600 Section 22A Clock Pulse Generator (H8S/2636 Group, H8S/2638 Group, H8S/2630 Group) External Clock Table 22A-4 and figure 22A-7 show the input conditions for the external clock. Table 22A-4 External Clock Input Conditions VCC = 5.0 V 10% Item External clock input low pulse width External clock input high pulse width External clock rise time External clock fall time Symbol tEXL tEXH tEXr tEXf Min. 15 15 -- -- Max. -- -- 5 5 Unit ns ns ns ns Test Conditions Figure 22A-7 tEXH tEXL EXTAL VCC 0.5 tEXr tEXf Figure 22A-7 External Clock Input Timing Rev. 6.00 Feb 22, 2005 page 936 of 1484 REJ09B0103-0600 Section 22A Clock Pulse Generator (H8S/2636 Group, H8S/2638 Group, H8S/2630 Group) 22A.4 PLL Circuit The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 1, 2, or 4. The multiplication factor is set with the STC bits in SCKCR. The phase of the rising edge of the internal clock is controlled so as to match that at the EXTAL pin. When the multiplication factor of the PLL circuit is changed, the operation varies according to the setting of the STCS bit in SCKCR. When STCS = 0 (initial value), the setting becomes valid after a transition to software standby mode, watch mode*, or subactive mode*. The transition time count is performed in accordance with the setting of bits STS2 to STS0 in SBYCR. [1] The initial PLL circuit multiplication factor is 1. [2] A value is set in bits STS2 to STS0 to give the specified transition time. [3] The target value is set in STC1 and STC0, and a transition is made to software standby mode, watch mode*, or subactive mode*. [4] The clock pulse generator stops and the value set in STC1 and STC0 becomes valid. [5] Software standby mode, watch mode*, or subactive mode* is cleared, and a transition time is secured in accordance with the setting in STS2 to STS0. [6] After the set transition time has elapsed, the LSI resumes operation using the target multiplication factor. If a PC break is set for the SLEEP instruction that causes a transition to software standby mode in [1], software standby mode is entered and break exception handling is executed after the oscillation stabilization time. In this case, the instruction following the SLEEP instruction is executed after execution of the RTE instruction. When STCS = 1, the LSI operates on the changed multiplication factor immediately after bits STC1 and STC0 are rewritten. Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions only. These functions cannot be used with the other versions. Rev. 6.00 Feb 22, 2005 page 937 of 1484 REJ09B0103-0600 Section 22A Clock Pulse Generator (H8S/2636 Group, H8S/2638 Group, H8S/2630 Group) 22A.5 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock to generate /2, /4, /8, /16, and /32. 22A.6 Bus Master Clock Selection Circuit The bus master clock selection circuit selects the system clock () or one of the medium-speed clocks (/2, /4, or /8, /16, and /32) to be supplied to the bus master, according to the settings of the SCK2 to SCK0 bits in SCKCR. 22A.7 Subclock Oscillator Connecting 32.768kHz Quartz Oscillator (U Mask, W Mask): To supply a clock to the subclock divider, connect a 32.768kHz quartz oscillator, as shown in figure 22A-8. See section 22A.3.1, "Notes on Board Design" for notes on connecting quartz oscillators. C1 OSC1 C2 OSC2 C1=C2=15pF (typ) Figure 22A-8 Example Connection of 32.768kHz Quartz Oscillator Figure 22A-9 shows the equivalence circuit for a 32.768kHz oscillator. Ls Cs Rs OSC1 Co OSC2 Cs = 1.5 pF (typ.) Rs = 14 k9 (typ.) fw = 32.768 kHz Figure 22A-9 Equivalence Circuit for 32.768kHz Oscillator Rev. 6.00 Feb 22, 2005 page 938 of 1484 REJ09B0103-0600 Section 22A Clock Pulse Generator (H8S/2636 Group, H8S/2638 Group, H8S/2630 Group) Handling Pins when Subclock not Required: If no subclock is required, connect the OSC1 pin to VSS and leave OSC2 open, as shown in figure 22A-10. OSC1 OSC2 Open Figure 22A-10 Pin Handling when Subclock not Required 22A.8 Subclock Waveform Generation Circuit To eliminate noise from the subclock input to OSCI, the subclock is sampled using the dividing clock . The sampling frequency is set using the NESEL bit of LPWRCR. For details, see section 23A.2.3, 23B.2.3, Low Power Control Register (LPWRCR). No sampling is performed in subactive mode*, subsleep mode*, or watch mode*. Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions only. These functions cannot be used with the other versions. 22A.9 Note on Crystal Resonator Since various characteristics related to the crystal resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, for both the mask versions and F-ZTAT versions, using the resonator connection examples shown in this section as a guide. As the resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. Rev. 6.00 Feb 22, 2005 page 939 of 1484 REJ09B0103-0600 Section 22A Clock Pulse Generator (H8S/2636 Group, H8S/2638 Group, H8S/2630 Group) Rev. 6.00 Feb 22, 2005 page 940 of 1484 REJ09B0103-0600 Section 22B Clock Pulse Generator (H8S/2639 Group, H8S/2635 Group) Section 22B Clock Pulse Generator (H8S/2639 Group, H8S/2635 Group) 22B.1 Overview The chip has a built-in clock pulse generator (CPG) that generates the system clock (), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator, PLL (phase-locked loop) circuit, system clock selection circuit, medium-speed clock divider, bus master clock selection circuit, and subclock divider. The frequency can be changed by means of the PLL circuit in the CPG. Frequency changes are performed by software by means of settings in the system clock control register (SCKCR) and low-power control register (LPWRCR). 22B.1.1 Block Diagram Figure 22B-1 shows a block diagram of the clock pulse generator. LPWRCR STC1, STC0 SCKCR SCK2 to SCK0 EXTAL Clock oscillator XTAL PLL circuit (x1, x2, x4) System clock selection circuit SUB Mediumspeed clock divider /2 to /32 Bus master clock selection circuit Subclock divider (1/128) System clock Internal clock to to pin supporting modules Bus master clock to CPU and DTC WDT1 count clock Legend: LPWRCR: Low-power control register SCKCR: System clock control register Figure 22B-1 Block Diagram of Clock Pulse Generator Rev. 6.00 Feb 22, 2005 page 941 of 1484 REJ09B0103-0600 Section 22B Clock Pulse Generator (H8S/2639 Group, H8S/2635 Group) 22B.1.2 Register Configuration The clock pulse generator is controlled by SCKCR and LPWRCR. Table 22B-1 shows the register configuration. Table 22B-1 Clock Pulse Generator Register Name System clock control register Low-power control register Abbreviation SCKCR LPWRCR R/W R/W R/W Initial Value H'00 H'00 Address* H'FDE6 H'FDEC Note:* Lower 16 bits of the address. 22B.2 Register Descriptions 22B.2.1 System Clock Control Register (SCKCR) Bit : 7 PSTOP Initial value: R/W : 0 R/W 3/4 3/4 0 6 3/4 3/4 0 5 3/4 3/4 0 4 3 STCS 0 R/W 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W SCKCR is an 8-bit readable/writable register that performs clock output control and mediumspeed mode control, selection of operation when the PLL circuit frequency multiplication factor is changed, and medium-speed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7-- Clock Output Disable (PSTOP): In combination with the DDR of the applicable port, this bit controls output. See section 23B.12, Clock Output Disable Function for details. Description Bit 7 PSTOP 0 1 Normal Operating State output (initial value) Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance Sleep Mode output Fixed high Bits 6 to 4--Reserved: These bits are always read as 0 and cannot be modified. Rev. 6.00 Feb 22, 2005 page 942 of 1484 REJ09B0103-0600 Section 22B Clock Pulse Generator (H8S/2639 Group, H8S/2635 Group) Bit 3--Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation when the PLL circuit frequency multiplication factor is changed. Bit 3 STCS 0 1 Description Specified multiplication factor is valid after transition to software standby mode, watch mode, and subactive mode (Initial value) Specified multiplication factor is valid immediately after STC bits are rewritten Bits 2 to 0--System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master clock. Bit 2 SCK2 0 Bit 1 SCK1 0 1 1 0 1 Bit 0 SCK0 0 1 0 1 0 1 -- Description Bus master is in high-speed mode Medium-speed clock is /2 Medium-speed clock is /4 Medium-speed clock is /8 Medium-speed clock is /16 Medium-speed clock is /32 -- (Initial value) 22B.2.2 Low-Power Control Register (LPWRCR) Bit : 7 DTON Initial value : R/W : 0 R/W 6 LSON 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W NESEL SUBSTP RFCUT 3/4 0 R/W 2 1 STC1 0 R/W 0 STC0 0 R/W LPWRCR is an 8-bit readable/writable register that performs power-down mode control. The following pertains to bits 1 and 0. For details of the other bits, see section 23B.2.3, Low Power Control Register (LPWRCR). LPWRCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Rev. 6.00 Feb 22, 2005 page 943 of 1484 REJ09B0103-0600 Section 22B Clock Pulse Generator (H8S/2639 Group, H8S/2635 Group) Bits 1 and 0--Frequency Multiplication Factor (STC1, STC0): The STC bits specify the frequency multiplication factor of the PLL circuit. Bit 1 STC1 0 1 Bit 0 STC0 0 1 0 1 Description x1 x2 x4 Setting prohibited (Initial value) Note: A system clock frequency multiplied by the multiplication factor (STC1 and STC0) should not exceed the maximum operating frequency defined in section 24, Electrical Characteristics. 22B.3 Oscillator Clock pulses may be supplied either by connecting a crystal oscillator or inputting an external clock. In the latter case, the input clock frequency should be between 4 MHz and 5 MHz. 22B.3.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 22B-2. Select the damping resistance Rd according to table 22B-2. An AT-cut parallel-resonance crystal should be used. CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22pF Figure 22B-2 Connection of Crystal Resonator (Example) Table 22B-2 Damping Resistance Value Frequency (MHz) Rd () 4 500 5 200 Rev. 6.00 Feb 22, 2005 page 944 of 1484 REJ09B0103-0600 Section 22B Clock Pulse Generator (H8S/2639 Group, H8S/2635 Group) Crystal Resonator: Figure 22B-3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 18-3. The crystal resonator frequency should not exceed 5 MHz. CL L XTAL Rs EXTAL AT-cut parallel-resonance type C0 Figure 22B-3 Crystal Resonator Equivalent Circuit Table 22B-3 Crystal Resonator Parameters Frequency (MHz) RS max () C0 max (pF) 4 120 7 5 80 7 Note on Board Design: When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 22B-4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Avoid CL2 XTAL EXTAL CL1 Signal A Signal B Chip Figure 22B-4 Example of Incorrect Board Design Rev. 6.00 Feb 22, 2005 page 945 of 1484 REJ09B0103-0600 Section 22B Clock Pulse Generator (H8S/2639 Group, H8S/2635 Group) External circuitry such as that shown below is recommended around the PLL. R1: 3 kW PLLCAP C1: 470 pF PLLVSS VCC CB: 0.1 mF* VSS (Values are preliminary recommended values.) Note: * CB is laminated ceramic capacitors. Figure 22B-5 Points for Attention when Using PLL Oscillation Circuit Place oscillation stabilization capacitor C1 and resistor R1 close to the PLLCAP pin, and ensure that no other signal lines cross this line. Supply the C1 ground from PLLVSS. Separate PLLVSS from the other VCC and VSS lines at the board power supply source, and be sure to insert bypass capacitors CB close to the pins. Rev. 6.00 Feb 22, 2005 page 946 of 1484 REJ09B0103-0600 Section 22B Clock Pulse Generator (H8S/2639 Group, H8S/2635 Group) 22B.3.2 External Clock Input Circuit Configuration An external clock signal can be input as shown in the examples in figure 22B-6. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode. In this case, the input clock frequency should be between 4 MHz and 5 MHz. EXTAL XTAL Open External clock input (a) XTAL pin left open EXTAL XTAL External clock input (b) Complementary clock input at XTAL pin* Note: * In the case of the H8S/2635 Group, do not input a complementary clock to the XTAL pin. Figure 22B-6 External Clock Input (Examples) Rev. 6.00 Feb 22, 2005 page 947 of 1484 REJ09B0103-0600 Section 22B Clock Pulse Generator (H8S/2639 Group, H8S/2635 Group) External Clock Table 22B-4 and figure 22B-7 show the input conditions for the external clock. Table 22B-4 External Clock Input Conditions VCC = 5.0 V 10% Item External clock input low pulse width External clock input high pulse width External clock rise time External clock fall time Symbol tEXL tEXH tEXr tEXf Min. 50 50 -- -- Max. -- -- 5 5 Unit ns ns ns ns Test Conditions Figure 22B-7 tEXH tEXL EXTAL VCC 0.5 tEXr tEXf Figure 22B-7 External Clock Input Timing Rev. 6.00 Feb 22, 2005 page 948 of 1484 REJ09B0103-0600 Section 22B Clock Pulse Generator (H8S/2639 Group, H8S/2635 Group) 22B.4 PLL Circuit The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 1, 2, or 4. The multiplication factor is set with the STC bits in SCKCR. The phase of the rising edge of the internal clock is controlled so as to match that at the EXTAL pin. When the multiplication factor of the PLL circuit is changed, the operation varies according to the setting of the STCS bit in SCKCR. When STCS = 0 (initial value), the setting becomes valid after a transition to software standby mode, watch mode, or subactive mode. The transition time count is performed in accordance with the setting of bits STS2 to STS0 in SBYCR. [1] The initial PLL circuit multiplication factor is 1. [2] A value is set in bits STS2 to STS0 to give the specified transition time. [3] The target value is set in STC1 and STC0, and a transition is made to software standby mode, watch mode, or subactive mode. [4] The clock pulse generator stops and the value set in STC1 and STC0 becomes valid. [5] Software standby mode, watch mode, or subactive mode is cleared, and a transition time is secured in accordance with the setting in STS2 to STS0. [6] After the set transition time has elapsed, the LSI resumes operation using the target multiplication factor. If a PC break is set for the SLEEP instruction that causes a transition to software standby mode in [1], software standby mode is entered and break exception handling is executed after the oscillation stabilization time. In this case, the instruction following the SLEEP instruction is executed after execution of the RTE instruction. When STCS = 1, the LSI operates on the changed multiplication factor immediately after bits STC1 and STC0 are rewritten. 22B.5 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock to generate /2, /4, /8, /16, and /32. 22B.6 Bus Master Clock Selection Circuit The bus master clock selection circuit selects the system clock () or one of the medium-speed clocks (/2, /4, or /8, /16, and /32) to be supplied to the bus master, according to the settings of the SCK2 to SCK0 bits in SCKCR. Rev. 6.00 Feb 22, 2005 page 949 of 1484 REJ09B0103-0600 Section 22B Clock Pulse Generator (H8S/2639 Group, H8S/2635 Group) 22B.7 Subclock Divider The subclock divider divides the input clock into 1/128 to generate SUB. 22B.8 Note on Resonator Since various characteristics related to the resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, for both the mask versions and F-ZTAT versions, using the resonator connection examples shown in this section as a guide. As the resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. Rev. 6.00 Feb 22, 2005 page 950 of 1484 REJ09B0103-0600 Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] Subclock functions are not available in the HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, and HD6432630F. 23A.1 Overview In addition to the normal program execution state, the chip has nine power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. The chip operating modes are as follows: (1) High-speed mode (2) Medium-speed mode (3) Sleep mode (4) Module stop mode (5) Software standby mode (6) Hardware standby mode (2) to (6) are low power dissipation states. Sleep mode is CPU states, medium-speed mode is a CPU and bus master state, and module stop mode is an internal peripheral function (including bus masters other than the CPU) state. Some of these states can be combined. After a reset, the LSI is in high-speed mode with modules other than the DTC in module stop mode. Notes: 1. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions only. These functions cannot be used with the other versions. 2. See section 22A.7, Subclock Oscillator, for the method of fixing pins OSC1 and OSC2 when not used. Rev. 6.00 Feb 22, 2005 page 951 of 1484 REJ09B0103-0600 Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] Table 23A-1 shows the internal state of the LSI in the respective modes. Table 23A-2 shows the conditions for shifting between the low power dissipation modes. Figure 23A-1 is a mode transition diagram. Table 23A-1 LSI Internal States in Each Mode Function System clock pulse generator CPU Instructions Registers NMI IRQ0 to IRQ5 WDT1 WDT0 DTC PBC TPU PPG D/A0, 1 SCI0 SCI1 SCI2 PWM A/D RAM I/O HCAN Functioning Functioning Functioning Functioning Functioning Functioning Functioning (DTC) Functioning Functioning Functioning Functioning Halted (reset) Retained Retained Halted (reset) Retained High impedance Halted (reset) Functioning Functioning Functioning Halted (reset) Halted (reset) Halted (reset) Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Halted (retained) Halted (retained) Halted (retained) Halted (retained) Halted (retained) Halted (retained) Halted (retained) Halted (retained) Halted (reset) Halted (reset) Halted (reset) Halted (reset) Halted (reset) HighSpeed Functioning Functioning MediumSpeed Functioning Sleep Functioning Module Stop Functioning Software Standby Halted Hardware Standby Halted Halted (undefined) Halted Medium-speed Halted operation (retained) Functioning Functioning High/medium- Halted speed (retained) operation Functioning Functioning External interrupts Peripheral functions Functioning Medium-speed Functioning operation Medium-speed Functioning operation Functioning Functioning Note: "Halted (retained)" means that internal register values are retained. The internal state is "operation suspended." "Halted (reset)" means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). Rev. 6.00 Feb 22, 2005 page 952 of 1484 REJ09B0103-0600 Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] Program-halted state STBY pin = Low Reset state Hardware standby mode STBY pin = High RES pin = Low RES pin = High Program execution state SLEEP command High-speed mode (main clock) All interrupt SCK2 to SCK0 = 0 SCK2 to SCK0 0 SLEEP command SSBY = 1, PSS = 0, LSON = 0 Software standby mode SSBY = 0, LSON = 0 Sleep mode (main clock) Medium-speed mode (main clock) External interrupt * : Transition after exception processing : Low power dissipation mode Note: When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. From any state except hardware standby mode, a transition to the reset state occurs when RES is driven low. From any state, a transition to hardware standby mode occurs when STBY is driven low. * NMI and IRQ0 to IRQ5 Figure 23A-1 Mode Transition Diagram Rev. 6.00 Feb 22, 2005 page 953 of 1484 REJ09B0103-0600 Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] Table 23A.2 Low Power Dissipation Mode Transition Conditions Status of Control Bit at Transition State after Transition Back from Low Power Mode Invoked by Interrupt High-speed/Mediumspeed -- High-speed/Mediumspeed -- -- -- -- -- -- -- -- -- High-speed -- -- -- Pre-Transition State SSBY PSS High-speed/ Medium-speed 0 0 1 1 1 1 1 1 Subactive 0 0 0 1 1 1 1 1 Legend: *: Don't care --: Do not set * * 0 0 1 1 1 1 0 1 1 0 1 1 1 1 State after Transition Invoked by SLEEP LSON DTON Command * * * * 0 0 1 1 * * * * 0 0 1 1 Sleep -- Software standby -- -- -- -- -- -- -- -- -- -- -- High-speed -- 0 1 0 1 0 1 0 1 * 0 1 * 0 1 0 1 Rev. 6.00 Feb 22, 2005 page 954 of 1484 REJ09B0103-0600 Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] 23A.1.1 Register Configuration Power-down modes are controlled by the SBYCR, SCKCR, LPWRCR, TCSR (WDT1), and MSTPCR registers. Table 23A-3 summarizes these registers. Table 23A-3 Power-Down Mode Registers Name Standby control register System clock control register Low-power control register Timer control/status register Module stop control register A, B, C, D Abbreviation SBYCR SCKCR LPWRCR TCSR MSTPCRA MSTPCRB MSTPCRC MSTPCRD Note: 1. Lower 16 bits of the address. R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'58 H'00 H'00 H'00 H'3F H'FF H'FF B'11****** Address*1 H'FDE4 H'FDE6 H'FDEC H'FFA2 H'FDE8 H'FDE9 H'FDEA H'FC60 Rev. 6.00 Feb 22, 2005 page 955 of 1484 REJ09B0103-0600 Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] 23A.2 Register Descriptions 23A.2.1 Standby Control Register (SBYCR) Bit : 7 SSBY Initial value : R/W : 0 R/W 6 STS2 1 R/W 5 STS1 0 R/W 4 STS0 1 R/W 3 OPE 1 R/W 3/4 3/4 0 2 3/4 3/4 0 1 3/4 3/4 0 0 SBYCR is an 8-bit readable/writable register that performs power-down mode control. SBYCR is initialized to H'58 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Software Standby (SSBY): When making a low power dissipation mode transition by executing the SLEEP instruction, the operating mode is determined in combination with other control bits. Note that the value of the SSBY bit does not change even when shifting between modes using interrupts. Bit 7 SSBY 0 1 Description Shifts to sleep mode when the SLEEP instruction is executed in high-speed mode or medium-speed mode. (Initial value) Shifts to software standby mode when the SLEEP instruction is executed in highspeed mode or medium-speed mode. Bits 6 to 4--Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the MCU wait time for clock stabilization when shifting to high-speed mode or medium-speed mode by using a specific interrupt or command to cancel software standby mode. With a quartz oscillator (Table 23A-5), select a wait time of 8ms (oscillation stabilization time) or more, depending on the operating frequency. With an external clock, select a standby time of 2 ms or more (PLL oscillator settling time), based on the operating frequency. Rev. 6.00 Feb 22, 2005 page 956 of 1484 REJ09B0103-0600 Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] Bit 6 STS2 0 Bit 5 STS1 0 1 1 0 1 Bit 4 STS0 0 1 0 1 0 1 0 1 Description Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states (Setting prohibited) (Initial value) Bit 3--Output Port Enable (OPE): This bit specifies whether the output of the address bus and , , ) is retained or set to high-impedance state in the bus control signals (AS, software standby mode. Bit 3 OPE 0 1 Description In software standby mode, address bus and bus control signals are high-impedance. In software standby mode, the output state of the address bus and bus control signals is retained. (Initial value) Bits 2 to 0--Reserved: These bits always return 0 when read, and cannot be written to. 23A.2.2 System Clock Control Register (SCKCR) Bit : 7 PSTOP Initial value : R/W : 0 R/W SCKCR is an 8-bit readable/writable register that performs clock output control and mediumspeed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Rev. 6.00 Feb 22, 2005 page 957 of 1484 REJ09B0103-0600 RWL RWH DR 3/4 3/4 0 6 3/4 3/4 0 5 3/4 3/4 0 4 3 STCS 0 R/W 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] Bit 7-- Clock Output Disable (PSTOP): In combination with the DDR of the applicable port, this bit controls output. See section 23A.8, Clock Output Disable Function for details. Description Bit 7 PSTOP 0 1 High-Speed Mode, Medium-Speed Mode output (initial value) Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance Sleep Mode output Fixed high Bits 6 to 4--Reserved: These bits are always read as 0 and cannot be modified. Bit 3--Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation when the PLL circuit frequency multiplication factor is changed. Bit 3 STCS 0 1 Description Specified multiplication factor is valid after transition to software standby mode (Initial value) Specified multiplication factor is valid immediately after STC bits are rewritten Bits 2 to 0--System Clock Select (SCK2 to SCK0): These bits select the bus master clock in high-speed mode, and medium-speed mode. Bit 2 SCK2 0 Bit 1 SCK1 0 1 1 0 1 Bit 0 SCK0 0 1 0 1 0 1 -- Description Bus master in high-speed mode Medium-speed clock is /2 Medium-speed clock is /4 Medium-speed clock is /8 Medium-speed clock is /16 Medium-speed clock is /32 -- (Initial value) Rev. 6.00 Feb 22, 2005 page 958 of 1484 REJ09B0103-0600 Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] 23A.2.3 Low-Power Control Register (LPWRCR) Bit : 7 DTON Initial value : R/W : 0 R/W 6 LSON 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W NESEL SUBSTP RFCUT 3/4 0 R/W 2 1 STC1 0 R/W 0 STC0 0 R/W The LPWRCR is an 8-bit read/write register that controls the low power dissipation modes. The LPWRCR is initialized to H'00 at a reset and when in hardware standby mode. It is not initialized in software standby mode. The following describes bits 7 to 2. For details of other bits, see section 22A.2.2, Low-Power Control Register (LPWRCR). Bits 7 to 3--Reserved: Bits DTON, LSON, NESEL, SUBSTP and RFCUT must always be written with 0, as this version does not support subclock operation. Bit 2--Reserved: Only write 0 to this bit. 23A.2.4 Timer Control/Status Register (TCSR) Bit : 7 OVF Initial value : R/W : 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 PSS 0 R/W 3 RST/NMI 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Note: * Only write 0 to clear the flag. TCSR is an 8-bit read/write register that selects the clock input to WDT1 TCNT and the mode. Here, we describe bit 4. For details of the other bits in this register, see section 12.2.2, Timer Control/Status Register (TCSR). The TCSR is initialized to H'00 at a reset and when in hardware standby mode. It is not initialized in software standby mode. Bit 4--Reserved: The PSS bit must always be written with 0 since no subclock functions are available in versions other than the U-mask and W-mask versions. Rev. 6.00 Feb 22, 2005 page 959 of 1484 REJ09B0103-0600 Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] 23A.2.5 Module Stop Control Register (MSTPCR) MSTPCRA Bit : 7 0 R/W 6 0 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W MSTPCRB Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : R/W MSTPCRC Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value : R/W : : : MSTPCRD Bit : 7 1 R/W 6 1 R/W 5 4 3 2 1 0 MSTPD7 MSTPD6 MSTPD5 MSTPD4 MSTPD3 MSTPD2 MSTPD1 MSTPD0 Initial value : R/W : Undefined Undefined Undefined Undefined Undefined Undefined -- -- -- -- -- -- MSTPCR, comprising four 8-bit readable/writable registers, performs module stop mode control. MSTPCRA to MSTPCRC are initialized to H'3FFFFF by a reset and in hardware standby mode. MSTPCRD is initialized to B'11****** by a reset and in hardware standby mode. They are not initialized in software standby mode. Rev. 6.00 Feb 22, 2005 page 960 of 1484 REJ09B0103-0600 Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] MSTPCRA/MSTPCRB/MSTPCRC Bits 7 to 0, MSTPCRD Bits 7 and 6--Module Stop (MSTPA7 to MSTPA0, MSTPB7 to MSTPB0, MSTPC7 to MSTPC0, MSTPD7 and MSTPD6): These bits specify module stop mode. See table 23A-4 for the method of selecting the on-chip peripheral functions. MSTPCRA/MSTPCRB/ MSTPCRC Bits 7 to 0, MSTPCRD Bits 7 and 6 MSTPA7 to MSTPA0, MSTPB7 to MSTPB0, MSTPC7 to MSTPC0, MSTPD7 and MSTPD6 Description 0 1 Module stop mode is cleared (initial value of MSTPA7 and MSTPA6) Module stop mode is set (initial value of MSTPA5-0, MSTPB7-0, MSTPC7-0, and MSTPC7, 6) Rev. 6.00 Feb 22, 2005 page 961 of 1484 REJ09B0103-0600 Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] 23A.3 Medium-Speed Mode In high-speed mode, when the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to medium-speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (/2, /4, /8, /16, or /32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (DTC) also operate in medium-speed mode. On-chip supporting modules other than the bus masters always operate on the high-speed clock (). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if /4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, and LSON bit in LPWRCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the SSBY bit = 1, LPWRCR LSON bit = 0, and TCSR (WDT1) PSS bit = 0, operation shifts to the software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. pin is set low and medium-speed mode is cancelled, operation shifts to the reset When the state. The same applies in the case of a reset caused by overflow of the watchdog timer. Figure 23A-2 shows the timing for transition to and clearance of medium-speed mode. Rev. 6.00 Feb 22, 2005 page 962 of 1484 REJ09B0103-0600 YBTS When the SER pin is driven low, a transition is made to hardware standby mode. Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] Medium-speed mode B, supporting module clock Bus master clock Internal address bus SBYCR SBYCR Internal write signal Figure 23A-2 Medium-Speed Mode Transition and Clearance Timing 23A.4 Sleep Mode 23A.4.1 Sleep Mode When the SLEEP instruction is executed when the SBYCR SSBY bit = 0 and the LPWRCR LSON bit = 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the contents of the CPUis internal registers are retained. Other supporting modules do not stop. 23A.4.2 Exiting Sleep Mode Exiting Sleep Mode by Interrupts: When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU. pin: Setting the pin level Low selects the reset state. After the Exiting Sleep Mode by stipulated reset input duration, driving the pin High starts the CPU performing reset exception processing. YBTS YBTS Exiting Sleep Mode by to hardware standby mode. Pin: When the pin level is driven Low, a transition is made Rev. 6.00 Feb 22, 2005 page 963 of 1484 REJ09B0103-0600 YBTS SER Sleep mode is exited by any interrupt, or signals at the , or pins. SER SER SER Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] 23A.5 Module Stop Mode 23A.5.1 Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 23A-4 shows MSTP bits and the corresponding on-chip supporting modules. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI, Motor control PWM, A/D converter and HCAN are retained. After reset clearance, all modules other than DTC are in module stop mode. When an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. Rev. 6.00 Feb 22, 2005 page 964 of 1484 REJ09B0103-0600 Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] Table 23A-4 MSTP Bits and Corresponding On-Chip Supporting Modules Register MSTPCRA Bit MSTPA6 MSTPA5 MSTPA3 MSTPA2 MSTPA1 MSTPA0*1 MSTPCRB MSTPB7 MSTPB6 MSTPB5 MSTPB4*2 MSTPB3*2 MSTPB0*1 MSTPCRC MSTPC4 MSTPC3 MSTPC2 MSTPC1*1 MSTPC0*1 MSTPCRD MSTPD7 MSTPD6*1 Notes: 1. MSTPA0, MSTPB0 and MSTPC1 to MSTPC0 and MSTPD6 are readable/writable bits with an initial value of 1. 2. The I2C bus interface is available as an option in the H8S/2638 and H8S/2630. In the H8S/2636, MSTB4 and MSTB3 are readable and writable bits that have 1 as their initial value. Motor control PWM (PWM) PC break controller (PBC) HCAN0 HCAN1 Serial communication interface 0 (SCI0) Serial communication interface 1 (SCI1) Serial communication interface 2 (SCI2) Module Data transfer controller (DTC) 16-bit timer pulse unit (TPU) Programmable pulse generator (PPG) D/A converter (channel 0, 1) A/D converter 23A.5.2 Usage Notes DTC Module Stop: Depending on the operating status of the DTC, the MSTPA7 and MSTPA6 bits may not be set to 1. Setting of the DTC module stop mode should be carried out only when the respective module is not activated. For details, refer to section 8, Data Transfer Controller (DTC). Rev. 6.00 Feb 22, 2005 page 965 of 1484 REJ09B0103-0600 Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Writing to MSTPCR: MSTPCR should only be written to by the CPU. 23A.6 Software Standby Mode 23A.6.1 Software Standby Mode A transition is made to software standby mode when the SLEEP instruction is executed when the SBYCR SSBY bit = 1 and the LPWRCR LSON bit = 0, and the TCSR (WDT1) PSS bit = 0. In this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of the CPU's internal registers, RAM data, and the states of on-chip supporting modules other than the SCI, A/D converter, Motor control, PWM, HCAN and I/O ports, are retained. Whether the address bus and bus control signals are placed in the high-impedance state. In this mode the oscillator stops, and therefore power dissipation is significantly reduced. 23A.6.2 Clearing Software Standby Mode * Clearing with an interrupt When an NMI or IRQ0 to IRQ5 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ5 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ5 is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. * Clearing with the pin When the pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the pin must be held low until clock oscillation stabilizes. When the pin goes high, the CPU begins reset exception handling. Rev. 6.00 Feb 22, 2005 page 966 of 1484 REJ09B0103-0600 5QRI 0QRI Software standby mode is cleared by an external interrupt (NMI pin, or pins pin or pin. means of the to ), or by SER SER YBTS SER SER SER Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] * Clearing with the pin When the pin is driven low, a transition is made to hardware standby mode. 23A.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time). Table 23A-5 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 23A-5 Oscillation Stabilization Time Settings STS2 STS1 STS0 Standby Time 0 0 0 1 1 0 1 1 0 1 0 1 0 1 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved 16 states (Setting prohibited) 20 MHz 0.41 0.82 1.6 3.3 6.6 -- 0.8 16 12 10 8 6 4 MHz MHz MHz MHz MHz MHz Unit 0.51 0.68 0.8 1.0 2.0 4.1 8.2 -- 1.0 1.3 2.7 5.5 1.6 3.3 6.6 1.0 2.0 4.1 8.2 1.3 2.7 5.5 2.0 4.1 8.2 ms : Recommended time setting Using a External Clock: The PLL circuit requires time to stabilize, so the standby time should be set to a value of 2 ms or more. YBTS YBTS 10.9 16.4 10.9 13.1 16.4 21.8 32.8 -- 1.3 -- 1.6 -- 2.0 -- 2.6 -- 4.0 s 13.1 16.4 21.8 26.2 32.8 43.6 65.6 Rev. 6.00 Feb 22, 2005 page 967 of 1484 REJ09B0103-0600 Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] 23A.6.4 Software Standby Mode Application Example Figure 23A-3 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin. Oscillator B NMI NMIEG SSBY NMI exception Software standby mode handling (power-down mode) NMIEG=1 SSBY=1 SLEEP instruction Oscillation stabilization time tOSC2 NMI exception handling Figure 23A-3 Software Standby Mode Application Example Rev. 6.00 Feb 22, 2005 page 968 of 1484 REJ09B0103-0600 Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] 23A.6.5 Usage Notes I/O Port Status: In software standby mode, I/O port states are retained. If the OPE bit is set to 1, the address bus and bus control signal output is also retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. Current Dissipation during Oscillation Stabilization Wait Period: Current dissipation increases during the oscillation stabilization wait period. Write Data Buffer Function: The write data buffer function and software standby mode cannot be used at the same time. When the write data buffer function is used, the WDBE bit in BCRL should be cleared to 0 to cancel the write data buffer function before entering software standby mode. Also check that external writes have finished, by reading external addresses, etc., before executing a SLEEP instruction to enter software standby mode. See section 7.7, Write Data Buffer Function, for details of the write data buffer function. 23A.7 Hardware Standby Mode 23A.7.1 Hardware Standby Mode In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before pin low. driving the Do not change the state of the mode pins (MD2 to MD0) while the chip is in hardware standby mode. Hardware standby mode is cleared by means of the pin and the pin. When the pin is driven high while the pin is low, the reset state is set and clock oscillation is started. Ensure that the pin is held low until the clock oscillator stabilizes (at least 8 ms--the oscillation stabilization time--when using a crystal oscillator). When the pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. Rev. 6.00 Feb 22, 2005 page 969 of 1484 REJ09B0103-0600 YBTS SER SER YBTS SER SER YBTS YBTS When the pin is driven low, a transition is made to hardware standby mode from any mode. Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] 23A.7.2 Hardware Standby Mode Timing Figure 23A-4 shows an example of hardware standby mode timing. pin is driven low after the pin has been driven low, a transition is made to When the hardware standby mode. Hardware standby mode is cleared by driving the pin high, pin from low to high. waiting for the oscillation stabilization time, then changing the Oscillator 4-5 56*; Oscillation stabilization time Figure 23A-4 Hardware Standby Mode Timing Rev. 6.00 Feb 22, 2005 page 970 of 1484 REJ09B0103-0600 YBTS SER SER YBTS Reset exception handling Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] 23A.8 Clock Output Disabling Function Output of the clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the clock stops at the end of the bus cycle, and output goes high. clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, clock output is disabled and input port mode is set. Table 23A-6 shows the state of the pin in each processing state. Using the on-chip PLL circuit to lower the oscillator frequency or prohibiting external clock output also have the effect of reducing unwanted electromagnetic interference*. Therefore, consideration should be given to these options when deciding on system board settings. Note: * Electromagnetic interference: EMI (Electro Magnetic Interference) Table 23A-6 Pin State in Each Processing State DDR PSTOP Hardware standby mode Software standby Sleep mode High-speed mode, medium-speed mode 0 -- High impedance High impedance High impedance High impedance 1 0 High impedance Fixed high output output 1 1 High impedance Fixed high Fixed high Fixed high Rev. 6.00 Feb 22, 2005 page 971 of 1484 REJ09B0103-0600 Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F, HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F] Rev. 6.00 Feb 22, 2005 page 972 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF, HD6432635F, HD64F2635F, HD6432634F] Note: The DTC, PBC, PPB, and D/A converter are not implemented in the H8S/2635 and H8S/2634. 23B.1 Overview In addition to the normal program execution state, the chip has nine power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. The chip operating modes are as follows: (1) High-speed mode (2) Medium-speed mode (3) Subactive mode* (U-mask, W-mask version, H8S/2635 Group only) (4) Sleep mode (5) Subsleep mode* (U-mask, W-mask version, H8S/2635 Group only) (6) Watch mode* (U-mask, W-mask version, H8S/2635 Group only) (7) Module stop mode (8) Software standby mode (9) Hardware standby mode (2) to (9) are low power dissipation states. Sleep mode and subsleep mode are CPU states, medium-speed mode is a CPU and bus master state, subactive mode is a CPU and bus master and internal peripheral function state, and module stop mode is an internal peripheral function (including bus masters other than the CPU) state. Some of these states can be combined. Rev. 6.00 Feb 22, 2005 page 973 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] After a reset, the LSI is in high-speed mode with modules other than the DTC in module stop mode. Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used with the other versions. Tables 23B-1 and 23B-2 show the internal state of the LSI in the respective modes. Table 23B-3 shows the conditions for shifting between the low power dissipation modes. Figure 23B-1 is a mode transition diagram. Rev. 6.00 Feb 22, 2005 page 974 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] Table 23B-1 LSI Internal States in Each Mode (H8S/2636, H8S/2638, H8S/2630) Function System clock pulse generator Subclock pulse generator CPU HighSpeed MediumSpeed Sleep Module Stop Watch Subactive Halted Software Hardware Subsleep Standby Standby Halted Halted Halted Function- Function- Function- Function- Halted ing ing ing ing Function- Function- Function- Function- Function- Function- Function- Function- Halted ing*1 ing*1 ing*1 ing*1 ing*1 ing*1 ing*1 ing*1 Instructions Function- Medium- Halted High/ Halted Subclock Halted Halted Halted Registers ing speed (retained) medium- (retained) operation (retained) (retained) (undefined) operation speed operation Function- Function- Function- Function- Function- Function- Function- Function- Halted ing ing ing ing ing ing ing ing Function- Function- Function- ing ing ing Function- Function- Function- ing ing ing External NMI interrupts IRQ0 to IRQ5 Peripheral WDT1 functions WDT0 DTC Subclock Subclock Subclock Halted Halted operation operation operation (retained) (reset) Halted Subclock Subclock Halted Halted (retained) operation operation (retained) (reset) Halted Halted Halted Halted Halted Function- Medium- Function- Halted ing (retained) (retained) (retained) (retained) (retained) (reset) ing speed operation Halted Subclock Halted Halted Halted Function- Medium- Function- Halted ing (retained) (retained) operation (retained) (retained) (reset) ing speed operation Function- Function- Function- Halted Halted Halted Halted Halted Halted ing ing ing (retained) (retained) (retained) (retained) (retained) (reset) PBC TPU IIC0*2 IIC1*2 PPG D/A0, 1 SCI0 SCI1 SCI2 PWM A/D RAM I/O HCAN Function- Function- Function- Halted ing ing ing (reset) Halted (reset) Halted (reset) Halted (reset) Halted (reset) Halted (reset) Function- Function- Function- Function- Retained Function- Retained Retained Retained ing ing ing (DTC) ing ing Function- Function- Function- Function- Retained Function- Retained Retained High ing ing ing ing ing impedance Function- Function- Function- Halted ing ing ing (reset) Halted (reset) Halted (reset) Halted (reset) Halted (reset) Halted (reset) Notes: "Halted (retained)" means that internal register values are retained. The internal state is "operation suspended." "Halted (reset)" means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). 1. Halted if the SUBSTP bit in LPWRCR is set to 1. 2. The I2C bus interface is available as an option in the H8S/2638, H8S/2639, and H8S/2630. The product equipped with the I2C bus interface is the W-mask version. Rev. 6.00 Feb 22, 2005 page 975 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] Table 23B-2 LSI Internal States in Each Mode (H8S/2639 Group, H8S/2635 Group) Function System clock () HighSpeed MediumSpeed Sleep Module Stop Watch Subactive Halted Software Hardware Subsleep Standby Standby Halted Halted Halted Function- Function- Function- Function- Halted ing ing ing ing Clock pulse generator Function- Function- Function- Function- Function- Function- Function- Function- Halted ing ing ing ing ing*1 ing*1 ing*1 ing*1 Subclock (Sub) CPU Function- Function- Function- Function- Function- Function- Function- Function- Halted ing*1 ing*1 ing*1 ing*1 ing*1 ing*1 ing*1 ing*1 Instructions Function- Medium- Halted High/ Halted Subclock Halted Halted Halted Registers ing speed (retained) medium- (retained) operation (retained) (retained) (undefined) operation speed operation Function- Function- Function- Function- Function- Function- Function- Function- Halted ing ing ing ing ing ing ing ing Function- Function- Function- ing ing ing Function- Function- Function- ing ing ing External NMI interrupts IRQ0 to IRQ5 Peripheral WDT1 functions WDT0 DTC*3 Subclock Subclock Subclock Halted Halted operation operation operation (retained) (reset) Halted Subclock Subclock Halted Halted (retained) operation operation (retained) (reset) Halted Halted Halted Halted Halted Function- Medium- Function- Halted ing (retained) (retained) (retained) (retained) (retained) (reset) ing speed operation Function- Function- Function- Halted Halted Halted Halted Halted Halted ing ing ing (retained) (retained) (retained) (retained) (retained) (reset) TPU IIC0*2 IIC1*2 PBC*3 PPG*3 D/A0, 1*3 SCI0 SCI1 SCI2 PWM A/D RAM I/O HCAN Function- Function- Function- Halted ing ing ing (reset) Halted (reset) Halted (reset) Halted (reset) Halted (reset) Halted (reset) Function- Function- Function- Function- Retained Function- Retained Retained Retained ing ing ing (DTC) ing ing Function- Function- Function- Function- Retained Function- Retained Retained High ing ing ing ing ing impedance Function- Function- Function- Halted ing ing ing (reset) Halted (reset) Halted (reset) Halted (reset) Halted (reset) Halted (reset) Notes: "Halted (retained)" means that internal register values are retained. The internal state is "operation suspended." "Halted (reset)" means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). 1. Halted if the SUBSTP bit in LPWRCR is set to 1. 2. The I2C bus interface is available as an option in the H8S/2638, H8S/2639, and H8S/2630. The product equipped with the I2C bus interface is the W-mask version. 3. The DTC, PBC, PPG, DA0, and DA1 are not implemented in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 976 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] Program-halted state STBY pin = Low Reset state STBY pin = High RES pin = Low Hardware standby mode RES pin = High Program execution state SLEEP command High-speed mode (main clock) All interrupt SCK2 to SCK0 = 0 SCK2 to SCK0 0 SLEEP command SSBY = 1, PSS = 0, LSON = 0 Software standby mode SSBY = 0, LSON = 0 Sleep mode (main clock) Medium-speed mode (main clock) External interrupt *3 SLEEP command Interrupt *2 LSON bit = 0 SSBY = 1, PSS = 1, DTON = 0 Watch mode (subclock) SLEEP command SSBY = 1, PSS = 1 DTON = 1, LSON = 0 After the oscillation stabilization time (STS2 to 0), clock switching exception processing SLEEP command SSBY = 1, PSS = 1 DTON = 1, LSON = 1 Clock switching exception processing SLEEP command Interrupt *1 LSON bit = 1 SLEEP command Interrupt *2 SSBY = 0, PSS = 1, LSON = 1 Sub-sleep mode (subclock) Sub-active mode (subclock) : Transition after exception processing : Low power dissipation mode Notes: When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. From any state except hardware standby mode, a transition to the reset state occurs when RES is driven Low. From any state, a transition to hardware standby mode occurs when STBY is driven low. Always select high-speed mode before making a transition to watch mode or subactive mode. 1. NMI, IRQ0 to IRQ5, and WDT1 interrupts 2. NMI, IRQ0 to IRQ5, IWDT0 interrupts, and WDT1 interrupt. 3. NMI and IRQ0 to IRQ5 Figure 23B-1 Mode Transition Diagram Rev. 6.00 Feb 22, 2005 page 977 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] Table 23B.3 Low Power Dissipation Mode Transition Conditions Status of Control Bit at Transition Pre-Transition SSBY PSS State High-speed/ Medium-speed 0 0 1 1 1 1 1 1 Subactive 0 0 0 1 1 1 1 1 Legend: *: Don't care --: Do not set * * 0 0 1 1 1 1 0 1 1 0 1 1 1 1 State after Transition Invoked by SLEEP LSON DTON Command * * * * 0 0 1 1 * * * * 0 0 1 1 Sleep -- Software standby -- Watch Watch -- Subactive -- -- Subsleep -- Watch Watch High-speed -- State after Transition Back from Low Power Mode Invoked by Interrupt High-speed/Mediumspeed -- High-speed/Mediumspeed -- High-speed Subactive -- -- -- -- Subactive -- High-speed Subactive -- -- 0 1 0 1 0 1 0 1 * 0 1 * 0 1 0 1 Rev. 6.00 Feb 22, 2005 page 978 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] 23B.1.1 Register Configuration Power-down modes are controlled by the SBYCR, SCKCR, LPWRCR, TCSR (WDT1), and MSTPCR registers. Table 23B-4 summarizes these registers. Table 23B-4 Power-Down Mode Registers Name Standby control register System clock control register Low-power control register Timer control/status register Module stop control register A, B, C, D Abbreviation SBYCR SCKCR LPWRCR TCSR MSTPCRA MSTPCRB MSTPCRC MSTPCRD Note: 1. Lower 16 bits of the address. R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'58 H'00 H'00 H'00 H'3F H'FF H'FF B'11****** Address*1 H'FDE4 H'FDE6 H'FDEC H'FFA2 H'FDE8 H'FDE9 H'FDEA H'FC60 23B.2 Register Descriptions 23B.2.1 Standby Control Register (SBYCR) Bit : 7 SSBY Initial value : R/W : 0 R/W 6 STS2 1 R/W 5 STS1 0 R/W 4 STS0 1 R/W 3 OPE 1 R/W 3/4 3/4 0 2 3/4 3/4 0 1 3/4 3/4 0 0 SBYCR is an 8-bit readable/writable register that performs power-down mode control. SBYCR is initialized to H'58 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Software Standby (SSBY): When making a low power dissipation mode transition by executing the SLEEP instruction, the operating mode is determined in combination with other control bits. Rev. 6.00 Feb 22, 2005 page 979 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] Note that the value of the SSBY bit does not change even when shifting between modes using interrupts. Bit 7 SSBY 0 Description Shifts to sleep mode when the SLEEP instruction is executed in high-speed mode or medium-speed mode. Shifts to subsleep mode when the SLEEP instruction is executed in subactive mode. (Initial value) Shifts to software standby mode, subactive mode, and watch mode when the SLEEP instruction is executed in high-speed mode or medium-speed mode. Shifts to watch mode or high-speed mode when the SLEEP instruction is executed in subactive mode. 1 Bits 6 to 4--Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the MCU wait time for clock stabilization when shifting to high-speed mode or medium-speed mode by using a specific interrupt or command to cancel software standby mode, watch mode, or subactive mode. With a quartz oscillator (Table 23B-6), select a wait time of 8ms (oscillation stabilization time) or more, depending on the operating frequency. With an external clock, select a standby time of 2 ms or more (PLL oscillator settling time), based on the operating frequency. Bit 6 STS2 0 Bit 5 STS1 0 1 1 0 1 Bit 4 STS0 0 1 0 1 0 1 0 1 Description Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states (Setting prohibited) (Initial value) Rev. 6.00 Feb 22, 2005 page 980 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] Bit 3--Output Port Enable (OPE): This bit specifies whether the output of the address bus and bus control signals (AS, , , ) is retained or set to high-impedance state in the software standby mode, watch mode, and when making a direct transition. Bit 3 OPE 0 1 Description In software standby mode, watch mode, and when making a direct transition, address bus and bus control signals are high-impedance. In software standby mode, watch mode, and when making a direct transition, the output state of the address bus and bus control signals is retained. (Initial value) Bits 2 to 0--Reserved: These bits always return 0 when read, and cannot be written to. 23B.2.2 System Clock Control Register (SCKCR) Bit : 7 PSTOP Initial value : R/W : 0 R/W SCKCR is an 8-bit readable/writable register that performs clock output control and mediumspeed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7-- Clock Output Disable (PSTOP): In combination with the DDR of the applicable port, this bit controls output. See section 23B.12, Clock Output Disable Function for details. Description Bit 7 PSTOP 0 1 High-Speed Mode, Medium-Speed Mode, Sleep Mode, Subactive Mode Subsleep Mode output (initial value) output Fixed high Fixed high Software Standby Mode, Watch Mode, Hardware Standby Direct Transition Mode Fixed high High impedance Fixed high High impedance RWL RWH DR 3/4 3/4 0 6 3/4 3/4 0 5 3/4 3/4 0 4 3 STCS 0 R/W 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W Rev. 6.00 Feb 22, 2005 page 981 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] Bits 6 to 4--Reserved: These bits are always read as 0 and cannot be modified. Bit 3--Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation when the PLL circuit frequency multiplication factor is changed. Bit 3 STCS 0 1 Description Specified multiplication factor is valid after transition to software standby mode, watch mode, or subactive mode (Initial value) Specified multiplication factor is valid immediately after STC bits are rewritten Bits 2 to 0--System Clock Select (SCK2 to SCK0): These bits select the bus master clock in high-speed mode, medium-speed mode, and subactive mode. Set SCK2 to SCK0 all to 0 when shifting to operation in watch mode or subactive mode. Bit 2 SCK2 0 Bit 1 SCK1 0 1 1 0 1 Bit 0 SCK0 0 1 0 1 0 1 -- Description Bus master in high-speed mode Medium-speed clock is /2 Medium-speed clock is /4 Medium-speed clock is /8 Medium-speed clock is /16 Medium-speed clock is /32 -- (Initial value) Rev. 6.00 Feb 22, 2005 page 982 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] 23B.2.3 Low-Power Control Register (LPWRCR) Bit : 7 DTON* Initial value : R/W : 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W LSON* NESEL* SUBSTP* RFCUT* 3/4 0 R/W 2 1 STC1 0 R/W 0 STC0 0 R/W Note: * Bits 7 to 3 in LPWRCR are valid in the U-mask and W-mask versions, and H8S/2635 Group; they are reserved bits in all other versions. See section 23A.2.3, Low-Power Control Register (LPWRCR), for more information. The LPWRCR is an 8-bit read/write register that controls the low power dissipation modes. The LPWRCR is initialized to H'00 at a reset and when in hardware standby mode. It is not initialized in software standby mode. The following describes bits 7 to 2. For details of other bits, see sections 22A.2.2, 22B.2.2, Low-Power Control Register (LPWRCR). Bit 7--Direct Transition ON Flag (DTON): When shifting to low power dissipation mode by executing the SLEEP instruction, this bit specifies whether or not to make a direct transition between high-speed mode or medium-speed mode and the subactive modes. The selected operating mode after executing the SLEEP instruction is determined by the combination of other control bits. Bit 7 DTON 0 Description * * 1 * When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode*. When the SLEEP instruction is executed in subactive mode, operation shifts to subsleep mode or watch mode. (Initial value) When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts directly to subactive mode*, or shifts to sleep mode or software standby mode. When the SLEEP instruction is executed in subactive mode, operation shifts directly to high-speed mode, or shifts to subsleep mode. * Note: * Always set high-speed mode when shifting to watch mode or subactive mode. Rev. 6.00 Feb 22, 2005 page 983 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] Bit 6--Low-Speed ON Flag (LSON): When shifting to low power dissipation mode by executing the SLEEP instruction, this bit specifies the operating mode, in combination with other control bits. This bit also controls whether to shift to high-speed mode or subactive mode when watch mode is cancelled. Bit 6 LSON 0 Description * * * 1 * * * When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode*. When the SLEEP instruction is executed in subactive mode, operation shifts to watch mode or shifts directly to high-speed mode. Operation shifts to high-speed mode when watch mode is cancelled. (Initial value) When the SLEEP instruction is executed in high-speed mode, operation shifts to watch mode or subactive mode. When the SLEEP instruction is executed in subactive mode, operation shifts to subsleep mode or watch mode. Operation shifts to subactive mode when watch mode is cancelled. Note: * Always set high-speed mode when shifting to watch mode or subactive mode. Bit 5--Noise Elimination Sampling Frequency Select (NESEL): This bit selects the sampling frequency of the subclock (SUB) generated by the subclock oscillator is sampled by the clock () generated by the system clock oscillator. Set this bit to 0 when =5MHz or more. This setting is disabled in subactive mode, subsleep mode, and watch mode. Bit 5 NESEL 0 1 Description Sampling using 1/32 x Sampling using 1/4 x (Initial value) Bit 4--Subclock Enable (SUBSTP): This bit enables/disables subclock generation. Bit 4 SUBSTP Description 0 1 Enables subclock generation Disables subclock generation (Initial value) Rev. 6.00 Feb 22, 2005 page 984 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] Bit 3--Oscillation Circuit Feedback Resistance Control Bit (RFCUT): This bit turns the internal feedback resistance of the main clock oscillation circuit ON/OFF. Bit 3 RFCUT 0 1 Description When the main clock is oscillating, sets the feedback resistance ON. When the main clock is stopped, sets the feedback resistance OFF. (Initial value) Sets the feedback resistance OFF. Bit 2--Reserved: Only write 0 to this bit. 23B.2.4 Timer Control/Status Register (TCSR) Bit : 7 OVF Initial value : R/W : 0 R/(W)*1 6 WT/IT 0 R/W 5 TME 0 R/W 3 4 PSS*2 RST/NMI 0 R/W 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Notes: 1. Only write 0 to clear the flag. 2. Bit 4 (PSS) in TCSR of WDT1 is valid in the U-mask and W-mask versions, and H8S/2635 Group. In versions other than the U-mask and W-mask versions, and H8S/2635 Group, however, the PSS bit must always be written with 0 since no subclock functions are available. TCSR is an 8-bit read/write register that selects the clock input to WDT1 TCNT and the mode. Here, we describe bit 4. For details of the other bits in this register, see section 12.2.2, Timer Control/Status Register (TCSR). The TCSR is initialized to H'00 at a reset and when in hardware standby mode. It is not initialized in software standby mode. Rev. 6.00 Feb 22, 2005 page 985 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] Bit 4--Prescaler Select (PSS): This bit selects the clock source input to WDT1 TCNT. It also controls operation when shifting low power dissipation modes. The operating mode selected after the SLEEP instruction is executed is determined in combination with other control bits. For details, see the description for clock selection in section 12.2.2, Timer Control/Status Register (TCSR), and this section. Bit 4 PSS 0 Description * * 1 * * * TCNT counts the divided clock from the -based prescaler (PSM). When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode or software standby mode. (Initial value) TCNT counts the divided clock from the subclock-based prescaler (PSS). When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, watch mode*1 *2, or subactive mode*1 *2. 2 When the SLEEP instruction is executed in subactive mode* , operation shifts to 2 2 subsleep mode* , watch mode* , or high-speed mode. Notes: 1. Always set high-speed mode when shifting to watch mode or subactive mode. 2. Bit 4 (PSS) in TCSR of WDT1 is valid in the U-mask and W-mask versions, and H8S/2635 Group. In versions other than the U-mask and W-mask versions, and H8S/2635 Group, however, the PSS bit must always be written with 0 since no subclock functions are available. Rev. 6.00 Feb 22, 2005 page 986 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] 23B.2.5 Module Stop Control Register (MSTPCR) MSTPCRA Bit : 7 0 R/W 6 0 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W MSTPCRB Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : R/W MSTPCRC Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value : R/W : : : MSTPCRD Bit : 7 1 R/W 6 1 R/W 5 4 3 2 1 0 MSTPD7 MSTPD6 MSTPD5 MSTPD4 MSTPD3 MSTPD2 MSTPD1 MSTPD0 Initial value : R/W : Undefined Undefined Undefined Undefined Undefined Undefined -- -- -- -- -- -- MSTPCR, comprising four 8-bit readable/writable registers, performs module stop mode control. MSTPCRA to MSTPCRC are initialized to H'3FFFFF by a reset and in hardware standby mode. MSTPCRD is initialized to B'11****** by a reset and in hardware standby mode. They are not initialized in software standby mode. Rev. 6.00 Feb 22, 2005 page 987 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] MSTPCRA/MSTPCRB/MSTPCRC Bits 7 to 0, MSTPCRD Bits 7 and 6--Module Stop (MSTPA7 to MSTPA0, MSTPB7 to MSTPB0, MSTPC7 to MSTPC0, MSTPD7 and MSTPD6): These bits specify module stop mode. See table 23B-5 for the method of selecting the on-chip peripheral functions. MSTPCRA/MSTPCRB/ MSTPCRC Bits 7 to 0, MSTPCRD Bits 7 and 6 MSTPA7 to MSTPA0, MSTPB7 to MSTPB0, MSTPC7 to MSTPC0, MSTPD7 and MSTPD6 Description 0 1 Module stop mode is cleared (initial value of MSTPA7 and MSTPA6) Module stop mode is set (initial value of MSTPA5-0, MSTPB7-0, MSTPC7-0, and MSTPC7, 6) 23B.3 Medium-Speed Mode In high-speed mode, when the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to medium-speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (/2, /4, /8, /16, or /32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (DTC) also operate in medium-speed mode. On-chip supporting modules other than the bus masters always operate on the high-speed clock (). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if /4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, and LSON bit in LPWRCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the SSBY bit = 1, LPWRCR LSON bit = 0, and TCSR (WDT1) PSS bit = 0, operation shifts to the software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. Rev. 6.00 Feb 22, 2005 page 988 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] When the pin is set low and medium-speed mode is cancelled, operation shifts to the reset state. The same applies in the case of a reset caused by overflow of the watchdog timer. Figure 23B-2 shows the timing for transition to and clearance of medium-speed mode. Medium-speed mode B, supporting module clock Bus master clock Internal address bus Internal write signal 23B.4 Sleep Mode 23B.4.1 Sleep Mode When the SLEEP instruction is executed when the SBYCR SSBY bit = 0 and the LPWRCR LSON bit = 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the contents of the CPUis internal registers are retained. Other supporting modules do not stop. 23B.4.2 Exiting Sleep Mode Exiting Sleep Mode by Interrupts: When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU. Rev. 6.00 Feb 22, 2005 page 989 of 1484 REJ09B0103-0600 YBTS SER Sleep mode is exited by any interrupt, or signals at the YBTS When the SER pin is driven low, a transition is made to hardware standby mode. SBYCR SBYCR Figure 23B-2 Medium-Speed Mode Transition and Clearance Timing , or pins. Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] Exiting Sleep Mode by pin: Setting the pin level Low selects the reset state. After the stipulated reset input duration, driving the pin High starts the CPU performing reset exception processing. 23B.5 Module Stop Mode 23B.5.1 Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 23B-5 shows MSTP bits and the corresponding on-chip supporting modules. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI, Motor control PWM, A/D converter and HCAN are retained. After reset clearance, all modules other than DTC are in module stop mode. When an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. Rev. 6.00 Feb 22, 2005 page 990 of 1484 REJ09B0103-0600 YBTS YBTS Exiting Sleep Mode by to hardware standby mode. Pin: When the SER SER SER pin level is driven Low, a transition is made Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] Table 23B-5 MSTP Bits and Corresponding On-Chip Supporting Modules Register MSTPCRA Bit MSTPA6 MSTPA5 MSTPA3 MSTPA2 MSTPA1 MSTPA0 MSTPCRB MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB0*1 MSTPCRC MSTPC4 MSTPC3 MSTPC2 MSTPC1*1 MSTPC0*1 MSTPCRD MSTPD7 MSTPD6*1 Notes: 1. MSTPA0, MSTPB0 and MSTPC1 to MSTPC0 and MSTPD6 are readable/writable bits with an initial value of 1. 2. The I2C bus interface is available as an option in the H8S/2638, H8S/2639, and 2 H8S/2630. The product equipped with the I C bus interface is the W-mask version. When this optional feature is not used or in H8S/2636, MSTB4 and MSTB3 are readable and writable bits that have 1 as their initial value. 3. The DTC, PPG, D/A converter, PBC, and HCAN1 are not implemented in the H8S/2635 and H8S/2634. MSTPA6, MSTPA3, MSTPA2, MSTPC4, and MSTPC2 are readable/writable bits, but only 1 should be written to them. Motor control PWM (PWM) PC break controller (PBC)*3 HCAN0 HCAN1*3 *1 Serial communication interface 0 (SCI0) Serial communication interface 1 (SCI1) Serial communication interface 2 (SCI2) I2C bus interface 0 (IIC0)*2 I2C bus interface 1 (IIC1)*2 Module Data transfer controller (DTC)* 16-bit timer pulse unit (TPU) Programmable pulse generator (PPG)*3 D/A converter (channel 0, 1)*3 A/D converter 3 Rev. 6.00 Feb 22, 2005 page 991 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] 23B.5.2 Usage Notes Note: The DTC is not implemented in the H8S/2635 Group. DTC Module Stop: Depending on the operating status of the DTC, the MSTPA7 and MSTPA6 bits may not be set to 1. Setting of the DTC module stop mode should be carried out only when the respective module is not activated. For details, refer to section 8, Data Transfer Controller (DTC). On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Writing to MSTPCR: MSTPCR should only be written to by the CPU. 23B.6 Software Standby Mode 23B.6.1 Software Standby Mode A transition is made to software standby mode when the SLEEP instruction is executed when the SBYCR SSBY bit = 1 and the LPWRCR LSON bit = 0, and the TCSR (WDT1) PSS bit = 0. In this mode, the CPU, on-chip supporting modules, and oscillator all stop*. However, the contents of the CPU's internal registers, RAM data, and the states of on-chip supporting modules other than the SCI, A/D converter, Motor control PWM, HCAN and I/O ports, are retained. Whether the address bus and bus control signals are placed in the high-impedance state. In this mode the oscillator stops*, and therefore power dissipation is significantly reduced. Note: * The subclock (SUB) operates if the SUBSTP bit in LPWRCR is set to 0. Rev. 6.00 Feb 22, 2005 page 992 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] 23B.6.2 Clearing Software Standby Mode * Clearing with an interrupt When an NMI or IRQ0 to IRQ5 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ5 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ5 is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. * Clearing with the pin When the pin is driven Low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the pin must be held Low until clock oscillation stabilizes. When the pin goes high, the CPU begins reset exception handling. pin * Clearing with the When the pin is driven Low, a transition is made to hardware standby mode. 23B.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: 1. Setting for H8S/2636, H8S/2638, H8S/2639, H8S/2630 Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time). Table 23B-6 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Rev. 6.00 Feb 22, 2005 page 993 of 1484 REJ09B0103-0600 5QRI 0QRI Software standby mode is cleared by an external interrupt (NMI pin, or pins pin or pin. means of the to ), or by SER SER YBTS YBTS SER YBTS SER SER Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] Table 23B-6 Oscillation Stabilization Time Settings STS2 0 STS1 0 STS0 0 1 1 0 1 1 0 0 1 1 0 1 Standby Time 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved 16 states (Setting prohibited) 20 MHz 0.41 0.82 1.6 3.3 6.6 16 MHz 0.51 1.0 2.0 4.1 8.2 12 MHz 0.68 1.3 2.7 5.5 10.9 21.8 -- 1.3 10 MHz 0.8 1.6 3.3 6.6 8 MHz 1.0 2.0 4.1 8.2 6 MHz 1.3 2.7 5.5 10.9 21.8 43.6 -- 2.6 5 MHz 1.6 3.2 6.5 4 MHz 2.0 4.1 8.2 Unit ms 13.1 16.4 26.2 52.4 -- 3.2 32.8 65.6 -- 4.0 s 13.1 16.4 26.2 -- 1.6 32.8 -- 2.0 13.1 16.4 -- 0.8 -- 1.0 : Recommended time setting 2. Setting for H8S/2635, H8S/2634 Set bits STS2 to STS0 so that the standby time is at least 12 ms (the oscillation stabilization time). Table 23B-7 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 23B-7 Oscillation Stabilization Time Settings STS2 0 STS1 0 STS0 0 1 1 0 1 1 0 0 1 1 0 1 Standby Time 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved 16 states (Setting prohibited) 20 MHz 16 MHz 10 MHz 8 MHz 0.41 0.82 1.6 3.3 6.6 13.1 -- 0.8 0.51 1.0 2.0 4.1 8.2 16.4 -- 1.0 0.8 1.6 3.3 6.6 13.1 26.2 -- 1.6 1.0 2.0 4.1 8.2 16.4 32.8 -- 2.0 5 MHz 1.6 3.2 6.5 13.1 26.2 52.4 -- 3.2 4 MHz 2.0 4.1 8.2 16.4 32.8 65.6 -- 4.0 s Unit ms : Recommended time setting Rev. 6.00 Feb 22, 2005 page 994 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] Using an External Clock: The PLL circuit requires time to stabilize, so the standby time should be set to a value of 2 ms or more. 23B.6.4 Software Standby Mode Application Example Figure 23B-3 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin. Oscillator B NMI NMIEG SSBY NMI exception Software standby mode handling (power-down mode) NMIEG=1 SSBY=1 SLEEP instruction Oscillation stabilization time tOSC2 NMI exception handling Figure 23B-3 Software Standby Mode Application Example Rev. 6.00 Feb 22, 2005 page 995 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] 23B.6.5 Usage Notes I/O Port Status: In software standby mode, I/O port states are retained. If the OPE bit is set to 1, the address bus and bus control signal output is also retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. Current Dissipation during Oscillation Stabilization Wait Period: Current dissipation increases during the oscillation stabilization wait period. Write Data Buffer Function: The write data buffer function and software standby mode cannot be used at the same time. When the write data buffer function is used, the WDBE bit in BCRL should be cleared to 0 to cancel the write data buffer function before entering software standby mode. Also check that external writes have finished, by reading external addresses, etc., before executing a SLEEP instruction to enter software standby mode. See section 7.9, Write Data Buffer Function, for details of the write data buffer function. 23B.7 Hardware Standby Mode 23B.7.1 Hardware Standby Mode In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before pin low. driving the Do not change the state of the mode pins (MD2 to MD0) while the chip is in hardware standby mode. pin and the pin. When the Hardware standby mode is cleared by means of the pin is driven high while the pin is low, the reset state is set and clock oscillation is started. pin is held low until the clock oscillator stabilizes (at least 8 ms--the Ensure that the oscillation stabilization time--when using a crystal oscillator). When the pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. Rev. 6.00 Feb 22, 2005 page 996 of 1484 REJ09B0103-0600 YBTS SER SER YBTS SER SER YBTS YBTS When the pin is driven low, a transition is made to hardware standby mode from any mode. Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] 23B.7.2 Hardware Standby Mode Timing Figure 23B-4 shows an example of hardware standby mode timing. pin is driven low after the pin has been driven low, a transition is made to When the pin high, hardware standby mode. Hardware standby mode is cleared by driving the waiting for the oscillation stabilization time, then changing the pin from low to high. Oscillator 4-5 56*; Oscillation stabilization time Figure 23B-4 Hardware Standby Mode Timing 23B.8 Watch Mode (U-Mask, W-Mask Version, H8S/2635 Group Only) 23B.8.1 Watch Mode CPU operation makes a transition to watch mode when the SLEEP instruction is executed in highspeed mode or subactive mode with SBYCR SSBY=1, LPWRCR DTON = 0, and TCSR (WDT1) PSS = 1. In watch mode, the CPU is stopped and supporting modules other than WDT1 are also stopped. The contents of the CPU's internal registers, the data in internal RAM, and the statuses of the internal supporting modules (excluding the SCI, ADC, HCAN, and Motor control PWM) and I/O ports are retained. Rev. 6.00 Feb 22, 2005 page 997 of 1484 REJ09B0103-0600 YBTS SER SER YBTS Reset exception handling Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] 23B.8.2 Exiting Watch Mode (1) Exiting Watch Mode by Interrupts When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or medium-speed mode when the LPWRCR LSON bit = 0 or to subactive mode when the LSON bit = 1. When a transition is made to high-speed mode, a stable clock is supplied to all LSI circuits and interrupt exception processing starts after the time set in SBYCR STS2 to STS0 has elapsed. In the case of IRQ0 to IRQ5 interrupts, no transition is made from watch mode if the corresponding enable bit has been cleared to 0, and, in the case of interrupts from the internal supporting modules, the interrupt enable register has been set to disable the reception of that interrupt, or is masked by the CPU. See section 23B.6.3, Setting Oscillation Stabilization Time after Clearing Software Standby Mode for how to set the oscillation stabilization time when making a transition from watch mode to high-speed mode. 23B.8.3 Notes (1) I/O Port Status The status of the I/O ports is retained in watch mode. Also, when the OPE bit is set to 1, the address bus and bus control signals continue to be output. Therefore, when a High level is output, the current consumption is not diminished by the amount of current to support the High level output. (2) Current Consumption when Waiting for Oscillation Stabilization The current consumption increases during stabilization of oscillation. Rev. 6.00 Feb 22, 2005 page 998 of 1484 REJ09B0103-0600 YBTS When the pin level is driven Low, a transition is made to hardware standby mode. YBTS (3) Exiting Watch Mode by pin SER pins, see, Clearing with the For exiting watch mode by the Clearing Software Standby Mode. SER SER (2) Exiting Watch Mode by pins pins in section 23B.6.2, 5QRI 0QRI Watch mode is exited by any interrupt (WOVI interrupt, NMI pin, or the , or pins. to ), or signals at YBTS SER Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] 23B.9 Subsleep Mode (U-Mask, W-Mask Version, H8S/2635 Group Only) 23B.9.1 Subsleep Mode When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1, and TCSR (WDT1) PSS bit = 1, CPU operation shifts to subsleep mode. In subsleep mode, the CPU is stopped. Supporting modules other than WDT0, and WDT1 are also stopped. The contents of the CPU's internal registers, the data in internal RAM, and the statuses of the internal supporting modules (excluding the SCI, ADC, HCAN, and Motor control PWM) and I/O ports are retained. 23B.9.2 Exiting Subsleep Mode Subsleep mode is exited by an interrupt (interrupts from internal supporting modules, NMI pin, or to ), or signals at the or pins. (1) Exiting Subsleep Mode by Interrupts When an interrupt occurs, subsleep mode is exited and interrupt exception processing starts. In the case of IRQ0 to IRQ5 interrupts, subsleep mode is not cancelled if the corresponding enable bit has been cleared to 0, and, in the case of interrupts from the internal supporting modules, the interrupt enable register has been set to disable the reception of that interrupt, or is masked by the CPU. YBTS When the pin level is driven Low, a transition is made to hardware standby mode. YBTS (3) Exiting Subsleep Mode by Pin Rev. 6.00 Feb 22, 2005 page 999 of 1484 REJ09B0103-0600 SER SER For exiting subsleep mode by the Clearing Software Standby Mode. SER (2) Exiting Subsleep Mode by YBTS SER 5QRI 0QRI pins, see, Clearing with the pins in section 23B.6.2, Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] 23B.10 Subactive Mode (U-Mask, W-Mask Version, H8S/2635 Group Only) 23B.10.1 Subactive Mode When the SLEEP instruction is executed in high-speed mode with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 1, LSON bit = 1, and TCSR (WDT1) PSS bit = 1, CPU operation shifts to subactive mode. When an interrupt occurs in watch mode, and if the LSON bit of LPWRCR is 1, a transition is made to subactive mode. And if an interrupt occurs in subsleep mode, a transition is made to subactive mode. In subactive mode, the CPU operates at low speed on the subclock, and the program is executed step by step. Supporting modules other than WDT0, and WDT1 are also stopped. When operating the CPU in subactive mode, the SCKCR SCK2 to SCK0 bits must be set to 0. 23B.10.2 Exiting Subactive Mode (1) Exiting Subactive Mode by SLEEP Instruction When the SLEEP instruction is executed with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 0, and TCSR (WDT1) PSS bit = 1, the CPU exits subactive mode and a transition is made to watch mode. When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1, and TCSR (WDT1) PSS bit = 1, a transition is made to subsleep mode. Finally, when the SLEEP instruction is executed with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 1, LSON bit = 0, and TCSR (WDT1) PSS bit = 1, a direct transition is made to high-speed mode (SCK0 to SCK2 all 0). See section 23B.11, Direct Transitions for details of direct transitions. Rev. 6.00 Feb 22, 2005 page 1000 of 1484 REJ09B0103-0600 YBTS When the pin level is driven Low, a transition is made to hardware standby mode. YBTS (3) Exiting Subactive Mode by Pin SER SER For exiting subactive mode by the Clearing Software Standby Mode. SER (2) Exiting Subactive Mode by Pins pins, see, Claering with the pins in section 23B.6.2, YBTS SER Subactive mode is exited by the SLEEP instruction or the or pins. Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] 23B.11 Direct Transitions (U-Mask, W-Mask Version, H8S/2635 Group Only) 23B.11.1 Overview of Direct Transitions There are three modes, high-speed, medium-speed, and subactive, in which the CPU executes programs. When a direct transition is made, there is no interruption of program execution when shifting between high-speed and subactive modes. Direct transitions are enabled by setting the LPWRCR DTON bit to 1, then executing the SLEEP instruction. After a transition, direct transition interrupt exception processing starts. (1) Direct Transitions from High-Speed Mode to Subactive Mode Execute the SLEEP instruction in high-speed mode when the SBYCR SSBY bit = 1, LPWRCR LSON bit = 1, and DTON bit = 1, and TSCR (WDT1) PSS bit = 1 to make a transition to subactive mode. (2) Direct Transitions from Subactive Mode to High-Speed Mode Execute the SLEEP instruction in subactive mode when the SBYCR SSBY bit = 1, LPWRCR LSON bit = 0, and DTON bit = 1, and TSCR (WDT1) PSS bit = 1 to make a direct transition to high-speed mode after the time set in SBYCR STS2 to STS0 has elapsed. Rev. 6.00 Feb 22, 2005 page 1001 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] 23B.12 Clock Output Disabling Function Output of the clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the clock stops at the end of the bus cycle, and output goes high. clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, clock output is disabled and input port mode is set. Table 23B-8 shows the state of the pin in each processing state. Using the on-chip PLL circuit to lower the oscillator frequency or prohibiting external clock output also have the effect of reducing unwanted electromagnetic interference*. Therefore, consideration should be given to these options when deciding on system board settings. Note: * Electromagnetic interference: EMI (Electro Magnetic Interference) Table 23B-8 Pin State in Each Processing State DDR PSTOP Hardware standby mode Software standby mode, watch mode*, and direct transition Sleep mode and subsleep mode* High-speed mode, medium-speed mode, and subactive mode* Subactive mode 0 -- High impedance High impedance High impedance High impedance High impedance 1 0 High impedance Fixed high output output SUB output 1 1 High impedance Fixed high Fixed high Fixed high Fixed high Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used with the other versions. Rev. 6.00 Feb 22, 2005 page 1002 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] 23B.13 Usage Notes 1. When making a transition to subactive mode or watch mode, set the DTC to enter module stop mode (write 1 to the relevant bits in MSTPCR), and then read the relevant bits to confirm that they are set to 1 before mode transition. Do not clear module stop mode (write 0 to the relevant bits in MSTPCR) until a transition from subactive mode to high-speed mode or medium-speed mode has been performed. If a DTC activation source occurs in subactive mode, the DTC will be activated only after module stop mode has been cleared and high-speed mode or medium-speed mode has been entered. 2. The on-chip peripheral modules (DTC and TPU) which halt operation in subactive mode cannot clear an interrupt in subactive mode. Therefore, if a transition is made to subactive mode while an interrupt is requested, the CPU interrupt source cannot be cleared. Disable the interrupts of each on-chip peripheral module before executing a SLEEP instruction to enter subactive mode or watch mode. 3. A 1 is always returned when an attempt is made to read the pin status of I/O ports 1, 4, 9, or F during operation in subactive mode. (In the case of port 1, pins 13 to 10 are readable.) In addition, the ports may be used as output ports (except for ports 4 and 9). The procedure for determining the pin status during operation in subactive mode is as follows. [1] Use ports 3, A, B, C, D, E, H, and J as input ports. [2] Use external interrupt inputs (IRQ0 to IRQ5). (If the level sense setting has been selected for the IRQ pins, an interrupt request is generated by a low-level input.) 4. Operation cannot be guaranteed if a transition is made to the subactive mode, subsleep mode, or watch mode when the SUBSTP bit in LPWRCR is set to 1 (subclock generation prohibited). To prevent problems, it should be confirmed that the SUBSTP bit has been cleared to 0 before transitioning to the subactive mode, subsleep mode, or watch mode. 5. (H8S/2639 Group, H8S/2635 Group only) The subclock (SUB) is frequency divided internally, so the clock oscillator does not halt even if a transition to the software standby mode occurs when the SUBSTP bit in LPWRCR is cleared to 0. The SUBSTP bit in LPWRCR should be set to 1 before transitioning to the software standby mode. Rev. 6.00 Feb 22, 2005 page 1003 of 1484 REJ09B0103-0600 Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF] Rev. 6.00 Feb 22, 2005 page 1004 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics Section 24 Electrical Characteristics 24.1 24.1.1 H8S/2636 Group Electrical Characteristics Absolute Maximum Ratings Table 24-1 lists the absolute maximum ratings. Table 24-1 Absolute Maximum Ratings Item Power supply voltage Input voltage (OSC1, OSC2) Input voltage (XTAL, EXTAL) Input voltage (ports 4 and 9) Input voltage (ports H and J) Symbol VCC Vin Vin Vin Vin Value -0.3 to +7.0 -0.3 +4.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to PWMVCC +0.3 -0.3 to VCC +0.3 Unit V V V V V V Input voltage (except XTAL, Vin EXTAL, OSC1, OSC2, ports 4, 9, H and J) Reference voltage Analog power supply voltage Analog input voltage Operating temperature Storage temperature Vref AVCC VAN Topr Tstg -0.3 to AVCC +0.3 -0.3 to +7.0 -0.3 to AVCC +0.3 Regular specifications: -20 to +75 Wide-range specifications: -40 to +85 -55 to +125 V V V C C C Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded. Rev. 6.00 Feb 22, 2005 page 1005 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.1.2 Power Supply Voltage and Operating Frequency Range Power supply voltage and operating frequency ranges (shaded areas) are shown in figure 24-1. Operating range of high-speed, medium-speed and sleep modes 24 20 Frequency (MHz) 16 12 8 4 0 3 3.5 4 4.5 5 5.5 6 Power supply voltage (V) Operating range of watch*, sub-active* and sub-sleep* modes 32.768 Frequency (MHz) 0 3 3.5 4 4.5 5 5.5 6 Power supply voltage (V) Note: * The watch, subactive, and subsleep modes are available in the U-mask version only. Figure 24-1 Power Supply Voltage and Operating Ranges Rev. 6.00 Feb 22, 2005 page 1006 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.1.3 DC Characteristics Table 24-2 lists the DC characteristics. Table 24-3 lists the permissible output currents. Table 24-2 DC Characteristics Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)*1 *6 Item Schmitt trigger input voltage Input high voltage Symbol IRQ0 to IRQ5 VT VT , , NMI, FWE, MD2 to MD0 - + + - Min. 1.0 -- 0.4 VCC - 0.7 Typ. -- -- -- -- Max. -- VCC x 0.7 -- VCC + 0.3 Unit V Test Conditions VT - VT VIH V YBTS SER Input low voltage YBTS SER EXTAL Ports H, J HRxD0, HRxD1 EXTAL Ports H, J HRxD0, HRxD1 Ports 4, 9 VCC x 0.7 2.2 VCC x 0.8 -- -- -- VCC + 0.3 VCC + 0.3 VCC + 0.3 PWMVCC + 0.3 VCC + 0.3 AVCC + 0.3 0.5 V Ports 1, 3, F Ports A to E PWMVCC x -- 0.8 2.2 -- Ports 4 and 9 , , NMI, FWE, MD2 to MD0 Ports 1, 3, F Ports A to E VIL AVCC x 0.7 -- -0.3 -- -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -- -- -- -- -- -- 0.8 0.8 VCC x 0.2 PWMVCC x 0.2 VCC x 0.2 AVCC x 0.2 Rev. 6.00 Feb 22, 2005 page 1007 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics Item Output high voltage Ports 1, 3, A to F, H,J HTxD0, HTxD1 PWM1A to PWM1H, PWM2A to PWM2H Output low voltage All output pins VOL except PWM1A to PWM1H, PWM2A to PWM2H PWM1A to PWM1H, PWM2A to PWM2H Symbol VOH Min. VCC - 0.5 3.5 PWMVCC - 0.5 Typ. -- -- Max. -- -- -- Unit V Test Conditions IOH = -200 A IOH = -1 mA IOH = -15 mA -- -- 0.4 V IOL = 1.6 mA -- -- 0.5 V IOL = 15 mA Three-state leakage current (off state) MOS input Ports A to E pull-up current Rev. 6.00 Feb 22, 2005 page 1008 of 1484 REJ09B0103-0600 SER SER Input capacitance IMN YBTS SER Ports 4, 9 NMI Input leakage current | Iin | -- -- -- -- -- -- -- -- 1.0 1.0 1.0 1.0 1.0 A , , MD2 to MD0 HRxD0, HRxD1, FWE Vin =0.5 V to VCC - 0.5 V Vin = 0.5 V to AVCC - 0.5 V A Vin = 0.5 V to VCC - 0.5 V Ports 1, 3, A to F, H, J HTxD0, HTxD1 ITSI -- -IP Cin 50 -- -- -- -- -- -- 300 30 30 15 A pF Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25C All input pins except and NMI Section 24 Electrical Characteristics Item Current Normal dissipation*2 operation Sleep mode All modules stopped Mediumspeed mode (/32) Subactive mode*5 Subsleep mode*5 Watch mode*5 Standby mode*3 Analog During A/D power supply and D/A current conversion Idle Reference current During A/D and D/A conversion Idle RAM standby voltage VRAM AlCC AlCC Symbol Min. ICC*4 -- -- -- -- Typ. 75 65 57 49 Max. 90 80 -- -- mA f = 20 MHz (reference value) Unit mA Test Conditions f = 20 MHz -- -- -- -- -- -- 130 80 30 2.0 -- 1.0 220 160 60 5.0 20 2.0 A Using 32.768 kHz crystal resonator A mA Ta 50C 50C < Ta AVCC = 5.0 V -- -- 0.1 4.0 5.0 5.0 A mA Vref = 5.0 V -- 2.0 0.1 -- 5.0 -- A V Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage between 4.5 V and 5.5 V to the AVCC and Vref pins by connecting them to VCC, for instance. Set Vref AVCC. 2. Current dissipation values are for VIH (min.) = VCC - 0.5 V, VIL (max.) = 0.5 V with all output pins unloaded and the on-chip pull-up resistors in the off state. 3. The values are for VRAM VCC < 3.0 V, VIH (min.) = VCC x 0.9, and VIL (max.) = 0.3 V. 4. ICC depends on VCC and f as follows: ICC (max.) = 30 (mA) + 0.54 (mA/(MHz x V)) x VCC x f (normal operation) ICC (max.) = 30 (mA) + 0.45 (mA/(MHz x V)) x VCC x f (sleep mode) 5. The watch, subactive, and subsleep modes are available in the U-mask version only. See section 22A.7, Subclock Oscillator, for the method of fixing pins OSC1 and OSC2. 6. If the motor-control PWM timer is not used, do not leave the PMWVCC, or PMWVSS pins open. If the motor-control PWM timer is not used, apply a voltage of between 4.5 and 5.5 V to the PWMVCC pin, for instance, by connecting it to VCC. Rev. 6.00 Feb 22, 2005 page 1009 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics Table 24-3 Permissible Output Currents Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Permissible output low current (per pin) All output pins except PWM1A to PWM1H, PWM2A to PWM2H PWM1A to PWM1H, PWM2A to PWM2H Symbol IOL Min. -- Typ. -- Max. 10 Unit mA Test condition IOL -- -- -- -- -- -- -- 25 30 40 80 mA mA mA mA Ta = 85C Ta = 25C Ta = -40C Permissible output high current (per pin) All output pins except PWM1A to PWM1H, PWM2A to PWM2H PWM1A to PWM1H, PWM2A to PWM2H Note: To protect chip reliability, do not exceed the output current values in table 24-3. Rev. 6.00 Feb 22, 2005 page 1010 of 1484 REJ09B0103-0600 Total of PWM1A to PWM1H, and PWM2A to PWM2H Permissible Total of all output pins output high excepting PWM1A to current (total) PWM1H, and PWM2A to PWM2H Total of PWM1A to PWM1H, and PWM2A to PWM2H Permissible Total of all output pins output low excepting PWM1A to current (total) PWM1H, and PWM2A to PWM2H IOL -- IOL -- -- -- -- -- -- -- -- 150 180 220 2.0 mA mA mA mA Ta = 85C Ta = 25C Ta = -40C -IOH -IOH -- -- -- -- -- -- -- 25 30 40 40 mA mA mA mA Ta = 85C Ta = 25C Ta = -40C -IOH -- -IOH -- -- -- -- -- -- 150 180 220 mA mA mA Ta = 85C Ta = 25C Ta = -40C Section 24 Electrical Characteristics 24.1.4 AC Characteristics Figure 24-2 show, the test conditions for the AC characteristics. 5V RL LSI output pin C RH C = 50 pF: Ports 10 to 13, A to F (In case of expansion bus control signal output pin setting) C = 30 pF: All ports RL = 2.4 k RH = 12 k Input/output timing measurement levels * Low level: 0.8 V * High level: 2.0 V Figure 24-2 Output Load Circuit Rev. 6.00 Feb 22, 2005 page 1011 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics (1) Clock Timing Table 24-4 lists the clock timing Table 24-4 Clock Timing Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition 20MHz Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Clock oscillator settling time at reset (crystal) Clock oscillator settling time in software standby (crystal) External clock output stabilization delay time 32-kHz clock oscillation settling time Subclock oscillator frequency Subclock (SUB) cycle time Symbol tcyc tCH tCL tCr tCf tOSC1 tOSC2 tDEXT tOSC3 fSUB tSUB Min. 50 15 15 -- -- 20 8 2 -- 32.768 30.5 Max. 250 -- -- 10 10 -- -- -- 2 Unit ns ns ns ns ns ms ms ms s kHz s Figure 24-10 Figure 23A-3 Figure 23B-3 Figure 24-10 Test Conditions Figure 24-9 Rev. 6.00 Feb 22, 2005 page 1012 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics (2) Control Signal Timing Table 24-5 lists the control signal timing. Table 24-5 Control Signal Timing Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item setup time pulse width Symbol tRESS tRESW tNMIS tNMIH tNMIW tIRQS tIRQH tIRQW Min. 200 20 150 10 200 150 10 200 Max. -- -- -- -- -- -- -- -- ns ns ns ns Unit ns tcyc ns Figure 24-12 Test Conditions Figure 24-11 SER SER QRI QRI QRI NMI setup time NMI hold time NMI pulse width (exiting software standby mode) setup time hold time pulse width (exiting software standby mode) Rev. 6.00 Feb 22, 2005 page 1013 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics (3) Bus Timing Table 24-6 lists the bus timing. Table 24-6 Bus Timing Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item Address delay time Address setup time Address hold time delay time delay time 1 delay time 2 Symbol tAD tAS tAH tASD tRSD1 tRSD2 tRDS tRDH tACC1 tACC2 tACC3 tACC4 tACC5 tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS tWDH Min. -- 0.5 x tcyc - 20 0.5 x tcyc - 15 -- -- -- 20 0 -- -- -- -- -- -- -- 1.0 x tcyc - 20 1.5 x tcyc - 20 -- 0.5 x tcyc - 20 0.5 x tcyc - 10 Max. 35 -- -- 20 20 20 -- -- 1.0 x tcyc - 48 1.5 x tcyc - 45 2.0 x tcyc - 45 2.5 x tcyc - 45 3.0 x tcyc - 50 20 20 -- -- 30 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 24-13 to Figure 24-17 RW RW RW RW DR DR SA Read data setup time Read data hold time Read data access time1 Read data access time2 Read data access time3 Read data access time 4 Read data access time 5 delay time 1 delay time 2 pulse width 1 pulse width 2 Write data delay time Write data setup time Write data hold time Rev. 6.00 Feb 22, 2005 page 1014 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics (4) Timing of On-Chip Supporting Modules Table 24-7 lists the timing of on-chip supporting modules. Table 24-7 Timing of On-Chip Supporting Modules Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item I/O port Output data delay time Output data delay time 2 Input data setup time Input data hold time PPG TPU Pulse output delay time Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width PWM SCI Single edge Both edges Asynchronous Synchronous tSCKW tSCKr tSCKf tTXD tRXS tRXH tTRGS Symbol tPWD tPWD2 tPRS tPRH tPOD tTOCD tTICS tTCKS tTCKWH tTCKWL tMPWMOD tScyc Min. -- -- 30 30 -- -- 30 30 1.5 2.5 -- 4 6 0.4 -- -- -- 50 50 50 Max. 50 50 -- -- 50 50 -- -- -- -- 50 -- -- 0.6 1.5 1.5 50 -- -- -- ns Figure 24-26 ns Figure 24-25 tScyc tcyc ns tcyc Figure 24-23 Figure 24-24 ns tcyc Figure 24-22 ns ns Figure 24-20 Figure 24-21 Unit ns Test Conditions Figure 24-18 Figure 24-19 Pulse output delay time Input clock cycle Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) A/D Trigger input setup time converter Rev. 6.00 Feb 22, 2005 page 1015 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics Condition Item HCAN* Transmit data delay time Receive data setup time Receive data hold time Symbol tHTXD tHRXS tHRXH Min. -- 100 100 Max. 100 -- -- Unit ns Test Conditions Figure 24-27 Note: * The HCAN input signal is asynchronous. However, its state is judged to have changed at the leading edge (two clock cycles) of the CK clock signal shown in figure 24-27. The HCAN output signal is also asynchronous. Its state changes based on the leading edge (two clock cycles) of the CK clock signal shown in figure 24-27. 24.1.5 A/D Conversion Characteristics Table 24-8 lists the A/D conversion characteristics. Table 24-8 A/D Conversion Characteristics Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization Absolute accuracy Min. 10 10 -- -- -- -- -- -- -- Typ. 10 -- -- -- -- -- -- 0.5 -- Max. 10 -- 20 5 3.5 3.5 3.5 -- 4.0 Unit bits s pF k LSB LSB LSB LSB LSB Rev. 6.00 Feb 22, 2005 page 1016 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.1.6 D/A Conversion Characteristics Table 24-9 shows the D/A conversion characteristics. Table 24-9 D/A Conversion Characteristics Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item Resolution Conversion time Absolute accuracy Min. 8 -- -- -- Typ. 8 -- 1.5 -- Max. 8 10 2.0 1.5 Unit bits s LSB LSB 20-pF capacitive load 2-M resistive load 4-M resistive load Test Conditions Rev. 6.00 Feb 22, 2005 page 1017 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.1.7 Flash Memory Characteristics Table 24-10 shows the flash memory characteristics. Table 24-10 Flash Memory Characteristics Conditions: VCC =4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS, AVSS = 0 V Ta = 0 to +75C (Programming/erasing operating temperature range: regular specification) Item 124 Programming time* * * Symbol tP tE NWEC tsswe tspsu tsp30 tsp200 tsp10 Min. -- -- -- 1 50 28 198 8 Typ. 10 100 -- 1 50 30 200 10 Max. 200 1200 100 -- -- 32 202 12 Unit ms/ 128 bytes ms/block Times s s s s s Test Condition Erase time*1 *3 *5 Reprogramming count Programming Wait time after SWE bit setting *1 Wait time after PSU bit setting *1 Wait time after P bit setting *1 *4 Programming time wait Programming time wait Additionalprogramming time wait Wait time after P bit clear *1 Wait time after PSU bit clear *1 1 Wait time after PV bit setting * tcp tcpsu tspv tspvr tcpv tcswe 5 5 4 2 2 100 -- 1 100 10 10 10 20 5 5 4 2 2 100 -- 1 100 10 10 10 20 -- -- -- -- -- -- 1000 -- -- 100 -- -- -- s s s s s s Times s s ms s s s Erase time wait Wait time after H'FF dummy write*1 Wait time after PV bit clear *1 Wait time after SWE bit clear*1 Wait time after SWE bit setting *1 Wait time after ESU bit setting * Wait time after E bit setting *1 *5 1 Wait time after E bit clear * 1 Wait time after ESU bit clear * 1 14 Maximum programming count* * N Erase tsswe tsesu tse tce tcesu tsev Wait time after EV bit setting *1 Rev. 6.00 Feb 22, 2005 page 1018 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics Item Erase Wait time after H'FF dummy write*1 Wait time after EV bit clear * Maximum erase count*1 *5 1 Symbol tsevr tcev tcswe N Min. 2 4 100 12 Typ. 2 4 100 -- Max. -- -- -- 120 Unit s s s Times Test Condition Wait time after SWE bit clear*1 Notes: 1. Make each time setting in accordance with the program/program-verify flowchart or erase/erase-verify flowchart. 2. Programming time per 128 bytes (Shows the total period for which the P-bit in the flash memory control register (FLMCR1) is set. It does not include the programming verification time) 3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time) 4. To specify the maximum programming time value (tP (max.)) in the 128-byte programming algorithm, set the max. value (1000) for the maximum programming count (N). The wait time after P bit setting should be changed as follows according to the value of the programming counter (n). Programming counter (n) = 1 to 6: tsp30 = 30 s Programming counter (n) = 7 to 1000: tsp200 = 200 s [In additional programming] Programming counter (n)= 1 to 6: tsp10 = 10 s 5. For the maximum erase time (tE (max.), the following relationship applies between the wait time after E bit setting (tse) and the maximum erase count (N): tE (max.) = Wait time after E bit setting (tse) x maximum erase count (N) To set the maximum erase time, the values of (tse) and (N) should be set so as to satisfy the above formula. Examples: When tse = 100 [ms], N = 12 times When tse = 10 [ms], N = 120 times Rev. 6.00 Feb 22, 2005 page 1019 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.2 24.2.1 H8S/2638 Group Electrical Characteristics Absolute Maximum Ratings Table 24-11 lists the absolute maximum ratings. Table 24-11 Absolute Maximum Ratings Item Power supply voltage Input voltage (OSC1, OSC2) Input voltage (XTAL, EXTAL) Input voltage (ports 4 and 9) Input voltage (ports H and J) Symbol VCC Vin Vin Vin Vin Value -0.3 to +7.0 -0.3 +4.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to PWMVCC +0.3 -0.3 to VCC +0.3 Unit V V V V V V Input voltage (except XTAL, Vin EXTAL, OSC1, OSC2, ports 4, 9, H and J) Reference voltage Analog power supply voltage Analog input voltage Operating temperature Storage temperature Vref AVCC VAN Topr Tstg -0.3 to AVCC +0.3 -0.3 to +7.0 -0.3 to AVCC +0.3 Regular specifications: -20 to +75 Wide-range specifications: -40 to +85 -55 to +125 V V V C C C Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded. Rev. 6.00 Feb 22, 2005 page 1020 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.2.2 Power Supply Voltage and Operating Frequency Range Power supply voltage and operating frequency ranges (shaded areas) are shown in figure 24-3. Operating range of high-speed, medium-speed and sleep modes 24 20 Frequency (MHz) 16 12 8 4 0 3 3.5 4 4.5 5 5.5 6 Power supply voltage (V) Operating range of watch*, sub-active* and sub-sleep* modes 32.768 Frequency (MHz) 0 3 3.5 4 4.5 5 5.5 6 Power supply voltage (V) Note: * The watch, subactive, and subsleep modes are available in the U-mask and W-mask versions only. Figure 24-3 Power Supply Voltage and Operating Ranges Rev. 6.00 Feb 22, 2005 page 1021 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.2.3 DC Characteristics Table 24-12 lists the DC characteristics. Table 24-13 lists the permissible output currents. Table 24-12 DC Characteristics Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)*1 *6 Item Schmitt trigger input voltage Input high voltage Symbol IRQ0 to IRQ5 VT VT , , NMI, FWE, MD2 to MD0 - + + - Min. 1.0 -- 0.4 VCC - 0.7 Typ. -- -- -- -- Max. -- VCC x 0.7 -- VCC + 0.3 Unit V Test Conditions VT - VT VIH V Rev. 6.00 Feb 22, 2005 page 1022 of 1484 REJ09B0103-0600 YBTS SER Input low voltage YBTS SER EXTAL Ports H, J HRxD0, HRxD1 EXTAL Ports H, J HRxD0, HRxD1 Ports 4, 9 VCC x 0.7 2.2 VCC x 0.8 -- -- -- VCC + 0.3 VCC + 0.3 VCC + 0.3 PWMVCC + 0.3 VCC + 0.3 AVCC + 0.3 0.5 V Ports 1, 3, F Ports A to E PWMVCC x -- 0.8 2.2 -- Ports 4 and 9 , , NMI, FWE, MD2 to MD0 Ports 1, 3, F Ports A to E VIL AVCC x 0.7 -- -0.3 -- -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -- -- -- -- -- -- 0.8 0.8 VCC x 0.2 PWMVCC x 0.2 VCC x 0.2 AVCC x 0.2 Section 24 Electrical Characteristics Item Output high voltage Ports 1, 3, A to F, H,J HTxD0, HTxD1 (excluding P34 and 7 P35* ) P34, P35*7 Ports 1, 3, A to F, H, J HTxD0, HTxD1 (excluding P34 and 7 P35* ) PWM1A to PWM1H, PWM2A to PWM2H Output low voltage All output pins VOL except PWM1A to PWM1H, PWM2A to PWM2H PWM1A to PWM1H, PWM2A to PWM2H Symbol VOH Min. VCC - 0.5 Typ. -- Max. -- Unit V Test Conditions IOH = -200 A VCC - 2.5 3.5 -- -- -- -- IOH = -100 A IOH = -1 mA PWMVCC - 0.5 -- IOH = -15 mA -- -- 0.4 V IOL = 1.6 mA -- -- 0.5 V IOL = 15 mA Three-state leakage current (off state) IMN YBTS SER Ports 4, 9 Input leakage current | Iin | -- -- -- -- -- -- -- -- 1.0 1.0 1.0 1.0 1.0 A , , MD2 to MD0 HRxD0, HRxD1, FWE Vin = 0.5 V to VCC - 0.5 V Vin = 0.5 V to AVCC - 0.5 V A Vin = 0.5 V to VCC - 0.5 V Ports 1, 3, A to F, H, J HTxD0, HTxD1 ITSI -- Rev. 6.00 Feb 22, 2005 page 1023 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics Item MOS input Ports A to E pull-up current Symbol -IP Cin Min. 50 -- -- -- -- -- -- Typ. Max. 300 30 30 15 Unit A pF Test Conditions Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25C Current dissipation*2 Normal operation Sleep mode All modules stopped Mediumspeed mode (/32) Subactive 5 mode* Subsleep mode*5 Watch mode*5 Standby mode*3 Analog power supply current Reference current During A/D and D/A conversion Idle During A/D and D/A conversion Idle RAM standby voltage Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage between 4.5 V and 5.5 V to the AVCC and Vref pins by connecting them to VCC, for instance. Set Vref AVCC. 2. Current dissipation values are for VIH (min.) = VCC - 0.5 V, VIL (max.) = 0.5 V with all output pins unloaded and the on-chip pull-up resistors in the off state. 3. The values are for VRAM VCC < 3.0 V, VIH (min.) = VCC x 0.9, and VIL (max.) = 0.3 V. Rev. 6.00 Feb 22, 2005 page 1024 of 1484 REJ09B0103-0600 SER SER NMI All input pins except and NMI Input capacitance ICC*4 -- -- -- -- 75 65 57 49 90 80 -- -- mA f = 20 MHz mA f = 20 MHz (reference value) -- 130 220 A Using 32.768 kHz crystal resonator -- -- -- -- AlCC -- 80 30 2.0 -- 1.0 160 60 5.0 20 2.0 mA A Ta 50C 50C < Ta AVCC = 5.0 V -- AlCC -- 0.1 4.0 5.0 5.0 A mA Vref = 5.0 V -- VRAM 2.0 0.1 -- 5.0 -- A V Section 24 Electrical Characteristics 4. ICC depends on VCC and f as follows: ICC (max.) = 30 (mA) + 0.54 (mA/(MHz x V)) x VCC x f (normal operation) ICC (max.) = 30 (mA) + 0.45 (mA/(MHz x V)) x VCC x f (sleep mode) 5. The watch, subactive, and subsleep modes are available in the U-mask and W-mask versions only. See section 22A.7, Subclock Oscillator, for the method of fixing pins OSC1 and OSC2. 6. If the motor-control PWM timer is not used, do not leave the PMWVCC, or PMWVSS pins open. If the motor-control PWM timer is not used, apply a voltage of between 4.5 and 5.5 V to the PWMVCC pin, for instance, by connecting it to VCC. 7. The characteristics of pins 34 and 35 apply to the W-mask version. Rev. 6.00 Feb 22, 2005 page 1025 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics Table 24-13 Permissible Output Currents Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Permissible output low current (per pin) All output pins except PWM1A to PWM1H, PWM2A to PWM2H PWM1A to PWM1H, PWM2A to PWM2H Symbol IOL Min. -- Typ. -- Max. 10 Unit mA Test condition IOL -- -- -- -- -- -- -- 25 30 40 80 mA mA mA mA Ta = 85C Ta = 25C Ta = -40C Permissible output high current (per pin) All output pins except PWM1A to PWM1H, PWM2A to PWM2H PWM1A to PWM1H, PWM2A to PWM2H Permissible Total of all output pins output high excepting PWM1A to current (total) PWM1H, and PWM2A to PWM2H Total of PWM1A to PWM1H, - IOH and PWM2A to PWM2H Note: To protect chip reliability, do not exceed the output current values in table 24-13. Rev. 6.00 Feb 22, 2005 page 1026 of 1484 REJ09B0103-0600 Total of PWM1A to PWM1H, and PWM2A to PWM2H Permissible Total of all output pins output low excepting PWM1A to current (total) PWM1H, and PWM2A to PWM2H IOL -- IOL -- -- -- -- -- -- -- -- 150 180 220 2.0 mA mA mA mA Ta = 85C Ta = 25C Ta = -40C -IOH -IOH -- -- -- -- -- -- -- 25 30 40 40 mA mA mA mA Ta = 85C Ta = 25C Ta = -40C - IOH -- -- -- -- -- -- -- 150 180 220 mA mA mA Ta = 85C Ta = 25C Ta = -40C Section 24 Electrical Characteristics Table 24-14 Bus Drive Characteristics [Option]* Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Applicable Pins: SCL1-0, SDA1-0 Item Schmitt trigger input voltage Symbol VT VT - + + - Min. 1.0 -- 0.4 - VCC x 0.7 - 0.5 -- -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- Max. -- VCC x 0.7 -- VCC + 0.5 VCC x 0.3 0.7 0.4 0.4 20 1.0 250 Unit V Test Conditions VT - VT Input high voltage Input low voltage Output low voltage VIH VIL VOL VCC = 4.5 V to 5.5 V V V V IOL = 8 mA, VCC = 4.5 V to 5.5 V IOL = 3 mA, VCC = 4.5 V to 5.5 V IOL = 1.6 mA, VCC = 3.3 V to 5.5 V pF A ns Vin = 0 V, f = 1 MHz, Ta = 25 C Vin = 0.5 V to VCC - 5.5 V Input capacitance Three-state leakage current (off state) SCL, SDA, output fall time Cin ITSI tof -- -- 20 + 0.1Cb Note: * Available when using I2C bus interface (the W-mask version only). Rev. 6.00 Feb 22, 2005 page 1027 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.2.4 AC Characteristics Figure 24-4 show, the test conditions for the AC characteristics. 5V RL LSI output pin C RH C = 50 pF: Ports 10 to 13, A to F (In case of expansion bus control signal output pin setting) C = 30 pF: All ports RL = 2.4 k RH = 12 k Input/output timing measurement levels * Low level: 0.8 V * High level: 2.0 V Figure 24-4 Output Load Circuit Rev. 6.00 Feb 22, 2005 page 1028 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics (1) Clock Timing Table 24-15 lists the clock timing Table 24-15 Clock Timing Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition 20MHz Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Clock oscillator settling time at reset (crystal) Clock oscillator settling time in software standby (crystal) External clock output stabilization delay time 32-kHz clock oscillation settling time Subclock oscillator frequency Subclock (SUB) cycle time Symbol tcyc tCH tCL tCr tCf tOSC1 tOSC2 tDEXT tOSC3 fSUB tSUB Min. 50 15 15 -- -- 20 8 2 -- 32.768 30.5 Max. 250 -- -- 10 10 -- -- -- 2 Unit ns ns ns ns ns ms ms ms s kHz s Figure 24-10 Figure 23A-3 Figure 23B-3 Figure 24-10 Test Conditions Figure 24-9 Rev. 6.00 Feb 22, 2005 page 1029 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics (2) Control Signal Timing Table 24-16 lists the control signal timing. Table 24-16 Control Signal Timing Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item setup time pulse width Symbol tRESS tRESW tNMIS tNMIH tNMIW tIRQS tIRQH tIRQW Min. 200 20 150 10 200 150 10 200 Max. -- -- -- -- -- -- -- -- ns ns ns ns Unit ns tcyc ns Figure 24-12 Test Conditions Figure 24-11 SER SER QRI QRI QRI NMI setup time NMI hold time NMI pulse width (exiting software standby mode) setup time hold time pulse width (exiting software standby mode) Rev. 6.00 Feb 22, 2005 page 1030 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics (3) Bus Timing Table 24-17 lists the bus timing. Table 24-17 Bus Timing Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item Address delay time Address setup time Address hold time delay time delay time 1 delay time 2 Symbol tAD tAS tAH tASD tRSD1 tRSD2 tRDS tRDH tACC1 tACC2 tACC3 tACC4 tACC5 tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS tWDH Min. -- 0.5 x tcyc - 20 0.5 x tcyc - 15 -- -- -- 20 0 -- -- -- -- -- -- -- 1.0 x tcyc - 20 1.5 x tcyc - 20 -- 0.5 x tcyc - 20 0.5 x tcyc - 10 Max. 35 -- -- 20 20 20 -- -- 1.0 x tcyc - 48 1.5 x tcyc - 45 2.0 x tcyc - 45 2.5 x tcyc - 45 3.0 x tcyc - 50 20 20 -- -- 30 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 24-13 to Figure 24-17 RW RW RW RW DR DR SA Read data setup time Read data hold time Read data access time1 Read data access time2 Read data access time3 Read data access time 4 Read data access time 5 delay time 1 delay time 2 pulse width 1 pulse width 2 Write data delay time Write data setup time Write data hold time Rev. 6.00 Feb 22, 2005 page 1031 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics (4) Timing of On-Chip Supporting Modules Table 24-18 lists the timing of on-chip supporting modules. Table 24-18 Timing of On-Chip Supporting Modules Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item I/O port Output data delay time Output data delay time 2 Input data setup time Input data hold time PPG TPU Pulse output delay time Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width PWM SCI Single edge Both edges Symbol tPWD tPWD2 tPRS tPRH tPOD tTOCD tTICS tTCKS tTCKWH tTCKWL tMPWMOD Min. -- -- 30 30 -- -- 30 30 1.5 2.5 -- 4 6 tSCKW tSCKr tSCKf tTXD tRXS tRXH tTRGS 0.4 -- -- -- 50 50 50 Max. 50 50 -- -- 50 50 -- -- -- -- 50 -- -- 0.6 1.5 1.5 50 -- -- -- ns Figure 24-26 ns Figure 24-25 tScyc tcyc ns tcyc Figure 24-23 Figure 24-24 ns tcyc Figure 24-22 ns ns Figure 24-20 Figure 24-21 Unit ns Test Conditions Figure 24-18 Figure 24-19 Pulse output delay time Input clock cycle Synchronous Asynchronous tScyc Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) A/D Trigger input setup time converter Rev. 6.00 Feb 22, 2005 page 1032 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics Condition Item HCAN* Transmit data delay time Receive data setup time Receive data hold time Symbol tHTXD tHRXS tHRXH Min. -- 100 100 Max. 100 -- -- Unit ns Test Conditions Figure 24-27 Note: * The HCAN input signal is asynchronous. However, its state is judged to have changed at the leading edge (two clock cycles) of the CK clock signal shown in figure 24-27. The HCAN output signal is also asynchronous. Its state changes based on the leading edge (two clock cycles) of the CK clock signal shown in figure 24-27. Table 24-19 I2C Bus Timing [Option]*1 Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, = 5 MHz to maximum operating frequency, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rise time SCL, SDA input fall time SCL, SDA input spike pulse elimination time SDA input bus free time Start condition input hold time Retransmission start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load 2 Symbol tSCL tSCLH tSCLL tSr tSf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb Min. 12tcyc 3tcyc 5tcyc -- -- -- 5tcyc 3tcyc 3tcyc 3tcyc 0.5tcyc 0 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- Unit ns ns ns Notes Figure 24-28 7.5tcyc*2 ns 300 1tcyc -- -- -- -- -- -- 400 ns ns ns ns ns ns ns ns pF Notes: 1. Available when using I C bus interface (the W-mask version only). 2. 17.5tcyc can be set according to the clock selected for use by the I2C module. For details, see section 15.4, Usage Notes. Rev. 6.00 Feb 22, 2005 page 1033 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.2.5 A/D Conversion Characteristics Table 24-20 lists the A/D conversion characteristics. Table 24-20 A/D Conversion Characteristics Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization Absolute accuracy Min. 10 10 -- -- -- -- -- -- -- Typ. 10 -- -- -- -- -- -- 0.5 -- Max. 10 -- 20 5 3.5 3.5 3.5 -- 4.0 Unit bits s pF k LSB LSB LSB LSB LSB Rev. 6.00 Feb 22, 2005 page 1034 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.2.6 D/A Conversion Characteristics Table 24-21 shows the D/A conversion characteristics. Table 24-21 D/A Conversion Characteristics Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item Resolution Conversion time Absolute accuracy Min. 8 -- -- -- Typ. 8 -- 1.5 -- Max. 8 10 2.0 1.5 Unit bits s LSB LSB 20-pF capacitive load 2-M resistive load 4-M resistive load Test Conditions Rev. 6.00 Feb 22, 2005 page 1035 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.2.7 Flash Memory Characteristics Table 24-22 shows the flash memory characteristics. Table 24-22 Flash Memory Characteristics Conditions: VCC =4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS, AVSS = 0 V Ta = 0 to +75C (Programming/erasing operating temperature range: regular specification) Item 124 Programming time* * * Symbol tP tE NWEC tsswe tspsu tsp30 tsp200 tsp10 Min. -- -- -- 1 50 28 198 8 Typ. 10 100 -- 1 50 30 200 10 Max. 200 1200 100 -- -- 32 202 12 Unit ms/ 128 bytes ms/block Times s s s s s Test Condition Erase time*1 *3 *5 Reprogramming count Programming Wait time after SWE bit setting *1 Wait time after PSU bit setting *1 Wait time after P bit setting *1 *4 Programming time wait Programming time wait Additionalprogramming time wait Wait time after P bit clear *1 Wait time after PSU bit clear *1 1 Wait time after PV bit setting * tcp tcpsu tspv tspvr tcpv tcswe 5 5 4 2 2 100 -- 1 100 10 10 10 20 5 5 4 2 2 100 -- 1 100 10 10 10 20 -- -- -- -- -- -- 1000 -- -- 100 -- -- -- s s s s s s Times s s ms s s s Erase time wait Wait time after H'FF dummy write*1 Wait time after PV bit clear *1 Wait time after SWE bit clear*1 Wait time after SWE bit setting *1 Wait time after ESU bit setting * Wait time after E bit setting *1 *5 1 Wait time after E bit clear * 1 Wait time after ESU bit clear * 1 14 Maximum programming count* * N Erase tsswe tsesu tse tce tcesu tsev Wait time after EV bit setting *1 Rev. 6.00 Feb 22, 2005 page 1036 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics Item Erase Wait time after H'FF dummy write*1 Wait time after EV bit clear *1 1 Wait time after SWE bit clear* 15 Maximum erase count* * Symbol tsevr tcev tcswe N Min. 2 4 100 12 Typ. 2 4 100 -- Max. -- -- -- 120 Unit s s s Times Test Condition Notes: 1. Make each time setting in accordance with the program/program-verify flowchart or erase/erase-verify flowchart. 2. Programming time per 128 bytes (Shows the total period for which the P-bit in the flash memory control register (FLMCR1) is set. It does not include the programming verification time) 3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time) 4. To specify the maximum programming time value (tP (max.)) in the 128-byte programming algorithm, set the max. value (1000) for the maximum programming count (N). The wait time after P bit setting should be changed as follows according to the value of the programming counter (n). Programming counter (n) = 1 to 6: tsp30 = 30 s Programming counter (n) = 7 to 1000: tsp200 = 200 s [In additional programming] Programming counter (n)= 1 to 6: tsp10 = 10 s 5. For the maximum erase time (tE (max.)), the following relationship applies between the wait time after E bit setting (tse) and the maximum erase count (N): tE (max.) = Wait time after E bit setting (tse) x maximum erase count (N) To set the maximum erase time, the values of (tse) and (N) should be set so as to satisfy the above formula. Examples: When tse = 100 [ms], N = 12 times When tse = 10 [ms], N = 120 times Rev. 6.00 Feb 22, 2005 page 1037 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.3 24.3.1 H8S/2639 Group, H8S/2635 Group Electrical Characteristics Absolute Maximum Ratings Table 24-23 lists the absolute maximum ratings. Table 24-23 Absolute Maximum Ratings Item Power supply voltage Input voltage (XTAL*, EXTAL) Input voltage (ports 4 and 9) Input voltage (ports H and J) Input voltage (except XTAL, EXTAL, ports 4, 9, H and J) Reference voltage Analog power supply voltage Analog input voltage Operating temperature Storage temperature Symbol VCC Vin Vin Vin Vin Vref AVCC VAN Topr Tstg Value -0.3 to +7.0 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to PWMVCC +0.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to +7.0 -0.3 to AVCC +0.3 Regular specifications: -20 to +75 Wide-range specifications: -40 to +85 -55 to +125 Unit V V V V V V V V C C C Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded. Note: * In the case of the H8S/2635 Group, do not input a signal to the XTAL pin. Rev. 6.00 Feb 22, 2005 page 1038 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.3.2 Power Supply Voltage and Operating Frequency Range Power supply voltage and operating frequency ranges (shaded areas) are shown in figure 24-5. Operating range of high-speed, medium-speed and sleep modes 24 20 Frequency (MHz)*1 16 12 8 4 0 3 3.5 4 4.5 5 5.5 6 Power supply voltage (V) Operating range of watch, sub-active and sub-sleep modes SUB Frequency (MHz)*2 0 3 3.5 4 4.5 5 5.5 6 Power supply voltage (V) Notes: 1. An input clock frequency of 4 to 5 MHz should be used. For operation at 20 MHz, input a 5 MHz clock and use the PLL to multiply it (x4). 2. The maximum internal SUB frequency is 39.06 kHz (5 MHz/128). Figure 24-5 Power Supply Voltage and Operating Ranges Rev. 6.00 Feb 22, 2005 page 1039 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.3.3 DC Characteristics Table 24-24 lists the DC characteristics. Table 24-25 lists the permissible output currents. Table 24-24 DC Characteristics Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)*1 *5 Item Schmitt trigger input voltage Input high voltage Symbol IRQ0 to IRQ5 VT VT , , NMI, FWE, MD2 to MD0 - + + - Min. 1.0 -- 0.4 VCC - 0.7 Typ. -- -- -- -- Max. -- VCC x 0.7 -- VCC + 0.3 Unit V Test Conditions VT - VT VIH V Rev. 6.00 Feb 22, 2005 page 1040 of 1484 REJ09B0103-0600 YBTS SER Input low voltage YBTS SER EXTAL Ports H, J HRxD0, HRxD1*7 EXTAL Ports H, J HRxD0, HRxD1*7 Ports 4, 9 VCC x 0.7 2.2 VCC x 0.8 -- -- -- VCC + 0.3 VCC + 0.3 VCC + 0.3 PWMVCC + 0.3 VCC + 0.3 AVCC + 0.3 0.5 V Ports 1, 3, F Ports A to E PWMVCC x -- 0.8 2.2 -- Ports 4 and 9 , , NMI, FWE, MD2 to MD0 Ports 1, 3, F Ports A to E VIL AVCC x 0.7 -- -0.3 -- -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -- -- -- -- -- -- 0.8 0.8 VCC x 0.2 PWMVCC x 0.2 VCC x 0.2 AVCC x 0.2 Section 24 Electrical Characteristics Item Output high voltage Ports 1, 3, A to F, H,J HTxD0, HTxD1*7 (excluding P34 and 6 P35* ) P34, P35*6 Ports 1, 3, A to F, H, J HTxD0, 7 HTxD1* (excluding P34 and 6 P35* ) PWM1A to PWM1H, PWM2A to PWM2H Output low voltage All output pins VOL except PWM1A to PWM1H, PWM2A to PWM2H PWM1A to PWM1H, PWM2A to PWM2H Symbol VOH Min. VCC - 0.5 Typ. -- Max. -- Unit V Test Conditions IOH = -200 A VCC - 2.5 3.5 -- -- -- -- IOH = -100 A IOH = -1 mA PWMVCC - -- 0.5 -- IOH = -15 mA -- -- 0.4 V IOL = 1.6 mA -- -- 0.5 V IOL = 15 mA HRxD0, HRxD1*7, FWE Ports 4, 9 Three-state leakage current (off state) Ports 1, 3, A to F, H, J HTxD0, HTxD1*7 ITSI IMN YBTS SER Input leakage current | Iin | -- -- -- -- -- -- 1.0 1.0 1.0 A , , MD2 to MD0 Vin =0.5 V to VCC - 0.5 V -- -- -- -- 1.0 1.0 A Vin = 0.5 V to AVCC - 0.5 V Vin =0.5 V to VCC - 0.5 V Rev. 6.00 Feb 22, 2005 page 1041 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics Item MOS input Ports A to E pull-up current Symbol -IP Cin Min. 50 -- -- -- Typ. -- -- -- -- Max. 300 30 30 15 Unit A pF Test Conditions Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25C Current dissipation*2 (H8S/2639 Group) Normal operation Sleep mode All modules stopped Mediumspeed mode (/32) Subactive mode Subsleep mode Watch mode Standby 3 mode* Current dissipation*2 (H8S/2635 Group) Normal operation Sleep mode All modules stopped Mediumspeed mode (/32) Subactive mode Subsleep mode Watch mode Standby mode Rev. 6.00 Feb 22, 2005 page 1042 of 1484 REJ09B0103-0600 SER SER NMI All input pins except and NMI Input capacitance ICC*4 -- -- -- -- 75 65 57 49 90 80 -- -- mA f = 20 MHz mA f = 20 MHz (reference value) -- -- -- -- -- ICC*8 -- -- -- -- 0.7 0.7 0.6 2.0 -- 60 50 40 45 1.0 1.0 1.0 5.0 20 65 55 -- -- mA Subclock (using 4.19 MHz crystal oscillator) A mA Ta 50C 50C < Ta f = 20 MHz mA f = 20 MHz (reference value) -- -- -- -- -- 0.35 0.3 0.25 2.0 -- 0.4 0.35 0.3 5.0 20 mA Subclock (using 5.0 MHz crystal oscillator) A Ta 50C 50C < Ta Section 24 Electrical Characteristics Item Analog power supply current Reference current During A/D and D/A*7 conversion Idle During A/D and D/A*7 conversion Idle RAM standby voltage VRAM AlCC Symbol AlCC Min. -- Typ. 1.0 Max. 2.0 Unit mA Test Conditions AVCC = 5.0 V -- -- 0.1 4.0 5.0 5.0 A mA Vref = 5.0 V -- 2.0 0.1 -- 5.0 -- A V Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage between 4.5 V and 5.5 V to the AVCC and Vref pins by connecting them to VCC, for instance. Set Vref AVCC. 2. Current dissipation values are for VIH (min.) = VCC - 0.5 V, VIL (max.) = 0.5 V with all output pins unloaded and the on-chip pull-up resistors in the off state. 3. The values are for VRAM VCC < 3.0 V, VIH (min.) = VCC x 0.9, and VIL (max.) = 0.3 V. 4. ICC depends on VCC and f as follows: ICC (max.) = 30 (mA) + 0.54 (mA/(MHz x V)) x VCC x f (normal operation) ICC (max.) = 30 (mA) + 0.45 (mA/(MHz x V)) x VCC x f (sleep mode) 5. If the motor-control PWM timer is not used, do not leave the PMWVCC, or PMWVSS pins open. If the motor-control PWM timer is not used, apply a voltage of between 4.5 and 5.5 V to the PWMVCC pin, for instance, by connecting it to VCC. 6. The characteristics of pins 34 and 35 apply to the W-mask version. 7. The HTxD1, HRxD1 pins, and D/A converter are not available in the H8S/2635 Group. 8. ICC depends on VCC and f as follows: ICC (max.) = 17 (mA) + 0.43 (mA/(MHz x V)) x VCC x f (normal operation) ICC (max.) = 17 (mA) + 0.34 (mA/(MHz x V)) x VCC x f (sleep mode) Rev. 6.00 Feb 22, 2005 page 1043 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics Table 24-25 Permissible Output Currents Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Permissible output low current (per pin) All output pins except PWM1A to PWM1H, PWM2A to PWM2H PWM1A to PWM1H, PWM2A to PWM2H Symbol IOL Min. -- Typ. -- Max. 10 Unit mA Test condition IOL -- -- -- -- -- -- -- 25 30 40 80 mA mA mA mA Ta = 85C Ta = 25C Ta = -40C Permissible output high current (per pin) All output pins except PWM1A to PWM1H, PWM2A to PWM2H PWM1A to PWM1H, PWM2A to PWM2H Permissible Total of all output pins output high excepting PWM1A to current (total) PWM1H, and PWM2A to PWM2H Total of PWM1A to PWM1H, - IOH and PWM2A to PWM2H Note: To protect chip reliability, do not exceed the output current values in table 24-25. Rev. 6.00 Feb 22, 2005 page 1044 of 1484 REJ09B0103-0600 Total of PWM1A to PWM1H, and PWM2A to PWM2H Permissible Total of all output pins output low excepting PWM1A to current (total) PWM1H, and PWM2A to PWM2H IOL -- IOL -- -- -- -- -- -- -- -- 150 180 220 2.0 mA mA mA mA Ta = 85C Ta = 25C Ta = -40C -IOH -IOH -- -- -- -- -- -- -- 25 30 40 40 mA mA mA mA Ta = 85C Ta = 25C Ta = -40C - IOH -- -- -- -- -- -- -- 150 180 220 mA mA mA Ta = 85C Ta = 25C Ta = -40C Section 24 Electrical Characteristics Table 24-26 Bus Drive Characteristics [Option]* Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Applicable Pins: SCL1 to 0, SDA1 to 0 Item Schmitt trigger input voltage Input high voltage Input low voltage Output low voltage Symbol VT VT+ + - VT - VT VIH VIL VOL - Min. 1.0 -- 0.4 - VCC x 0.7 - 0.5 -- -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- Max. -- VCC x 0.7 -- VCC + 0.5 VCC x 0.3 0.7 0.4 0.4 20 1.0 250 Unit V Test Conditions VCC = 4.5 V to 5.5 V V V V Input capacitance Three-state leakage current (off state) SCL, SDA, output fall time Cin ITSI tof -- -- 20 + 0.1Cb pF A ns IOL = 8 mA, VCC = 4.5 V to 5.5 V IOL = 3 mA, VCC = 4.5 V to 5.5 V IOL = 1.6 mA, VCC = 3.3 V to 5.5 V Vin = 0 V, f = 1MHz, Ta = 25 C Vin = 0.5 V to VCC - 5.5 V Note: * Available when using the I2C bus interface (the W-mask version only). Rev. 6.00 Feb 22, 2005 page 1045 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.3.4 AC Characteristics Figure 24-6 show, the test conditions for the AC characteristics. 5V RL LSI output pin C RH C = 50 pF: Ports 10 to 13, A to F (In case of expansion bus control signal output pin setting) C = 30 pF: All ports RL = 2.4 k RH = 12 k Input/output timing measurement levels * Low level: 0.8 V * High level: 2.0 V Figure 24-6 Output Load Circuit Rev. 6.00 Feb 22, 2005 page 1046 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics (1) Clock Timing Table 24-27 lists the clock timing Table 24-27 Clock Timing Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition 20MHz Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Clock oscillator settling time at reset (crystal) Clock oscillator settling time in software standby (crystal) (H8S/2639 Group) Clock oscillator settling time in software standby (crystal) (H8S/2635 Group) External clock output stabilization delay time Subclock oscillator frequency Subclock (SUB) cycle time tDEXT fSUB tSUB Symbol tcyc tCH tCL tCr tCf tOSC1 tOSC2 Min. 50 15 15 -- -- 20 8 Max. 250 -- -- 10 10 -- -- Unit ns ns ns ns ns ms ms Figure 24-10 Figure 23A-3 Figure 23B-3 Test Conditions Figure 24-9 12 -- 2 31.25 25.6 -- 39.6 32.0 ms kHz s Figure 24-10 Rev. 6.00 Feb 22, 2005 page 1047 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics (2) Control Signal Timing Table 24-28 lists the control signal timing. Table 24-28 Control Signal Timing Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item setup time pulse width Symbol tRESS tRESW tNMIS tNMIH tNMIW tIRQS tIRQH tIRQW Min. 200 20 150 10 200 150 10 200 Max. -- -- -- -- -- -- -- -- ns ns ns ns Unit ns tcyc ns Figure 24-12 Test Conditions Figure 24-11 SER SER QRI QRI QRI NMI setup time NMI hold time NMI pulse width (exiting software standby mode) setup time hold time pulse width (exiting software standby mode) Rev. 6.00 Feb 22, 2005 page 1048 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics (3) Bus Timing Table 24-29 lists the bus timing. Table 24-29 Bus Timing Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item Address delay time Address setup time Address hold time delay time delay time 1 delay time 2 Symbol tAD tAS tAH tASD tRSD1 tRSD2 tRDS tRDH tACC1 tACC2 tACC3 tACC4 tACC5 tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS tWDH Min. -- 0.5 x tcyc - 20 0.5 x tcyc - 15 -- -- -- 20 0 -- -- -- -- -- -- -- 1.0 x tcyc - 20 1.5 x tcyc - 20 -- 0.5 x tcyc - 20 0.5 x tcyc - 10 Max. 35 -- -- 20 20 20 -- -- 1.0 x tcyc - 48 1.5 x tcyc - 45 2.0 x tcyc - 45 2.5 x tcyc - 45 3.0 x tcyc - 50 20 20 -- -- 30 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 24-13 to Figure 24-17 RW RW RW RW DR DR SA Read data setup time Read data hold time Read data access time1 Read data access time2 Read data access time3 Read data access time 4 Read data access time 5 delay time 1 delay time 2 pulse width 1 pulse width 2 Write data delay time Write data setup time Write data hold time Rev. 6.00 Feb 22, 2005 page 1049 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics (4) Timing of On-Chip Supporting Modules Table 24-30 lists the timing of on-chip supporting modules. Table 24-30 Timing of On-Chip Supporting Modules Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item I/O port Output data delay time Output data delay time 2 Input data setup time Input data hold time PPG TPU *1 Pulse output delay time Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width PWM SCI Single edge Both edges Asynchronous Synchronous tSCKW tSCKr tSCKf tTXD tRXS tRXH tTRGS Symbol tPWD tPWD2 tPRS tPRH tPOD tTOCD tTICS tTCKS tTCKWH tTCKWL tMPWMOD tScyc Min. -- -- 30 30 -- -- 30 30 1.5 2.5 -- 4 6 0.4 -- -- -- 50 50 50 Max. 50 50 -- -- 50 50 -- -- -- -- 50 -- -- 0.6 1.5 1.5 50 -- -- -- ns Figure 24-26 ns Figure 24-25 tScyc tcyc ns tcyc Figure 24-23 Figure 24-24 ns tcyc Figure 24-22 ns ns Figure 24-20 Figure 24-21 Unit ns Test Conditions Figure 24-18 Figure 24-19 Pulse output delay time Input clock cycle Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) A/D Trigger input setup time converter Rev. 6.00 Feb 22, 2005 page 1050 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics Condition Item HCAN*2 Transmit data delay time Receive data setup time Receive data hold time Symbol tHTXD tHRXS tHRXH Min. -- 100 100 Max. 100 -- -- Unit ns Test Conditions Figure 24-27 Notes: 1. The PPG output is not available in the H8S2635 Group. 2. The HCAN input signal is asynchronous. However, its state is judged to have changed at the leading edge (two clock cycles) of the CK clock signal shown in figure 24-27. The HCAN output signal is also asynchronous. Its state changes based on the leading edge (two clock cycles) of the CK clock signal shown in figure 24-27. Table 24-31 I2C Bus Timing [Option]*1 Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, = 5 MHz to maximum operating frequency, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rise time SCL, SDA input fall time SCL, SDA input spike pulse elimination time SDA input bus free time Start condition input hold time Retransmission start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load 2 Symbol tSCL tSCLH tSCLL tSr tSf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb Min. 12tcyc 3tcyc 5tcyc -- -- -- 5tcyc 3tcyc 3tcyc 3tcyc 0.5tcyc 0 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- 7.5tcyc 300 1tcyc -- -- -- -- -- -- 400 *2 Unit ns ns ns ns ns ns ns ns ns ns ns ns pF Notes Figure 24-28 Notes: 1. Available when using I C bus interface (the W-mask version only). 2. 17.5tcyc can be set according to the clock selected for use by the I2C module. For details, see section 15.4, Usage Notes. Rev. 6.00 Feb 22, 2005 page 1051 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.3.5 A/D Conversion Characteristics Table 24-32 lists the A/D conversion characteristics. Table 24-32 A/D Conversion Characteristics Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization Absolute accuracy Min. 10 10 -- -- -- -- -- -- -- Typ. 10 -- -- -- -- -- -- 0.5 -- Max. 10 -- 20 5 3.5 3.5 3.5 -- 4.0 Unit bits s pF k LSB LSB LSB LSB LSB Rev. 6.00 Feb 22, 2005 page 1052 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.3.6 D/A Conversion Characteristics* Table 24-33 shows the D/A conversion characteristics. Note: * The D/A conversion is not implemented in the H8S/2635 and H8S/2634. Table 24-33 D/A Conversion Characteristics Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item Resolution Conversion time Absolute accuracy Min. 8 -- -- -- Typ. 8 -- 1.5 -- Max. 8 10 2.0 1.5 Unit bits s LSB LSB 20-pF capacitive load 2-M resistive load 4-M resistive load Test Conditions Rev. 6.00 Feb 22, 2005 page 1053 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.3.7 Flash Memory Characteristics Table 24-34 shows the flash memory characteristics. Table 24-34 Flash Memory Characteristics Conditions: VCC =4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS, AVSS = 0 V Ta = 0 to +75C (Programming/erasing operating temperature range: regular specification) Item 124 Programming time* * * Symbol tP tE NWEC tsswe tspsu tsp30 tsp200 tsp10 Min. -- -- -- 1 50 28 198 8 Typ. 10 100 -- 1 50 30 200 10 Max. 200 1200 100 -- -- 32 202 12 Unit ms/ 128 bytes ms/block Times s s s s s Test Condition Erase time*1 *3 *5 Reprogramming count Programming Wait time after SWE bit setting *1 Wait time after PSU bit setting *1 Wait time after P bit setting *1 *4 Programming time wait Programming time wait Additionalprogramming time wait Wait time after P bit clear *1 Wait time after PSU bit clear *1 1 Wait time after PV bit setting * tcp tcpsu tspv tspvr tcpv tcswe 5 5 4 2 2 100 -- 1 100 10 10 10 20 5 5 4 2 2 100 -- 1 100 10 10 10 20 -- -- -- -- -- -- 1000 -- -- 100 -- -- -- s s s s s s Times s s ms s s s Erase time wait Wait time after H'FF dummy write*1 Wait time after PV bit clear *1 Wait time after SWE bit clear*1 Wait time after SWE bit setting *1 Wait time after ESU bit setting * Wait time after E bit setting *1 *5 1 Wait time after E bit clear * 1 Wait time after ESU bit clear * 1 14 Maximum programming count* * N Erase tsswe tsesu tse tce tcesu tsev Wait time after EV bit setting *1 Rev. 6.00 Feb 22, 2005 page 1054 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics Item Erase Wait time after H'FF dummy write*1 Wait time after EV bit clear * Maximum erase count*1 *5 1 Symbol tsevr tcev tcswe N Min. 2 4 100 12 Typ. 2 4 100 -- Max. -- -- -- 120 Unit s s s Times Test Condition Wait time after SWE bit clear*1 Notes: 1. Make each time setting in accordance with the program/program-verify flowchart or erase/erase-verify flowchart. 2. Programming time per 128 bytes (Shows the total period for which the P-bit in the flash memory control register (FLMCR1) is set. It does not include the programming verification time) 3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time) 4. To specify the maximum programming time value (tP (max.)) in the 128-byte programming algorithm, set the max. value (1000) for the maximum programming count (N). The wait time after P bit setting should be changed as follows according to the value of the programming counter (n). Programming counter (n) = 1 to 6: tsp30 = 30 s Programming counter (n) = 7 to 1000: tsp200 = 200 s [In additional programming] Programming counter (n)= 1 to 6: tsp10 = 10 s 5. For the maximum erase time (tE (max.)), the following relationship applies between the wait time after E bit setting (tse) and the maximum erase count (N): tE (max.) = Wait time after E bit setting (tse) x maximum erase count (N) To set the maximum erase time, the values of (tse) and (N) should be set so as to satisfy the above formula. Examples: When tse = 100 [ms], N = 12 times When tse = 10 [ms], N = 120 times Rev. 6.00 Feb 22, 2005 page 1055 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.4 24.4.1 H8S/2630 Group Electrical Characteristics Absolute Maximum Ratings Table 24-35 lists the absolute maximum ratings. Table 24-35 Absolute Maximum Ratings Item Power supply voltage Input voltage (OSC1, OSC2) Input voltage (XTAL, EXTAL) Input voltage (ports 4 and 9) Input voltage (ports H and J) Symbol VCC Vin Vin Vin Vin Value -0.3 to +7.0 -0.3 +4.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to PWMVCC +0.3 -0.3 to VCC +0.3 Unit V V V V V V Input voltage (except XTAL, Vin EXTAL, OSC1, OSC2, ports 4, 9, H and J) Reference voltage Analog power supply voltage Analog input voltage Operating temperature Storage temperature Vref AVCC VAN Topr Tstg -0.3 to AVCC +0.3 -0.3 to +7.0 -0.3 to AVCC +0.3 Regular specifications: -20 to +75 Wide-range specifications: -40 to +85 -55 to +125 V V V C C C Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded. Rev. 6.00 Feb 22, 2005 page 1056 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.4.2 Power Supply Voltage and Operating Frequency Range Power supply voltage and operating frequency ranges (shaded areas) are shown in figure 24-7. Operating range of high-speed, medium-speed and sleep modes 24 20 Frequency (MHz) 16 12 8 4 0 3 3.5 4 4.5 5 5.5 6 Power supply voltage (V) Operating range of watch*, sub-active* and sub-sleep* modes 32.768 Frequency (MHz) 0 3 3.5 4 4.5 5 5.5 6 Power supply voltage (V) Note: * The watch, subactive, and subsleep modes are available in the U-mask and W-mask versions only. Figure 24-7 Power Supply Voltage and Operating Ranges Rev. 6.00 Feb 22, 2005 page 1057 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.4.3 DC Characteristics Table 24-36 lists the DC characteristics. Table 24-36 lists the permissible output currents. Table 24-36 DC Characteristics Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)*1 *6 Item Schmitt trigger input voltage Input high voltage Symbol IRQ0 to IRQ5 VT VT , , NMI, FWE, MD2 to MD0 - + + - Min. 1.0 -- 0.4 VCC - 0.7 Typ. -- -- -- -- Max. -- VCC x 0.7 -- VCC + 0.3 Unit V Test Conditions VT - VT VIH V Rev. 6.00 Feb 22, 2005 page 1058 of 1484 REJ09B0103-0600 YBTS SER Input low voltage YBTS SER EXTAL Ports H, J HRxD0, HRxD1 EXTAL Ports H, J HRxD0, HRxD1 Ports 4, 9 VCC x 0.7 2.2 VCC x 0.8 -- -- -- VCC + 0.3 VCC + 0.3 VCC + 0.3 PWMVCC + 0.3 VCC + 0.3 AVCC + 0.3 0.5 V Ports 1, 3, F Ports A to E PWMVCC x -- 0.8 2.2 -- Ports 4 and 9 , , NMI, FWE, MD2 to MD0 Ports 1, 3, F Ports A to E VIL AVCC x 0.7 -- -0.3 -- -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -- -- -- -- -- -- 0.8 0.8 VCC x 0.2 PWMVCC x 0.2 VCC x 0.2 AVCC x 0.2 Section 24 Electrical Characteristics Item Output high voltage Ports 1, 3, A to F, H,J HTxD0, HTxD1 (excluding P34 and 7 P35* ) P34, P35*7 Ports 1, 3, A to F, H, J HTxD0, HTxD1 (excluding P34 and 7 P35* ) PWM1A to PWM1H, PWM2A to PWM2H Output low voltage All output pins VOL except PWM1A to PWM1H, PWM2A to PWM2H PWM1A to PWM1H, PWM2A to PWM2H Symbol VOH Min. VCC - 0.5 Typ. -- Max. -- Unit V Test Conditions IOH = -200 A VCC - 2.5 3.5 -- -- -- -- IOH = -100 A IOH = -1 mA PWMVCC - -- 0.5 -- IOH = -15 mA -- -- 0.4 V IOL = 1.6 mA -- -- 0.5 V IOL = 15 mA Three-state leakage current (off state) IMN YBTS SER Ports 4, 9 Input leakage current | Iin | -- -- -- -- -- -- -- -- -- 1.0 1.0 1.0 1.0 1.0 A , , MD2 to MD0 HRxD0, HRxD1, FWE Vin = 0.5 V to VCC - 0.5 V Vin = 0.5 V to AVCC - 0.5 V A Vin = 0.5 V to VCC - 0.5 V Ports 1, 3, A to F, H, J HTxD0, HTxD1 ITSI -- Rev. 6.00 Feb 22, 2005 page 1059 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics Item MOS input Ports A to E pull-up current Symbol -IP Cin Min. 50 -- -- -- Typ. -- -- -- -- Max. 300 30 30 15 Unit A pF Test Conditions Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25C Current 2 dissipation* Normal operation Sleep mode All modules stopped Mediumspeed mode (/32) Subactive 5 mode* Subsleep 5 mode* Watch mode*5 Standby 3 mode* Analog power supply current Reference current During A/D and D/A conversion Idle During A/D and D/A conversion Idle RAM standby voltage Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage between 4.5 V and 5.5 V to the AVCC and Vref pins by connecting them to VCC, for instance. Set Vref AVCC. 2. Current dissipation values are for VIH (min.) = VCC - 0.5 V, VIL (max.) = 0.5 V with all output pins unloaded and the on-chip pull-up resistors in the off state. 3. The values are for VRAM VCC < 3.0 V, VIH (min.) = VCC x 0.9, and VIL (max.) = 0.3 V. Rev. 6.00 Feb 22, 2005 page 1060 of 1484 REJ09B0103-0600 SER SER NMI All input pins except and NMI Input capacitance ICC* 4 -- -- -- -- 75 65 57 49 90 80 -- -- mA f = 20 MHz mA f = 20 MHz (reference value) -- 130 220 A Using 32.768 kHz crystal resonator -- -- -- -- AlCC -- 80 30 2.0 -- 1.0 160 60 5.0 20 2.0 mA A Ta 50C 50C < Ta AVCC = 5.0 V -- AlCC -- 0.1 4.0 5.0 5.0 A mA Vref = 5.0 V -- VRAM 2.0 0.1 -- 5.0 -- A V Section 24 Electrical Characteristics 4. ICC depends on VCC and f as follows: ICC (max.) = 30 (mA) + 0.54 (mA/(MHz x V)) x VCC x f (normal operation) ICC (max.) = 30 (mA) + 0.45 (mA/(MHz x V)) x VCC x f (sleep mode) 5. The watch, subactive, and subsleep modes are available in the U-mask and W-mask versions only. See section 22A.7, Subclock Oscillator, for the method of fixing pins OSC1 and OSC2. 6. If the motor-control PWM timer is not used, do not leave the PMWVCC, or PMWVSS pins open. If the motor-control PWM timer is not used, apply a voltage of between 4.5 and 5.5 V to the PWMVCC pin, for instance, by connecting it to VCC. 7. The characteristics of pins 34 and 35 apply to the W-mask version. Rev. 6.00 Feb 22, 2005 page 1061 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics Table 24-37 Permissible Output Currents Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Permissible output low current (per pin) All output pins except PWM1A to PWM1H, PWM2A to PWM2H PWM1A to PWM1H, PWM2A to PWM2H Symbol IOL Min. -- Typ. -- Max. 10 Unit mA Test condition IOL -- -- -- -- -- -- -- 25 30 40 80 mA mA mA mA Ta = 85C Ta = 25C Ta = -40C Permissible output high current (per pin) All output pins except PWM1A to PWM1H, PWM2A to PWM2H PWM1A to PWM1H, PWM2A to PWM2H Permissible Total of all output pins output high excepting PWM1A to current (total) PWM1H, and PWM2A to PWM2H Total of PWM1A to PWM1H, - IOH and PWM2A to PWM2H Note: To protect chip reliability, do not exceed the output current values in table 24-37. Rev. 6.00 Feb 22, 2005 page 1062 of 1484 REJ09B0103-0600 Total of PWM1A to PWM1H, and PWM2A to PWM2H Permissible Total of all output pins output low excepting PWM1A to current (total) PWM1H, and PWM2A to PWM2H IOL -- IOL -- -- -- -- -- -- -- -- 150 180 220 2.0 mA mA mA mA Ta = 85C Ta = 25C Ta = -40C -IOH -IOH -- -- -- -- -- -- -- 25 30 40 40 mA mA mA mA Ta = 85C Ta = 25C Ta = -40C - IOH -- -- -- -- -- -- -- 150 180 220 mA mA mA Ta = 85C Ta = 25C Ta = -40C Section 24 Electrical Characteristics Table 24-38 Bus Drive Characteristics [Option]* Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Applicable Pins: SCL1-0, SDA1-0 Item Schmitt trigger input voltage Symbol VT VT - + + - Min. 1.0 -- 0.4 - VCC x 0.7 - 0.5 -- -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- Max. -- VCC x 0.7 -- VCC + 0.5 VCC x 0.3 0.7 0.4 0.4 20 1.0 250 Unit V Test Conditions VT - VT Input high voltage Input low voltage Output low voltage VIH VIL VOL VCC = 4.5 V to 5.5 V V V V IOL = 8 mA, VCC = 4.5 V to 5.5 V IOL = 3 mA, VCC = 4.5 V to 5.5 V IOL = 1.6 mA, VCC = 3.3 V to 5.5 V pF A ns Vin = 0 V, f = 1 MHz, Ta = 25 C Vin = 0.5 V to VCC - 5.5 V Input capacitance Three-state leakage current (off state) SCL, SDA, output fall time Cin ITSI tof -- -- 20 + 0.1Cb Note: * Available when using I2C bus interface (the W-mask version only). Rev. 6.00 Feb 22, 2005 page 1063 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.4.4 AC Characteristics Figure 24-8 show, the test conditions for the AC characteristics. 5V RL LSI output pin C RH C = 50 pF: Ports 10 to 13, A to F (In case of expansion bus control signal output pin setting) C = 30 pF: All ports RL = 2.4 k RH = 12 k Input/output timing measurement levels * Low level: 0.8 V * High level: 2.0 V Figure 24-8 Output Load Circuit Rev. 6.00 Feb 22, 2005 page 1064 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics (1) Clock Timing Table 24-39 lists the clock timing Table 24-39 Clock Timing Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition 20MHz Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Clock oscillator settling time at reset (crystal) Clock oscillator settling time in software standby (crystal) External clock output stabilization delay time 32-kHz clock oscillation settling time Subclock oscillator frequency Subclock (SUB) cycle time Symbol tcyc tCH tCL tCr tCf tOSC1 tOSC2 tDEXT tOSC3 fSUB tSUB Min. 50 15 15 -- -- 20 8 2 -- 32.768 30.5 Max. 250 -- -- 10 10 -- -- -- 2 Unit ns ns ns ns ns ms ms ms s kHz s Figure 24-10 Figure 23A-3 Figure 23B-3 Figure 24-10 Test Conditions Figure 24-9 Rev. 6.00 Feb 22, 2005 page 1065 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics (2) Control Signal Timing Table 24-40 lists the control signal timing. Table 24-40 Control Signal Timing Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item setup time pulse width Symbol tRESS tRESW tNMIS tNMIH tNMIW tIRQS tIRQH tIRQW Min. 200 20 150 10 200 150 10 200 Max. -- -- -- -- -- -- -- -- ns ns ns ns Unit ns tcyc ns Figure 24-12 Test Conditions Figure 24-11 SER SER QRI QRI QRI NMI setup time NMI hold time NMI pulse width (exiting software standby mode) setup time hold time pulse width (exiting software standby mode) Rev. 6.00 Feb 22, 2005 page 1066 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics (3) Bus Timing Table 24-41 lists the bus timing. Table 24-41 Bus Timing Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item Address delay time Address setup time Address hold time delay time delay time 1 delay time 2 Symbol tAD tAS tAH tASD tRSD1 tRSD2 tRDS tRDH tACC1 tACC2 tACC3 tACC4 tACC5 tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS tWDH Min. -- 0.5 x tcyc - 20 0.5 x tcyc - 15 -- -- -- 20 0 -- -- -- -- -- -- -- 1.0 x tcyc - 20 1.5 x tcyc - 20 -- 0.5 x tcyc - 20 0.5 x tcyc - 10 Max. 35 -- -- 20 20 20 -- -- 1.0 x tcyc - 48 1.5 x tcyc - 45 2.0 x tcyc - 45 2.5 x tcyc - 45 3.0 x tcyc - 50 20 20 -- -- 30 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 24-13 to Figure 24-17 RW RW RW RW DR DR SA Read data setup time Read data hold time Read data access time1 Read data access time2 Read data access time3 Read data access time 4 Read data access time 5 delay time 1 delay time 2 pulse width 1 pulse width 2 Write data delay time Write data setup time Write data hold time Rev. 6.00 Feb 22, 2005 page 1067 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics (4) Timing of On-Chip Supporting Modules Table 24-42 lists the timing of on-chip supporting modules. Table 24-42 Timing of On-Chip Supporting Modules Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item I/O port Output data delay time Output data delay time 2 Input data setup time Input data hold time PPG TPU Pulse output delay time Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width PWM SCI Single edge Both edges Symbol tPWD tPWD2 tPRS tPRH tPOD tTOCD tTICS tTCKS tTCKWH tTCKWL tMPWMOD Min. -- -- 30 30 -- -- 30 30 1.5 2.5 -- 4 6 tSCKW tSCKr tSCKf tTXD tRXS tRXH tTRGS 0.4 -- -- -- 50 50 50 Max. 50 50 -- -- 50 50 -- -- -- -- 50 -- -- 0.6 1.5 1.5 50 -- -- -- ns Figure 24-26 ns Figure 24-25 tScyc tcyc ns tcyc Figure 24-23 Figure 24-24 ns tcyc Figure 24-22 ns ns Figure 24-20 Figure 24-21 Unit ns Test Conditions Figure 24-18 Figure 24-19 Pulse output delay time Input clock cycle Synchronous Asynchronous tScyc Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) A/D Trigger input setup time converter Rev. 6.00 Feb 22, 2005 page 1068 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics Condition Item HCAN* Transmit data delay time Receive data setup time Receive data hold time Symbol tHTXD tHRXS tHRXH Min. -- 100 100 Max. 100 -- -- Unit ns Test Conditions Figure 24-27 Note: * The HCAN input signal is asynchronous. However, its state is judged to have changed at the leading edge (two clock cycles) of the CK clock signal shown in figure 24-27. The HCAN output signal is also asynchronous. Its state changes based on the leading edge (two clock cycles) of the CK clock signal shown in figure 24-27. Table 24-43 I2C Bus Timing [Option]*1 Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, = 5 MHz to maximum operating frequency, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rise time SCL, SDA input fall time SCL, SDA input spike pulse elimination time SDA input bus free time Start condition input hold time Retransmission start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load 2 Symbol tSCL tSCLH tSCLL tSr tSf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb Min. 12tcyc 3tcyc 5tcyc -- -- -- 5tcyc 3tcyc 3tcyc 3tcyc 0.5tcyc 0 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- Unit ns ns ns Notes Figure 24-28 7.5tcyc*2 ns 300 1tcyc -- -- -- -- -- -- 400 ns ns ns ns ns ns ns ns pF Notes: 1. Available when using I C bus interface (the W-mask version only). 2. 17.5tcyc can be set according to the clock selected for use by the I2C module. For details, see section 15.4, Usage Notes. Rev. 6.00 Feb 22, 2005 page 1069 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.4.5 A/D Conversion Characteristics Table 24-44 lists the A/D conversion characteristics. Table 24-44 A/D Conversion Characteristics Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization Absolute accuracy Min. 10 10 -- -- -- -- -- -- -- Typ. 10 -- -- -- -- -- -- 0.5 -- Max. 10 -- 20 5 3.5 3.5 3.5 -- 4.0 Unit bits s pF k LSB LSB LSB LSB LSB Rev. 6.00 Feb 22, 2005 page 1070 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.4.6 D/A Conversion Characteristics Table 24-45 shows the D/A conversion characteristics. Table 24-45 D/A Conversion Characteristics Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item Resolution Conversion time Absolute accuracy Min. 8 -- -- -- Typ. 8 -- 1.5 -- Max. 8 10 2.0 1.5 Unit bits s LSB LSB 20-pF capacitive load 2-M resistive load 4-M resistive load Test Conditions Rev. 6.00 Feb 22, 2005 page 1071 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.4.7 Flash Memory Characteristics Table 24-46 shows the flash memory characteristics. Table 24-46 Flash Memory Characteristics Conditions: VCC =4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS, AVSS = 0 V Ta = 0 to +75C (Programming/erasing operating temperature range: regular specification) Item 124 Programming time* * * Symbol tP tE NWEC tsswe tspsu tsp30 tsp200 tsp10 Min. -- -- -- 1 50 28 198 8 Typ. 10 100 -- 1 50 30 200 10 Max. 200 1200 100 -- -- 32 202 12 Unit ms/ 128 bytes ms/block Times s s s s s Test Condition Erase time*1 *3 *5 Reprogramming count Programming Wait time after SWE bit setting *1 Wait time after PSU bit setting *1 Wait time after P bit setting *1 *4 Programming time wait Programming time wait Additionalprogramming time wait Wait time after P bit clear *1 Wait time after PSU bit clear *1 1 Wait time after PV bit setting * tcp tcpsu tspv tspvr tcpv tcswe 5 5 4 2 2 100 -- 1 100 10 10 10 20 5 5 4 2 2 100 -- 1 100 10 10 10 20 -- -- -- -- -- -- 1000 -- -- 100 -- -- -- s s s s s s Times s s ms s s s Erase time wait Wait time after H'FF dummy write*1 Wait time after PV bit clear *1 Wait time after SWE bit clear*1 Wait time after SWE bit setting *1 Wait time after ESU bit setting * Wait time after E bit setting *1 *5 1 Wait time after E bit clear * 1 Wait time after ESU bit clear * 1 14 Maximum programming count* * N Erase tsswe tsesu tse tce tcesu tsev Wait time after EV bit setting *1 Rev. 6.00 Feb 22, 2005 page 1072 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics Item Erase Wait time after H'FF dummy write*1 Wait time after EV bit clear * Maximum erase count*1 *5 1 Symbol tsevr tcev tcswe N Min. 2 4 100 12 Typ. 2 4 100 -- Max. -- -- -- 120 Unit s s s Times Test Condition Wait time after SWE bit clear*1 Notes: 1. Make each time setting in accordance with the program/program-verify flowchart or erase/erase-verify flowchart. 2. Programming time per 128 bytes (Shows the total period for which the P-bit in the flash memory control register (FLMCR1) is set. It does not include the programming verification time) 3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time) 4. To specify the maximum programming time value (tP (max.)) in the 128-byte programming algorithm, set the max. value (1000) for the maximum programming count (N). The wait time after P bit setting should be changed as follows according to the value of the programming counter (n). Programming counter (n) = 1 to 6: tsp30 = 30 s Programming counter (n) = 7 to 1000: tsp200 = 200 s [In additional programming] Programming counter (n)= 1 to 6: tsp10 = 10 s 5. For the maximum erase time (tE (max.)), the following relationship applies between the wait time after E bit setting (tse) and the maximum erase count (N): tE (max.) = Wait time after E bit setting (tse) x maximum erase count (N) To set the maximum erase time, the values of (tse) and (N) should be set so as to satisfy the above formula. Examples: When tse = 100 [ms], N = 12 times When tse = 10 [ms], N = 120 times Rev. 6.00 Feb 22, 2005 page 1073 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.5 Operation Timing The operation timing is shown below. 24.5.1 Clock Timing The clock timing is shown below. tcyc tCH tCL tCr tCf Figure 24-9 System Clock Timing EXTAL tDEXT VCC tDEXT STBY tOSC1 RES tOSC1 Figure 24-10 Oscillator Settling Timing Rev. 6.00 Feb 22, 2005 page 1074 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.5.2 Control Signal Timing The control signal timing is shown below. tRESS RES tRESW tRESS Figure 24-11 Reset Input Timing tNMIS NMI tNMIW tNMIH IRQ tIRQW tIRQS IRQ Edge input tIRQS IRQ Level input tIRQH Figure 24-12 Interrupt Input Timing Rev. 6.00 Feb 22, 2005 page 1075 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics 24.5.3 Bus Timing The bus timing is shown below. T1 T2 tAD A23 to A0 tAS AS tRSD2 tASD tASD tAH tRSD1 RD (read) tACC2 tACC3 D15 to D0 (read) tRDS tRDH tWRD2 HWR, LWR (write) tWDD D15 to D0 (write) tWSW1 tWRD2 tWDH Figure 24-13 Basic Bus Timing (Two-State Access) Rev. 6.00 Feb 22, 2005 page 1076 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics T1 T2 T3 tAD A23 to A0 tAS AS tAH tASD tASD tRSD1 RD (read) tACC4 tRSD2 tACC5 D15 to D0 (read) tRDS tRDH tWRD1 HWR, LWR (write) tWDD tWDS D15 to D0 (write) tWSW2 tWRD2 tWDH Figure 24-14 Basic Bus Timing (Three-State Access) Rev. 6.00 Feb 22, 2005 page 1077 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics T1 tAD A23 to A0 tAS AS tRSD1 RD (read) D15 to D0 (read) tASD T2 Tw T3 tASD tAH tRSD2 tRDS tRDH tWRD1 HWR, LWR (write) D15 to D0 (write) tWRD2 tWDD tWDS tWDH Figure 24-15 Basic Bus Timing (Three-State Access with One Wait State) Rev. 6.00 Feb 22, 2005 page 1078 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics T1 T2 or T3 T1 T2 tAD A23 to A0 tAS tAH tASD tASD AS tRSD2 RD (read) tACC3 D15 to D0 (read) tRDS tRDH Figure 24-16 Burst ROM Access Timing (Two-State Access) Rev. 6.00 Feb 22, 2005 page 1079 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics T1 T2 or T3 T1 tAD A23 to A0 AS tRSD2 RD (read) tACC1 D15 to D0 (read) tRDS tRDH Figure 24-17 Burst ROM Access Timing (One-State Access) 24.5.4 On-Chip Supporting Module Timing The on-chip supporting module timing is shown below. T1 tPRS Ports 1, 3, 4, 9 A to F (read) tPWD Ports 1, 3, A to F (write) tPRH T2 Figure 24-18 I/O Port Input/Output Timing (Ports 1, 3, 4, 9, A to F) Rev. 6.00 Feb 22, 2005 page 1080 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics Bus cycle T1 tPRS Ports H, J (read) tPWD2 Ports H, J (write) tPRH T2 T3 T4 Figure 24-19 I/O Port (Ports H and J) Input/Output Timing tPOD PO15 to PO8 Figure 24-20 PPG Output Timing* Note: * The PPG output is not implemented in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 1081 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 24-21 TPU Input/Output Timing tTCKS TCLKA to TCLKD tTCKWL tTCKWH tTCKS Figure 24-22 TPU Clock Input Timing tMPWMOD PWM1A to PWM1H, PWM2A to PWM2H Figure 24-23 Motor Control PWM Output Timing tSCKW SCK0 to SCK2 tScyc tSCKr tSCKf Figure 24-24 SCK Clock Input Timing Rev. 6.00 Feb 22, 2005 page 1082 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics SCK0 to SCK2 tTXD TxD0 to TxD2 (transit data) tRXS RxD0 to RxD2 (receive data) tRXH Figure 24-25 SCI Input/Output Timing (Clock Synchronous Mode) tTRGS ADTRG Figure 24-26 A/D Converter External Trigger Input Timing Preliminary CK tHTXD HTxD0, HTxD1 (transmit data) tHRXS tHRXH HRxD0, HRxD1 (receive data) Figure 24-27 HCAN Input/Output Timing Rev. 6.00 Feb 22, 2005 page 1083 of 1484 REJ09B0103-0600 Section 24 Electrical Characteristics VIH SDA0 to SDA1 tBUF tSTAH VIL tSCLH tSTAS tSP tSTOS SCL0 to SCL1 P* S* tSf tSCLL tSCL tSr tSDAH Sr* tSDAS Note: * S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr : Retransmission start condition Figure 24-28 I2C Bus Interface Input/Output Timing (Option)* Note: * I2C bus interface is available a an option in the H8S/2638, H8S/2639, and H8S/2630 only. 24.6 Usage Note Although both the F-ZTAT and mask ROM versions fully meet the electrical specifications listed in this manual, there may be differences in the actual values of the electrical characteristics, operating margins, noise margins, and so forth, due to differences in the fabrication process, the on-chip ROM, and the layout patterns. Therefore, if a system is evaluated using the F-ZTAT version, a similar evaluation should also be performed using the mask ROM version. Rev. 6.00 Feb 22, 2005 page 1084 of 1484 REJ09B0103-0600 Appendix A Instruction Set Appendix A Instruction Set A.1 Instruction List Operand Notation Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / ( ) <> :8/:16/:24/:32 General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-and-accumulate register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Add Subtract Multiply Divide Logical AND Logical OR Logical exclusive OR Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right Logical NOT (logical complement) Contents of operand 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev. 6.00 Feb 22, 2005 page 1085 of 1484 REJ09B0103-0600 Appendix A Instruction Set Condition Code Notation Symbol Changes according to the result of instruction * 0 1 -- Undetermined (no guaranteed value) Always cleared to 0 Always set to 1 Not affected by execution of the instruction Rev. 6.00 Feb 22, 2005 page 1086 of 1484 REJ09B0103-0600 Table A-1 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 1 1 2 3 Operand Size #xx Rn @ERn @(d,ERn) @aa @(d,PC) @@aa Mnemonic Operation #xx:8Rd8 2 2 4 8 2 2 4 6 2 4 8 2 2 4 6 Rs8@aa:8 Rs8@aa:16 Rs8@aa:32 #xx:16Rd16 2 2 Rs16Rd16 @ERsRd16 Rs8@(d:16,ERd) Rs8@(d:32,ERd) ERd32-1ERd32,Rs8@ERd Rs8@ERd @aa:32Rd8 @aa:16Rd8 @aa:8Rd8 @ERsRd8,ERs32+1ERs32 @(d:32,ERs)Rd8 @(d:16,ERs)Rd8 @ERsRd8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rs8Rd8 0 0 IHNZVC B2 B B B B B B B B B B B B B B B W4 W W MOV MOV.B #xx:8,Rd Instruction Set MOV.B Rs,Rd (1) Data Transfer Instructions MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd @-ERn/@ERn+ MOV.B @(d:32,ERs),Rd 5 3 2 3 4 2 3 5 3 2 3 4 2 1 2 MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1087 of 1484 REJ09B0103-0600 MOV.W @ERs,Rd MOV.W Rs,Rd Addressing Mode/ Instruction Length (Bytes) Condition Code Operation @(d:16,ERs)Rd16 @(d:32,ERs)Rd16 IHNZVC 0 0 0 0 0 0 0 0 0 ERs32ERd32 @ERsERd32 @(d:16,ERs)ERd32 @(d:32,ERs)ERd32 @ERsERd32,ERs32+4ERs32 @aa:16ERd32 0 0 0 0 0 0 0 0 No. of States*1 Advanced 3 5 3 3 4 2 3 5 3 3 4 3 1 4 5 7 5 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Mnemonic W W W W W W W W W W W L6 L L L L L L L 4 6 8 10 6 4 2 6 4 Rs16@aa:16 Rs16@aa:32 #xx:32ERd32 2 8 Rs16@(d:32,ERd) 4 Rs16@(d:16,ERd) 2 Rs16@ERd 6 @aa:32Rd16 4 @aa:16Rd16 2 @ERsRd16,ERs32+2ERs32 8 4 MOV MOV.W @(d:16,ERs),Rd Appendix A Instruction Set MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd ERd32-2ERd32,Rs16@ERd MOV.L @aa:32,ERd @aa:32ERd32 Rev. 6.00 Feb 22, 2005 page 1088 of 1484 REJ09B0103-0600 0 0 5 6 MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 4 Operand Size #xx Rn @ERn @(d,ERn) @aa @(d,PC) @@aa Mnemonic Operation ERs32@ERd 6 10 4 6 8 2 4 2 4 4 @SPRn16,SP+2SP @SPERn32,SP+4SP SP-2SP,Rn16@SP SP-4SP,ERn32@SP (@SPERn32,SP+4SP) Repeated for each register restored L 4 (SP-4SP,ERn32@SP) Repeated for each register saved Cannot be used in this LSI Cannot be used in this LSI ERs32@aa:32 ERs32@aa:16 ERs32@(d:32,ERd) ERs32@(d:16,ERd) L 4 @-ERn/@ERn+ IHNZVC 0 0 0 0 0 0 0 0 0 0 MOV MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) L 5 7 5 5 6 3 5 3 5 7/9/11 [1] MOV.L ERs,@(d:32,ERd) L L L L W L W L L MOV.L ERs,@-ERd ERd32-4ERd32,ERs32@ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 POP POP.W Rn POP.L ERn PUSH.L ERn LDM*4 LDM @SP+,(ERm-ERn) PUSH PUSH.W Rn STM*4 STM (ERm-ERn),@-SP 7/9/11 [1] MOVFPE MOVFPE @aa:16,Rd [2] [2] MOVTPE MOVTPE Rs,@aa:16 Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1089 of 1484 REJ09B0103-0600 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 1 1 2 1 3 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa Mnemonic Operation Rd8+#xx:8Rd8 2 Rd16+#xx:16Rd16 2 ERd32+#xx:32ERd32 2 Rd8+#xx:8+CRd8 2 2 2 2 2 2 2 2 2 2 2 Rd8+1Rd8 Rd16+1Rd16 Rd16+2Rd16 ERd32+1ERd32 ERd32+2ERd32 Rd8 decimal adjustRd8 Rd8-Rs8Rd8 Rd16-#xx:16Rd16 ERd32+2ERd32 ERd32+4ERd32 ERd32+1ERd32 Rd8+Rs8+CRd8 ERd32+ERs32ERd32 [4] Rd16+Rs16Rd16 [3] [3] Rd8+Rs8Rd8 IHNZVC B2 B W4 W L6 L B2 B L L L B W W L L B B W4 ADD ADD.B #xx:8,Rd Appendix A Instruction Set (2) Arithmetic Instructions ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd [4] [5] ADDX Rs,Rd [5] Rev. 6.00 Feb 22, 2005 page 1090 of 1484 REJ09B0103-0600 1 1 * * 1 1 1 1 1 1 1 1 1 1 [3] 2 ADDX ADDX #xx:8,Rd ADDS ADDS #1,ERd ADDS #2,ERd ADDS #4,ERd INC INC.B Rd INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd DAA DAA Rd SUB SUB.B Rs,Rd SUB.W #xx:16,Rd Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 1 3 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa Mnemonic Operation Rd16-Rs16Rd16 ERd32-#xx:32ERd32 2 Rd8-#xx:8-CRd8 2 2 2 2 2 2 2 2 2 2 2 2 Rd8-1Rd8 Rd16-1Rd16 Rd16-2Rd16 ERd32-1ERd32 ERd32-2ERd32 Rd8 decimal adjustRd8 ERd32-4ERd32 ERd32-2ERd32 ERd32-1ERd32 Rd8-Rs8-CRd8 ERd32-ERs32ERd32 [4] [4] [3] W L6 L B2 B L L L B W W L L B B W 2 IHNZVC SUB SUB.W Rs,Rd SUB.L ERs,ERd [5] [5] SUB.L #xx:32,ERd SUBX SUBX #xx:8,Rd 1 1 * * 1 1 1 1 1 1 1 1 1 SUBX Rs,Rd SUBS SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd DEC DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DAS DAS Rd DEC.L #2,ERd MULXU MULXU.B Rs,Rd Rd8xRs8Rd16 (unsigned multiplication) Rd16xRs16ERd32 (unsigned multiplication) Rd8xRs8Rd16 (signed multiplication) Rd16xRs16ERd32 (signed multiplication) 3 4 MULXU.W Rs,ERd MULXS W 4 MULXS.B Rs,Rd B 4 4 5 Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1091 of 1484 REJ09B0103-0600 MULXS.W Rs,ERd Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 12 Operand Size #xx Rn @ERn @(d,ERn) @aa @(d,PC) @@aa Mnemonic Operation B RdL: quotient) (unsigned division) W Rd: quotient) (unsigned division) B RdL: quotient) (signed division) W Rd8-#xx:8 2 Rd16-Rs16 ERd32-#xx:32 2 2 2 2 2 2 ERd32-ERs32 0-Rd8Rd8 0-Rd16Rd16 0-ERd32ERd32 0( @-ERn/@ERn+ IHNZVC Appendix A Instruction Set DIVXU DIVXU.B Rs,Rd Rd16/Rs8Rd16 (RdH: remainder, [6] [7] DIVXU.W Rs,ERd ERd32/Rs16ERd32 (Ed: remainder, [6] [7] 20 DIVXS divxs.B Rs,Rd Rd16/Rs8Rd16 (RdH: remainder, [8] [7] 13 Rev. 6.00 Feb 22, 2005 page 1092 of 1484 REJ09B0103-0600 ERd32/Rs16ERd32 (Ed: remainder, [8] [7] Rd: quotient) (signed division) B2 B W4 W L6 L B W L W L 1 1 [3] 2 [3] 1 [4] 3 [4] 1 1 1 1 0 0 0 0 1 1 21 DIVXS.W Rs,ERd CMP CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd NEG NEG.B Rd NEG.W Rd NEG.L ERd EXTU EXTU.W Rd EXTU.L ERd Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @(d,PC) @@aa @-ERn/@ERn+ Mnemonic Operation IHNZVC ( ( TAS TAS @ERd *3 @ERd-0CCR set, (1) EXTS.L ERd L 2 ( EXTS EXTS.W Rd W 2 ( 0 0 0 1 4 MAC MAC @ERn+,@ERm+ CLRMAC CLRMAC LDMAC LDMAC ERs,MACH LDMAC ERs,MACL STMAC MACL,ERd STMAC STMAC MACH,ERd Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1093 of 1484 REJ09B0103-0600 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 1 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @(d,PC) @@aa Mnemonic Operation Rd8#xx:8Rd8 2 Rd16#xx:16Rd16 2 ERd32#xx:32ERd32 4 Rd8#xx:8Rd8 2 Rd16#xx:16Rd16 2 Rd16Rs16Rd16 ERd32#xx:32ERd32 4 ERd32ERs32ERd32 Rd8#xx:8Rd8 2 Rd8Rs8Rd8 Rd16#xx:16Rd16 2 Rd16Rs16Rd16 ERd32#xx:32ERd32 4 2 2 2 ERd32ERs32ERd32 Rd8Rd8 Rd16Rd16 ERd32ERd32 Rd8Rs8Rd8 ERd32ERs32ERd32 Rd16Rs16Rd16 Rd8Rs8Rd8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IHNZVC B2 B W4 W L6 L B2 B W4 W L6 L B2 B W4 W L6 L B W L (3) Logical Instructions AND AND.B #xx:8,Rd Appendix A Instruction Set AND.B Rs,Rd @-ERn/@ERn+ AND.W #xx:16,Rd 2 1 3 2 1 1 2 1 3 2 1 1 2 1 3 2 1 1 1 AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd NOT.L ERd Rev. 6.00 Feb 22, 2005 page 1094 of 1484 REJ09B0103-0600 OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd XOR XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd NOT NOT.B Rd NOT.W Rd Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 1 1 1 1 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa (4) Shift Instructions Mnemonic B B W W L L B B W W MSB L L B B W W L L 2 2 2 2 C MSB LSB 2 0 2 2 2 2 2 LSB C 2 2 2 2 2 C MSB LSB 2 0 2 2 Operation IHNZVC SHAL SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1095 of 1484 REJ09B0103-0600 SHLL.L #2,ERd SHLL.L ERd Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa Mnemonic Operation -- -- -- 0 -- -- -- -- -- -- -- C -- -- -- -- -- -- MSB -- -- LSB C MSB LSB MSB LSB C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B B W W L L B B W W L L B B W W L L 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 IHNZVC SHLR SHLR.B Rd Appendix A Instruction Set SHLR.B #2,Rd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SHLR.W Rd SHLR.W #2,Rd 0 SHLR.L ERd SHLR.L #2,ERd ROTXR.L #2,ERd Rev. 6.00 Feb 22, 2005 page 1096 of 1484 REJ09B0103-0600 ROTXL ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa Mnemonic B B W W C MSB LSB L L B B W W MSB -- 1 L L 2 2 2 2 -- LSB C 2 -- 2 -- 2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 Operation IHNZVC ROTL ROTL.B Rd ROTL.B #2,Rd 1 1 1 1 1 1 1 1 1 1 1 ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L #2,ERd ROTR.L ERd Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1097 of 1484 REJ09B0103-0600 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 1 4 4 5 6 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa Mnemonic B B B B B B B B B B B B B B B B B B B 4 6 4 2 8 6 4 4 2 (#xx:3 of Rd8)0 (#xx:3 of @ERd)0 (#xx:3 of @aa:8)0 (#xx:3 of @aa:16)0 (#xx:3 of @aa:32)0 (Rn8 of Rd8)0 (Rn8 of @ERd)0 (Rn8 of @aa:8)0 (Rn8 of @aa:16)0 8 (Rn8 of @aa:32)1 6 (Rn8 of @aa:16)1 4 (Rn8 of @aa:8)1 4 (Rn8 of @ERd)1 2 (Rn8 of Rd8)1 8 (#xx:3 of @aa:32)1 6 (#xx:3 of @aa:16)1 4 (#xx:3 of @aa:8)1 4 (#xx:3 of @ERd)1 2 (#xx:3 of Rd8)1 Operation IHNZVC BSET BSET #xx:3,Rd Appendix A Instruction Set BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 (5) Bit-Manipulation Instructions BSET #xx:3,@aa:32 BSET Rn,Rd Rev. 6.00 Feb 22, 2005 page 1098 of 1484 REJ09B0103-0600 4 4 5 6 1 4 4 5 6 1 4 4 5 BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 6 1 4 Operand Size #xx Rn @ERn @(d,ERn) @aa @(d,PC) @@aa Mnemonic Operation (Rn8 of @aa:32)0 B B B [ (#xx:3 of @ERd)] B [ (#xx:3 of @aa:8)] B [ (#xx:3 of @aa:16)] B 8 (#xx:3 of @aa:32) [ (#xx:3 of @aa:32)] B B B B 6 4 4 2 (Rn8 of Rd8)[ (Rn8 of Rd8)] 6 (#xx:3 of @aa:16) 4 (#xx:3 of @aa:8) 4 (#xx:3 of @ERd) 2 8 @-ERn/@ERn+ IHNZVC BCLR BCLR Rn,@aa:32 BNOT BNOT #xx:3,Rd (#xx:3 of Rd8)[ (#xx:3 of Rd8)] BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 4 BNOT #xx:3,@aa:16 5 BNOT #xx:3,@aa:32 6 BNOT Rn,Rd 1 4 4 BNOT Rn,@ERd (Rn8 of @ERd)[ (Rn8 of @ERd)] (Rn8 of @aa:8)[ (Rn8 of @aa:8)] (Rn8 of @aa:16) [ (Rn8 of @aa:16)] (Rn8 of @aa:32) 8 [ (Rn8 of @aa:32)] BNOT Rn,@aa:8 BNOT Rn,@aa:16 5 BNOT Rn,@aa:32 B 6 BTST B B B 4 BTST #xx:3,Rd B 2 (#xx:3 of Rd8)Z (#xx:3 of @ERd)Z 4 6 (#xx:3 of @aa:8)Z (#xx:3 of @aa:16)Z 1 3 3 4 BTST #xx:3,@ERd Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1099 of 1484 REJ09B0103-0600 BTST #xx:3,@aa:16 BTST #xx:3,@aa:8 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 5 Operand Size #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa Mnemonic Operation (#xx:3 of @aa:32)Z (Rn8 of Rd8)Z 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 (#xx:3 of @ERd)C (#xx:3 of @aa:8)C (#xx:3 of @aa:16)C (#xx:3 of @aa:32)C (#xx:3 of Rd8)C (#xx:3 of @ERd)C (#xx:3 of @aa:8)C (#xx:3 of @aa:16)C (#xx:3 of @aa:32)C C(#xx:3 of Rd8) C(#xx:3 of @ERd24) C(#xx:3 of @aa:8) (#xx:3 of Rd8)C (Rn8 of @aa:32)Z (Rn8 of @aa:16)Z (Rn8 of @aa:8)Z (Rn8 of @ERd)Z B B B B B B B B B B B B B B B B B B B 2 8 IHNZVC BTST BTST #xx:3,@aa:32 Appendix A Instruction Set BTST Rn,Rd 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:32 BILD #xx:3,@aa:32 Rev. 6.00 Feb 22, 2005 page 1100 of 1484 REJ09B0103-0600 1 4 4 BTST Rn,@aa:16 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 5 6 1 4 Operand Size #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa Mnemonic Operation C(#xx:3 of @aa:16) C(#xx:3 of @aa:32) C(#xx:3 of Rd8) 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 C(#xx:3 of Rd8)C C(#xx:3 of @ERd24)C C(#xx:3 of @aa:8)C C(#xx:3 of @aa:16)C C(#xx:3 of @aa:32)C C[ (#xx:3 of Rd8)]C C[ (#xx:3 of @ERd24)]C C[ (#xx:3 of @aa:8)]C C[ (#xx:3 of @aa:16)]C C[ (#xx:3 of @aa:32)]C C(#xx:3 of Rd8)C C(#xx:3 of @ERd24)C C(#xx:3 of @aa:32) C(#xx:3 of @aa:16) C(#xx:3 of @aa:8) C(#xx:3 of @ERd24) B B B B B B B B B B B B B B B B B B B 2 8 6 IHNZVC BST BST #xx:3,@aa:16 BST #xx:3,@aa:32 BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 4 5 6 1 3 3 4 5 1 3 3 4 5 1 3 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1101 of 1484 REJ09B0103-0600 BOR #xx:3,@ERd BOR BOR #xx:3,Rd Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 3 4 5 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa Mnemonic B B B B B B B B B B B B B B B B B B 6 8 4 4 2 8 6 4 4 2 8 C(#xx:3 of Rd8)C C(#xx:3 of @ERd24)C C(#xx:3 of @aa:8)C C(#xx:3 of @aa:16)C C(#xx:3 of @aa:32)C C[ (#xx:3 of Rd8)]C C[ (#xx:3 of @ERd24)]C C[ (#xx:3 of @aa:8)]C C[ (#xx:3 of @aa:16)]C C[ (#xx:3 of @aa:32)]C 6 C[ (#xx:3 of @aa:16)]C C[ (#xx:3 of @aa:32)]C 4 C[ (#xx:3 of @aa:8)]C 4 C[ (#xx:3 of @ERd24)]C 2 C[ (#xx:3 of Rd8)]C 8 C(#xx:3 of @aa:32)C 6 C(#xx:3 of @aa:16)C 4 C(#xx:3 of @aa:8)C Operation IHNZVC BOR BOR #xx:3,@aa:8 Appendix A Instruction Set BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BIOR BIOR #xx:3,Rd BIOR #xx:3,@ERd 3 3 4 5 1 3 3 4 5 1 3 3 4 5 BIOR #xx:3,@aa:8 BIXOR #xx:3,@aa:32 Rev. 6.00 Feb 22, 2005 page 1102 of 1484 REJ09B0103-0600 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 Addressing Mode/ Instruction Length (Bytes) Operation Condition Code Branching Condition No. of States*1 Advanced 2 3 2 3 2 Operand Size #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa Mnemonic 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 V=0 Z=1 Z=0 C=1 C=0 CZ=1 CZ=0 else next; Never PCPC+d if condition is true then Always IHNZVC (6) Branch Instructions Bcc BRA d:8(BT d:8) BRA d:16(BT d:16) BRN d:8(BF d:8) BRN d:16(BF d:16) BHI d:8 BHI d:16 3 2 3 2 3 2 3 2 3 2 3 2 3 BLS d:8 BLS d:16 BCC d:B(BHS d:8) BCC d:16(BHS d:16) BCS d:8(BLO d:8) BCS d:16(BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1103 of 1484 REJ09B0103-0600 BVC d:16 Addressing Mode/ Instruction Length (Bytes) Operation Condition Code Branching Condition No. of States*1 Advanced 2 3 2 3 Operand Size #xx Rn @ERn @(d,ERn) @aa @(d,PC) @@aa Mnemonic 2 4 2 4 2 4 2 4 2 4 2 4 2 4 NV=1 NV=0 N=1 N=0 V=1 @-ERn/@ERn+ IHNZVC Bcc BVS d:8 Appendix A Instruction Set BVS d:16 BPL d:8 BPL d:16 BMI d:8 2 3 2 3 2 3 BMI d:16 Rev. 6.00 Feb 22, 2005 page 1104 of 1484 REJ09B0103-0600 Z(NV)=0 Z(NV)=1 2 3 2 3 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 2 3 5 4 Operand Size #xx Rn @ERn @(d,ERn) @aa @(d,PC) @@aa Mnemonic Operation PCERn 4 2 2 4 2 4 2 2 PC@SP+ PC@-SP,PCaa:24 PC@-SP,PC@aa:8 PC@-SP,PCERn PC@-SP,PCPC+d:16 PC@-SP,PCPC+d:8 PC@aa:8 PCaa:24 2 @-ERn/@ERn+ IHNZVC JMP JMP @ERn JMP @aa:24 JMP @@aa:8 BSR BSR d:8 BSR d:16 5 4 5 6 5 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 RTS RTS Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1105 of 1484 REJ09B0103-0600 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 8 [13] Operand Size #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa Mnemonic PC@-SP,CCR@-SP, EXR@-SP, Operation IHNZVC Appendix A Instruction Set TRAPA EXR@SP+,CCR@SP+, PC@SP+ Transition to power-down state #xx:8CCR #xx:8EXR 2 2 4 4 6 6 10 10 4 4 6 6 8 8 @ERsEXR @(d:16,ERs)CCR @(d:16,ERs)EXR @(d:32,ERs)CCR @(d:32,ERs)EXR @ERsCCR,ERs32+2ERs32 @ERsEXR,ERs32+2ERs32 @aa:16CCR @aa:16EXR @aa:32CCR @aa:32EXR @ERsCCR Rs8EXR Rs8CCR B2 B4 B B W W W W W W W W W W W W TRAPA #xx:2 (7) System Control Instructions RTE RTE 5 [13] SLEEP SLEEP 2 LDC LDC #xx:8,CCR 1 2 LDC Rs,CCR LDC @(d:16,ERs),CCR LDC @(d:32,ERs),CCR Rev. 6.00 Feb 22, 2005 page 1106 of 1484 REJ09B0103-0600 1 1 3 3 4 4 6 6 4 4 4 4 5 5 LDC #xx:8,EXR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 1 1 3 3 Operand Size #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa Mnemonic Operation CCRRd8 EXRRd8 4 4 6 6 10 10 4 4 6 6 8 8 EXR@(d:32,ERd) CCR@(d:32,ERd) EXR@(d:16,ERd) CCR@(d:16,ERd) EXR@ERd CCR@ERd B B W W W W W W W W W W W W B2 B4 B2 B4 B2 B4 2 2 IHNZVC STC STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) 4 4 6 6 4 4 4 4 5 STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@-ERd ERd32-2ERd32,CCR@ERd ERd32-2ERd32,EXR@ERd CCR@aa:16 EXR@aa:16 CCR@aa:32 EXR@aa:32 CCR#xx:8CCR EXR#xx:8EXR CCR#xx:8CCR EXR#xx:8EXR CCR#xx:8CCR EXR#xx:8EXR 2 PCPC+2 STC EXR,@-ERd STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 5 ANDC ANDC #xx:8,CCR 1 2 ANDC #xx:8,EXR ORC ORC #xx:8,CCR 1 2 ORC #xx:8,EXR XORC XORC #xx:8,CCR 1 2 1 XORC #xx:8,EXR Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1107 of 1484 REJ09B0103-0600 NOP NOP Addressing Mode/ Instruction Length (Bytes) Condition Code Operation IHNZVC No. of States*1 Advanced Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Mnemonic 4 if R4L0 Repeat @ER5@ER6 ER5+1ER5 ER6+1ER6 R4L-1R4L Until R4L=0 else next; 4 if R40 Repeat @ER5@ER6 ER5+1ER5 ER6+1ER6 R4-1R4 Until R4=0 else next; Appendix A Instruction Set (8) Block Transfer Instructions EEPMOV EEPMOV.B 4+2n *2 Rev. 6.00 Feb 22, 2005 page 1108 of 1484 REJ09B0103-0600 4+2n *2 EEPMOV.W Notes: 1. The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. 2. n is the initial value of R4L or R4. 3. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 4. Only register ER0 to ER6 should be used when using the STM/LDM instruction. [1] Seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers. [2] Cannot be used in this LSI. [3] Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. [4] Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. [5] Retains its previous value when the result is zero; otherwise cleared to 0. [6] Set to 1 when the divisor is negative; otherwise cleared to 0. [7] Set to 1 when the divisor is zero; otherwise cleared to 0. [8] Set to 1 when the quotient is negative; otherwise cleared to 0. [9] One additional state is required for execution when EXR is valid. [10] MAC instruction results are indicated in the flags when the STMAC instruction is executed. [11] A maximum of three additional states are required for execution of one of these instructions within three states after execution of a MAC instruction. For example, if there is a one-state instruction (such as NOP) between a MAC instruction and one of these instructions, that instruction will be two states longer. Appendix A Instruction Set A.2 Instruction Codes Table A-2 shows the instruction codes. Rev. 6.00 Feb 22, 2005 page 1109 of 1484 REJ09B0103-0600 Table A-2 Instruction Codes Instruction Format Size 1st byte 8 IMM rs 1 IMM rs 1 0 erd IMM 1 ers 0 erd 0 8 9 IMM rs IMM rs 6 IMM rs 6 IMM 6 0 ers 0 erd 6 F IMM 4 IMM 0 IMM 0 erd abs 1 3 disp 0 disp 1 0 disp 0 disp 0 0 7 6 0 7 6 rd 0 IMM 0 IMM abs abs 0 0 7 6 0 IMM 0 7 6 0 IMM 0 1 0 6 0 0 erd rd rd rd rd 0 erd 0 erd 0 erd rd rd rd 0 7 0 7 0 0 0 0 9 0 E 1 7 6 7 0 0 0 7 7 7 6 6 4 5 4 5 8 1 8 0 A A E C 6 1 6 1 A 6 9 6 rd E rd B B B A A 9 9 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B W W L L L L L B B B B W W L L B B B B B B B 10th byte Instruction Mnemonic ADD ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd Appendix A Instruction Set ADD.L ERs,ERd ADDS ADDS #1,ERd ADDS #2,ERd ADDS #4,ERd ADDX ADDX #xx:8,Rd ADDX Rs,Rd Rev. 6.00 Feb 22, 2005 page 1110 of 1484 REJ09B0103-0600 AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 Bcc BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) Instruction Size 1st byte 4 5 0 disp 3 0 disp 4 0 disp 5 0 disp 6 0 disp 7 0 disp 8 0 disp 9 0 disp A 0 disp B 0 disp C 0 disp D 0 disp E 0 disp F 0 disp disp disp disp disp disp disp disp disp disp disp disp disp 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 8 F 8 E 8 D 8 C 8 B 8 A 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 disp 2 2 disp 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte Mnemonic Instruction Format 10th byte Bcc BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1111 of 1484 REJ09B0103-0600 BLE d:16 Instruction Size 1st byte 7 7 7 6 0 IMM 7 0 IMM 2 0 6 6 7 7 6 6 7 7 7 6 1 IMM 6 7 7 7 6 6 7 7 7 6 6 A 3 0 A 1 0 E abs 7 4 C 0 erd 0 7 4 1 IMM 1 IMM abs abs 4 1 IMM rd 0 0 7 4 1 IMM 0 7 4 1 IMM 0 A 3 0 abs A abs 1 0 7 E abs 1 IMM 7 7 0 7 1 IMM 0 7 7 1 IMM 0 C 1 IMM 0 erd 0 7 7 0 7 1 IMM rd A 3 abs 0 A abs 1 0 7 6 0 7 6 1 IMM 0 E abs 1 IMM 7 6 0 C 1 IMM 0 erd 0 7 6 0 6 1 IMM rd A 3 abs 8 6 2 A abs 1 8 6 2 rn 0 rn 0 F abs 6 2 rn 0 D 0 erd 0 6 2 rn 0 2 rn rd A 3 abs 8 A abs 1 8 7 2 0 F abs 0 IMM 7 2 0 D 0 IMM 0 erd 0 7 2 0 2 0 IMM rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B B B B B B B B B B B B B B B B 10th byte Mnemonic Instruction Format BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd Appendix A Instruction Set BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd Rev. 6.00 Feb 22, 2005 page 1112 of 1484 REJ09B0103-0600 BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 Instruction Size 1st byte 6 1 IMM 0 erd abs 1 abs 1 IMM 6 1 IMM 7 0 abs 3 1 IMM 0 erd abs 1 abs 1 IMM 7 5 abs 3 0 IMM 0 erd abs 1 abs 0 IMM abs 3 0 IMM 0 erd abs 1 abs abs 3 rn 0 erd abs 1 3 8 8 6 1 abs abs 0 6 1 rn rn rd 0 0 6 1 rn 0 6 1 rn 0 8 8 7 7 0 IMM 1 0 1 0 IMM 0 7 1 0 IMM 0 0 0 IMM 7 1 0 rd 0 0 7 7 7 0 IMM 7 0 0 7 7 0 IMM 0 0 0 IMM 7 7 0 rd 0 0 7 5 0 1 IMM 0 7 1 IMM 5 0 0 1 IMM 7 5 0 rd 8 8 6 7 0 6 1 IMM 7 0 0 1 IMM 6 7 0 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 A A F D 1 A A F D 1 A A E C 7 A A E C 5 A A F D 7 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B B B B B B B B B B B B B B B B Mnemonic Instruction Format 10th byte BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1113 of 1484 REJ09B0103-0600 BNOT Rn,@aa:32 Instruction Size 1st byte 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 abs 5 5 6 7 7 abs 1 abs abs 3 0 IMM 0 erd abs 1 3 rn 0 erd rd 0 6 3 rn 0 0 0 7 0 7 3 3 rd 0 IMM 0 IMM abs abs 0 0 7 3 0 IMM 0 7 3 0 IMM 0 8 8 6 6 7 7 7 6 6 6 7 C 3 A A E C 3 A A F 0 IMM 6 7 0 6 7 0 IMM 0 6 7 0 IMM 0 D 0 erd 0 IMM 0 6 7 0 7 0 IMM rd C disp 0 0 5 disp A 3 8 A abs 1 8 6 0 rn 0 6 0 rn 0 F abs 6 0 rn 0 D 0 erd 0 6 0 rn 0 0 rn rd A abs 3 8 7 0 A abs 0 IMM 1 8 7 0 0 0 IMM 0 F abs 0 IMM 7 0 0 D 0 IMM 0 erd 0 7 0 0 0 0 IMM rd A abs 0 IMM 3 0 7 4 0 A abs 0 IMM 1 0 7 4 0 E abs 0 IMM 7 4 0 C 0 IMM 0 erd 0 7 4 0 4 0 IMM rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B B B B B B B B B B B B B B B B B B 10th byte Mnemonic Instruction Format BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET BSET #xx:3,Rd Appendix A Instruction Set BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd Rev. 6.00 Feb 22, 2005 page 1114 of 1484 REJ09B0103-0600 BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR BSR d:8 BSR d:16 BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd Instruction Size 1st byte 7 6 abs abs 6 3 rn 0 6 7 7 7 abs 1 abs 0 IMM 7 5 0 IMM abs 3 A IMM rs 2 IMM rs 2 0 erd IMM 1 ers 0 erd 0 0 0 5 D 7 0 erd 0 erd 0 0 rd 0 erd C 4 5 5 9 9 8 8 F F 5 3 5 1 rs rs rd 0 erd F D D rs rs 5 D rd rd rd rd rd rd rd rd 0 0 0 7 5 0 0 6 6 0 A 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 B B 3 1 1 1 B B B B A F F F A D 9 C rd 1 A A E 0 IMM 7 5 0 C 0 erd 0 IMM 0 7 5 0 5 0 IMM rd A 3 0 A 1 0 6 3 rn 0 E abs 6 3 rn 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B W W L L B B B W W L L B W B W Mnemonic Instruction Format 10th byte BTST BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CLRMAC CMP CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA DAA Rd DAS DAS Rd DEC DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV EEPMOV.B Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1115 of 1484 REJ09B0103-0600 EEPMOV.W Instruction Size 1st byte 1 1 0 erd rd 0 erd rd rd rd 0 erd 0 erd 0 abs abs 0 ern abs abs IMM 4 IMM 0 1 4 0 ers 0 ers 0 ers 0 ers 0 ers 8 D 6 6 1 0 1 4 6 6 D B B 0 ers 0 ers 0 ers 0 0 0 0 0 0 8 0 0 0 0 0 abs abs 6 6 B B disp disp 2 2 0 0 disp disp 4 4 4 4 4 4 4 4 0 1 7 0 7 1 6 F 0 6 F 1 6 9 0 6 9 0 rs rs 1 0 7 0 1 1 0 0 0 0 0 5 0 ern 5 5 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 3 3 1 7 F E D B A 9 B F B 7 B D B 5 A 0 7 7 7 5 7 F 7 D rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W L W L B W W L L B B B B W W W W W W W W W W 10th byte Mnemonic Instruction Format EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC INC.B Rd INC.W #1,Rd Appendix A Instruction Set INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 Rev. 6.00 Feb 22, 2005 page 1116 of 1484 REJ09B0103-0600 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 LDC LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR Instruction Size 1st byte 0 0 0 0 ern+1 0 ern+2 0 ern+3 abs abs 0 0 0 0 0 0 ers 0 ers 0 0 ern 0 erm IMM rs 0 ers 0 ers disp 6 A 2 rd disp 0 ers 0 ers abs 0 abs abs 2 1 erd 1 erd disp 6 A rs A disp 0 erd 1 erd abs 8 A 0 rs 0 ers 0 ers 0 ers rd 0 6 B rd disp 2 rd disp rd rd rs IMM rs abs abs rs 0 rs rs rd rd rd 0 rd rd rd 6 D 0 0 F 0 6 6 7 6 2 6 6 6 6 7 6 3 6 6 7 0 6 6 7 8 F 9 D 9 A A rs C 8 E 8 A A rd C 8 E 8 C rd 1 6 3 3 3 2 1 3 0 6 D 7 1 2 0 6 D 7 1 1 0 6 D 7 1 4 1 6 B 2 1 4 0 6 B 2 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W W L L L L L B B B B B B B B B B B B B B B B W W W W W 10th byte Mnemonic Instruction Format LDC LDC @aa:32,CCR LDC @aa:32,EXR LDM*3 LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC LDMAC ERs,MACH LDMAC ERs,MACL MAC MAC @ERn+,@ERm+ MOV MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa :16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1117 of 1484 REJ09B0103-0600 MOV.W @(d:32,ERs),Rd Instruction Size 1st byte 6 0 ers 0 abs abs 2 1 erd 1 erd disp 6 disp B A rs 0 erd 1 erd 8 abs abs IMM A 0 0 erd 1 ers 0 erd 0 0 ers 0 erd 0 ers 0 erd disp 6 B 2 0 erd disp 0 ers 0 ers 0 erd 0 0 erd 0 erd 2 1 erd 0 ers 1 erd 0 ers 0 erd 0 6 B disp A 0 ers disp abs abs 0 0 0 0 0 0 0 0 0 0 0 0 0 6 B 0 6 B 8 A 0 6 D 0 7 8 0 6 F 0 6 9 0 6 B 0 6 B 0 6 D 0 7 8 0 6 F 0 6 9 rs rs rs 0 rs rs rd rd 6 6 6 6 7 6 6 6 7 0 0 0 0 0 0 0 0 0 0 0 0 0 Cannot be used in this LSI 1 1 1 1 1 1 1 1 1 1 1 1 F A B B D 8 F 9 B B D rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W W W W W W W W W L L L L L L L L L L 10th byte Mnemonic Instruction Format MOV MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) Appendix A Instruction Set MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,Rd MOV.L ERs,ERd MOV.L @ERs,ERd Rev. 6.00 Feb 22, 2005 page 1118 of 1484 REJ09B0103-0600 L L L B B B W B W 5 2 rs 5 0 rs rd 0 erd 0 1 C 0 0 1 C 0 5 5 0 2 rs rs rd 0 erd 1 erd 0 ers 0 ers 0 ers abs abs MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16 ,ERd MOV.L @aa:32 ,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd)*1 L MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE MOVFPE @aa:16,Rd MOVTPE MOVTPE Rs,@aa:16 MULXS MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd Instruction Size 1st byte 1 1 1 0 1 1 1 C IMM rs 4 IMM rs 4 0 erd 0 6 4 0 ers 0 erd IMM 4 0 4 IMM 7 0 6 D 7 0 ern F 0 6 D F 0 ern 8 C 9 D B 0 erd 0 erd F rd rd rd rd 0 rn 0 rn 1 IMM F rd rd rd 1 7 6 7 0 0 0 6 0 6 0 1 1 1 1 1 1 2 2 2 2 2 2 1 D 1 D 1 4 1 A 4 9 4 rd 7 0 erd 3 7 1 rd 7 0 rd 0 0 0 7 0 erd B 7 9 rd 7 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B W L B W L B B W W L L B B W L W L B B W W L L Mnemonic Instruction Format 10th byte NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOP NOT NOT.B Rd NOT.W Rd NOT.L ERd OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC ORC #xx:8,CCR ORC #xx:8,EXR POP POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.B #2, Rd ROTL.W Rd ROTL.W #2, Rd ROTL.L ERd Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1119 of 1484 REJ09B0103-0600 ROTL.L #2, ERd Instruction Size 1st byte 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 erd 0 erd 0 0 rd rd rd rd 0 erd 0 erd 1 5 5 1 1 1 1 1 1 0 F 0 B 0 D 0 9 0 C 0 8 4 7 6 7 3 7 3 3 3 5 rd 3 1 rd 3 4 rd 3 0 rd 2 0 erd 7 2 0 erd 3 2 5 rd 2 1 rd 2 4 rd 2 0 rd 3 0 erd F 3 0 erd B 3 D rd 3 9 rd 3 C rd 3 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B W W L L B B W W L L B B W W L L B B W W L L 10th byte Mnemonic Instruction Format ROTR ROTR.B Rd ROTR.B #2, Rd ROTR.W Rd ROTR.W #2, Rd ROTR.L ERd ROTR.L #2, ERd Appendix A Instruction Set ROTXL ROTXL.B Rd ROTXL.B #2, Rd ROTXL.W Rd ROTXL.W #2, Rd ROTXL.L ERd ROTXL.L #2, ERd Rev. 6.00 Feb 22, 2005 page 1120 of 1484 REJ09B0103-0600 ROTXR ROTXR.B Rd ROTXR.B #2, Rd ROTXR.W Rd ROTXR.W #2, Rd ROTXR.L ERd ROTXR.L #2, ERd RTE RTE RTS RTS SHAL SHAL.B Rd SHAL.B #2, Rd SHAL.W Rd SHAL.W #2, Rd SHAL.L ERd SHAL.L #2, ERd Instruction Size 1st byte 1 1 1 1 1 1 1 1 1 1 1 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 rd rd 0 6 6 6 6 7 7 0 1 4 6 6 F F 8 8 D D 9 9 1 0 1 0 1 1 erd 1 erd 1 erd 1 erd 0 erd 0 erd 1 erd 1 erd 0 0 0 0 0 0 0 0 6 6 B B disp disp A A 0 0 disp disp 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 4 1 4 1 4 1 4 1 4 1 4 1 4 2 1 2 0 1 8 1 7 1 3 1 5 1 1 1 4 1 0 0 7 0 3 0 5 rd 0 1 rd 0 4 rd 0 0 rd 1 0 erd F 1 0 erd B 1 D rd 1 9 rd 1 C rd 1 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B W W L L B B W W L L B B W W L L B B W W Mnemonic Instruction Format 10th byte SHAR SHAR.B Rd SHAR.B #2, Rd SHAR.W Rd SHAR.W #2, Rd SHAR.L ERd SHAR.L #2, ERd SHLL SHLL.B Rd SHLL.B #2, Rd SHLL.W Rd SHLL.W #2, Rd SHLL.L ERd SHLL.L #2, ERd SHLR SHLR.B Rd SHLR.B #2, Rd SHLR.W Rd SHLR.W #2, Rd SHLR.L ERd SHLR.L #2, ERd SLEEP SLEEP STC STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) W STC.W EXR,@(d:16,ERd) W STC.W CCR,@(d:32,ERd) W STC.W EXR,@(d:32,ERd) W W W STC.W CCR,@-ERd Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1121 of 1484 REJ09B0103-0600 STC.W EXR,@-ERd Instruction Size 1st byte 0 0 0 0 0 0 ern 0 ern 0 ern 0 0 0 0 1 7 1 7 1 1 1 1 B IMM rs E 0 erd 00 IMM IMM rs 5 rs 5 F 0 0 erd 6 5 rd IMM 0 ers 0 erd rd rd IMM 0 0 7 B C rd 1 0 5 D 1 7 6 7 0 1 A 5 9 5 rd 7 1 E rd B 9 0 erd B 8 0 erd B 0 0 erd A 1 ers 0 erd A IMM 3 0 erd 9 rs rd 9 IMM 3 rd 8 rs rd 2 3 0 ers 2 2 0 ers 1 3 0 6 D F 1 2 0 6 D F 1 1 0 6 D F 1 abs 4 1 6 B A 0 1 abs 4 0 6 B A 0 1 abs 4 1 6 B 8 0 1 abs 4 0 6 B 8 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W W W W L L L L L B W W L L L L L B B B B B W W L L 10th byte Mnemonic Instruction Format STC STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM*3 STM.L(ERn-ERn+1), @-SP STM.L (ERn-ERn+2), @-SP Appendix A Instruction Set STM.L (ERn-ERn+3), @-SP STMAC STMAC MACH,ERd STMAC MACL,ERd SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd Rev. 6.00 Feb 22, 2005 page 1122 of 1484 REJ09B0103-0600 SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd SUBX SUBX #xx:8,Rd SUBX Rs,Rd TAS TAS @ERd*2 TRAPA TRAPA #x:2 XOR XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd Instruction Size 1st byte 0 0 1 4 1 0 5 IMM 5 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B Mnemonic Instruction Format 10th byte XORC XORC #xx:8,CCR XORC #xx:8,EXR Notes: 1. Bit 7 of the 4th byte of the MOV.L ERs, @(d:32,ERd) instruction can be either 1 or 0. 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 3. Only register ER0 to ER6 should be used when using the STM/LDM instruction. Legend: IMM: abs: disp: rs, rd, rn: ers, erd, ern, erm: Immediate data (2, 3, 8, 16, or 32 bits) Absolute address (8, 16, 24, or 32 bits) Displacement (8, 16, or 32 bits) Register field (4 bits specifying an 8-bit or 16-bit register. The symbols rs, rd, and rn correspond to operand symbols Rs, Rd,and Rn) Register field (3 bits specifying an address register or 32-bit register. The symbols ers, erd, ern, and erm correspond to operand symbols ERs, ERd, ERn, and ERm) The register fields specify general registers as follows. 16-Bit Register Register Field 0000 0001 * * * 0111 1000 1001 * * * 1111 R0 R1 * * * R7 E0 E1 * * * E7 0000 0001 * * * 0111 1000 1001 * * * 1111 General Register Register Field General Register R0H R1H * * * R7H R0L R1L * * * R7L 8-Bit Register Address Register 32-Bit Register Register Field General Register 000 001 * * * 111 ER0 ER1 * * * ER7 Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1123 of 1484 REJ09B0103-0600 A.3 Table A-3 Operation Code Map (1) Instruction when most significant bit of BH is 0. 2nd byte BH BL Instruction when most significant bit of BH is 1. Instruction code 1st byte Appendix A Instruction Set AH AL AL 2 4 9 C D MOV CMP ADD SUB A B ORC OR MOV.B XOR AND Table A.3(2) XORC ANDC LDC 5 6 7 8 3 AH 0 1 E ADDX SUBX F Operation Code Map 0 NOP 1 Table A.3(2) LDC Table STC A.3(2) STMAC LDMAC Table Table Table A.3(2) A.3(2) A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A-3 shows the operation code map. Rev. 6.00 Feb 22, 2005 page 1124 of 1484 REJ09B0103-0600 BHI BCC RTS OR MOV Table A.3(2) XOR AND BST MOV BSR RTE TRAPA Table A.3(2) JMP BCS BNE BEQ BVC BVS BPL DIVXU BTST BLS BMI BGE BSR MOV Table A.3(3) BLT BGT JSR BLE BIST BOR BLD BXOR BAND BIOR BILD BIXOR BIAND ADD ADDX CMP SUBX OR XOR AND MOV Table A.3(2) Table A.3(2) EEPMOV 2 3 4 BRA BRN 5 MULXU DIVXU MULXU 6 BSET BNOT BCLR 7 8 9 A B C D E F Table A-3 Operation Code Map (2) 2nd byte BH BL Instruction code AL 1st byte AH BH 2 5 7 SLEEP CLRMAC MAC 6 B 8 9 A STM STC LDC 3 4 AH AL 0 1 C Table A.3(3) ADD D Table A.3(3) E TAS F Table A.3(3) 01 MOV LDM 0A INC INC ADDS INC 0B ADDS INC MOV INC 0F SHLL SHLL SHLR ROTXL ROTXR EXTU EXTU ROTL ROTR NEG SHAR SHAL SHLR ROTXL ROTXR NOT DAA 10 SHLL SHAL SHAR ROTL ROTR NEG SUB EXTS SHAL SHAR ROTL ROTR EXTS 11 SHLR 12 ROTXL 13 ROTXR 17 NOT 1A DEC DEC DEC SUBS 1B SUBS DEC CMP DEC 1F BHI BCS MOV CMP OR OR CMP SUB SUB Table * A.3(4) MOVFPE XOR XOR BLS BCC DAS BNE BEQ BVC MOV AND AND BVS BPL MOV BMI 58 BRA BRN BGE MOVTPE* BLT BGT BLE 6A MOV Table A.3(4) 79 MOV ADD 7A MOV ADD Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1125 of 1484 REJ09B0103-0600 Note: * Cannot be used in this LSI. Table A-3 Operation Code Map (3) 2nd byte BH BL CH CL DH DL 3rd byte 4th byte Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1. Appendix A Instruction Set Instruction code AL 1st byte AH CL 1 MULXS DIVXS OR BTST BTST BCLR BCLR BTST BTST BCLR BCLR XOR AND 2 3 4 5 6 7 8 9 A AH AL BH BL CH 0 B C D E F 01C05 MULXS Rev. 6.00 Feb 22, 2005 page 1126 of 1484 REJ09B0103-0600 BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 01D05 DIVXS 01F06 7Cr06 *1 7Cr07 *1 7Dr06 *1 BSET BNOT 7Dr07 *1 BSET BNOT 7Eaa6 *2 7Eaa7 *2 7Faa6 *2 BSET BNOT 7Faa7 *2 BSET BNOT Notes: 1. r is the register specification field. 2. aa is the absolute address specification. Table A-3 Operation Code Map (4) 2nd byte BH BL CH CL DH DL EH EL FH FL Instruction when most significant bit of FH is 0. Instruction when most significant bit of FH is 1. 1 BTST BXOR BAND BLD BOR BIXOR BIAND BILD BIOR BST BIST 2 3 4 5 6 7 8 9 A B C D E F 3rd byte 4th byte 5th byte 6th byte Instruction code AL 1st byte AH EL AHALBHBLCHCLDHDLEH 0 6A10aaaa6* 6A10aaaa7* 6A18aaaa6* BCLR BSET BNOT 6A18aaaa7* Instruction code AL BH BL CH CL DH DL EH 1st byte 2nd byte 3rd byte 4th byte 5th byte EL 6th byte FH FL 7th byte GH GL 8th byte HH HL Instruction when most significant bit of HH is 0. Instruction when most significant bit of HH is 1. AH GL 1 4 5 BTST 2 3 AHALBHBL ... FHFLGH 0 6 7 8 9 A B C D E F 6A30aaaaaaaa6* 6A30aaaaaaaa7* 6A38aaaaaaaa6* BCLR BSET BNOT BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 6A38aaaaaaaa7* Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1127 of 1484 REJ09B0103-0600 Note: * aa is the absolute address specification. Appendix A Instruction Set A.4 Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the CPU. Table A-5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A-4 indicates the number of states required for each cycle. The number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I x SI + J x SJ + K x SK + L x SL + M x SM + N x SN Examples: Advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. 1. BSET #0, @FFFFC7:8 From table A-5: I = L = 2, J = K = M = N = 0 From table A-4: SI = 4, SL = 2 Number of states required for execution = 2 x 4 + 2 x 2 = 12 2. JSR @@30 From table A-5: I = J = K = 2, L = M = N = 0 From table A-4: SI = SJ = SK = 4 Number of states required for execution = 2 x 4 + 2 x 4 + 2 x 4 = 24 Rev. 6.00 Feb 22, 2005 page 1128 of 1484 REJ09B0103-0600 Appendix A Instruction Set Table A-4 Number of States per Cycle Access Conditions On-Chip Supporting Module External Device 8-Bit Bus 16-Bit Bus Cycle Instruction fetch Stack operation Byte data access Word data access Internal operation SI SK SL SM SN On-Chip 8-Bit Memory Bus 1 4 16-Bit Bus 2 2-State 3-State 2-State 3-State Access Access Access Access 4 6 + 2m 2 3+m Branch address read SJ 2 4 1 1 1 2 4 1 3+m 6 + 2m 1 1 1 Legend: m: Number of wait states inserted into external device access Rev. 6.00 Feb 22, 2005 page 1129 of 1484 REJ09B0103-0600 Appendix A Instruction Set Table A-5 Number of Cycles in Instruction Execution Instruction Fetch Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Internal Operation N Instruction ADD Mnemonic ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd I 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 2 1 2 2 3 4 2 2 2 2 2 2 2 2 2 ADDS ADDX ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 1 1 1 1 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 Rev. 6.00 Feb 22, 2005 page 1130 of 1484 REJ09B0103-0600 Appendix A Instruction Set Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Instruction Fetch Instruction Bcc Mnemonic BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 I 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3 4 1 2 2 3 4 Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 Rev. 6.00 Feb 22, 2005 page 1131 of 1484 REJ09B0103-0600 Appendix A Instruction Set Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Instruction Fetch Instruction BIAND Mnemonic BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR BIOR #xx:8,Rd BIOR #xx:8,@ERd BIOR #xx:8,@aa:8 BIOR #xx:8,@aa:16 BIOR #xx:8,@aa:32 BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 1 1 1 1 1 1 1 1 Rev. 6.00 Feb 22, 2005 page 1132 of 1484 REJ09B0103-0600 Appendix A Instruction Set Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Instruction Fetch Instruction BNOT Mnemonic BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR BSR d:8 BSR d:16 BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 2 2 1 2 2 3 4 Internal Operation N 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 1 2 2 2 2 Rev. 6.00 Feb 22, 2005 page 1133 of 1484 REJ09B0103-0600 Appendix A Instruction Set Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Instruction Fetch Instruction BTST Mnemonic BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CMP CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA DAS DEC DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 1*3 11 19 11 19 Rev. 6.00 Feb 22, 2005 page 1134 of 1484 REJ09B0103-0600 Appendix A Instruction Set Branch Address Read J Byte Stack Data Operation Access K L 2 2n+2* Instruction Fetch Instruction EEPMOV Mnemonic EEPMOV.B EEPMOV.W EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 LDC LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR I 2 2 1 1 1 1 1 1 1 2 2 2 2 2 2 1 2 1 1 2 2 3 3 5 5 2 2 3 3 4 4 Word Data Access M Internal Operation N 2n+2*2 1 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Rev. 6.00 Feb 22, 2005 page 1135 of 1484 REJ09B0103-0600 Appendix A Instruction Set Branch Address Read J Byte Stack Data Operation Access K 4 6 8 L Word Data Access M Instruction Fetch Instruction LDM Mnemonic LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC LDMAC ERs,MACH LDMAC ERs,MACL MAC MOV MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd I 2 2 2 1 1 2 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 2 1 1 2 4 1 2 3 1 Internal Operation N 1 1 1 1* 1* 3 3 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Rev. 6.00 Feb 22, 2005 page 1136 of 1484 REJ09B0103-0600 Appendix A Instruction Set Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M 1 1 1 1 1 1 Instruction Fetch Instruction MOV Mnemonic MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE MOVTPE MULXS MOVFPE @:aa:16,Rd MOVTPE Rs,@:aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOP NOT.B Rd NOT.W Rd NOT.L ERd 2 2 1 1 1 1 1 1 1 1 1 I 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 Internal Operation N 2 2 2 2 2 2 2 2 2 2 2 2 1 1 Can not be used in this LSI 2 3 2 3 Rev. 6.00 Feb 22, 2005 page 1137 of 1484 REJ09B0103-0600 Appendix A Instruction Set Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Instruction Fetch Instruction OR Mnemonic OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC ORC #xx:8,CCR ORC #xx:8,EXR POP POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd ROTXL ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd I 1 1 2 1 3 2 1 2 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Internal Operation N 1 2 1 2 1 1 1 1 Rev. 6.00 Feb 22, 2005 page 1138 of 1484 REJ09B0103-0600 Appendix A Instruction Set Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Instruction Fetch Instruction ROTXR Mnemonic ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd RTE RTS SHAL RTE RTS SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP SLEEP I 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Internal Operation N 2/3*1 2 1 1 1 Rev. 6.00 Feb 22, 2005 page 1139 of 1484 REJ09B0103-0600 Appendix A Instruction Set Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Instruction Fetch Instruction STC Mnemonic STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd I 1 1 2 2 Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 4 6 8 1 1 1 0* 3 STC.W CCR,@(d:16,ERd) 3 STC.W EXR,@(d:16,ERd) 3 STC.W CCR,@(d:32,ERd) 5 STC.W EXR,@(d:32,ERd) 5 STC.W CCR,@-ERd STC.W EXR,@-ERd STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM STM.L (ERn-ERn+1), @-SP STM.L (ERn-ERn+2), @-SP STM.L (ERn-ERn+3), @-SP STMAC STMAC MACH,ERd STMAC MACL,ERd SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS SUBX TAS* 4 2 2 3 3 4 4 2 2 2 1 1 1 2 1 3 1 1 1 1 2 2 2 2/3*1 2 1 1 0*3 SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd TRAPA #x:2 TRAPA 2 Rev. 6.00 Feb 22, 2005 page 1140 of 1484 REJ09B0103-0600 Appendix A Instruction Set Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Instruction Fetch Instruction XOR Mnemonic XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC XORC #xx:8,CCR XORC #xx:8,EXR I 1 1 2 1 3 2 1 2 Internal Operation N Notes: 1. 2 when EXR is invalid, 3 when EXR is valid. 2. When n bytes of data are transferred. 3. An internal operation may require between 0 and 3 additional states, depending on the preceding instruction. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev. 6.00 Feb 22, 2005 page 1141 of 1484 REJ09B0103-0600 Appendix A Instruction Set A.5 Bus States during Instruction Execution Table A-6 indicates the types of cycles that occur during instruction execution by the CPU. See table A-4 for the number of states per cycle. How to Read the Table: Order of execution Instruction JMP@aa:24 1 R:W 2nd 2 3 4 5 6 7 8 Internal operation, R:W EA 1 state End of instruction Read effective address (word-size read) No read or write Read 2nd word of current instruction (word-size read) Legend R:B R:W W:B W:W :M 2nd 3rd 4th 5th NEXT EA VEC Byte-size read Word-size read Byte-size write Word-size write Transfer of the bus is not performed immediately after this cycle Address of 2nd word (3rd and 4th bytes) Address of 3rd word (5th and 6th bytes) Address of 4th word (7th and 8th bytes) Address of 5th word (9th and 10th bytes) Address of next instruction Effective address Vector address Rev. 6.00 Feb 22, 2005 page 1142 of 1484 REJ09B0103-0600 Appendix A Instruction Set Figure A-1 shows timing waveforms for the address bus and the , , and signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. Address bus RD HWR, LWR High level R:W 2nd Fetching 3rd byte of instruction Fetching 4th byte of instruction Internal operation R:W EA Fetching 1nd byte of instruction at jump address Fetching 2nd byte of instruction at jump address Figure A-1 Address Bus, , , and Timing (8-Bit Bus, Three-State Access, No Wait States) Rev. 6.00 Feb 22, 2005 page 1143 of 1484 REJ09B0103-0600 RWL RWH DR RWL RWH DR Table A-6 Instruction Execution Cycles 2 3 4 5 6 7 8 9 R:W NEXT R:W 3rd R:W NEXT Appendix A Instruction Set R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W NEXT Rev. 6.00 Feb 22, 2005 page 1144 of 1484 REJ09B0103-0600 Instruction ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC #xx:8,CCR ANDC #xx:8,EXR BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 1 R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT 3 R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA Instruction BLE d:8 BRA d:16 (BT d:16) R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:B:M EA R:B:M EA R:W 3rd 1 R:W NEXT R:W 2nd 4 5 6 7 8 9 BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 2 R:W EA Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state R:W:M NEXT W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1145 of 1484 REJ09B0103-0600 BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 2 R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1146 of 1484 REJ09B0103-0600 3 R:W 4th 4 R:B:M EA 5 6 R:W:M NEXT W:B EA 7 8 9 R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT 1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT Instruction BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT #xx:3,Rd 2 R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:W EA Internal operation, 1 state R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:W:M stack (H) R:W EA W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA W:W stack (L) W:W:M stack (H) W:W stack (L) R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA Instruction BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR d:8 BSR d:16 1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd 3 R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th 4 5 6 W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA 7 8 9 Rev. 6.00 Feb 22, 2005 page 1147 of 1484 REJ09B0103-0600 R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA Appendix A Instruction Set 2 R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd Internal operation, 1 state R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1148 of 1484 REJ09B0103-0600 1 R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT 3 4 5 R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT 6 7 8 9 R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT Internal operation, 11 states R:W NEXT Internal operation, 19 states Internal operation, 11 states Internal operation, 19 states R:B EAd*1 R:B EAs*2 W:B EAd*2 R:B EAs*1 R:B EAs*1 R:B EAd*1 R:B EAs*2 W:B EAd*2 Repeated n times*2 R:W NEXT R:W NEXT Instruction BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd Instruction INC.W #1/2,Rd INC.L #1/2,ERd JMP @ERn JMP @aa:24 R:W NEXT R:W NEXT R:W 2nd R:W EA R:W EA Internal operation, R:W EA 1 state R:W:M aa:8 R:W aa:8 Internal operation, R:W EA 1 state R:W EA W:W:M stack (H) W:W stack (L) Internal operation, R:W EA W:W:M stack (H) W:W stack (L) 1 state R:W:M aa:8 R:W aa:8 W:W:M stack (H) W:W stack (L) R:W NEXT 1 R:W NEXT R:W NEXT R:W NEXT R:W 2nd 2 3 4 5 6 7 8 9 JMP @@aa:8 JSR @ERn JSR @aa:24 JSR @@aa:8 LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR R:W NEXT R:W NEXT R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W NEXT R:W EA R:W EA R:W 5th R:W 5th R:W EA R:W NEXT R:W NEXT R:W EA R:W EA R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W:M stack (H)*3 R:W stack (L)*3 R:W:M stack (H)*3 R:W stack (L)*3 R:W:M stack (H)*3 R:W stack (L)*3 Repeated n times *3 R:W EA R:W EA R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM.L @SP+, (ERn-ERn+1)*9 LDM.L @SP+,(ERn-ERn+2)*9 LDM.L @SP+,(ERn-ERn+3)*9 R:W 2nd R:W NEXT Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1149 of 1484 REJ09B0103-0600 LDMAC ERs,MACH R:W EA R:W EA R:W NEXT R:W NEXT R:W 4th R:W 4th Internal operation, 1 state R:W NEXT Internal operation, 1 state R:W 3rd R:W NEXT R:W 3rd R:W NEXT R:W 3rd R:W 4th R:W 3rd R:W 4th R:W:M NEXT Internal operation, 1 state R:W NEXT Internal operation, 1 state R:W NEXT Internal operation, 1 state Internal operation, 1 state Instruction LDMAC ERs,MACL R:W EAm 1 R:W NEXT 2 3 Internal operation, 1 state R:W NEXT R:W EAh 4 5 6 7 8 9 Appendix A Instruction Set MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd R:B EA R:W 4th R:B EA R:W NEXT R:B EA R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:B EA R:W NEXT R:B EA Rev. 6.00 Feb 22, 2005 page 1150 of 1484 REJ09B0103-0600 R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT W:B EA R:W 4th W:B EA R:W NEXT W:B EA R:B EA R:W NEXT R:W 3rd Internal operation, 1 state R:B EA R:W NEXT R:W 3rd W:B EA R:W NEXT R:W 3rd Internal operation, 1 state W:B EA R:W NEXT R:W 3rd R:W NEXT W:B EA R:W NEXT W:B EA R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W EA R:W 4th R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:B EA R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT W:W EA R:E 4th W:W EA W:W EA R:W NEXT R:W 2nd R:W 2nd R:W NEXT W:W EA R:W EA R:W NEXT R:W 3rd Internal operation, 1 state R:W NEXT R:W 3rd W:W EA R:W NEXT R:W 3rd Internal operation, 1 state R:W NEXT R:W 3rd W:W EA MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+, Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 2 R:W 3rd 3 R:W NEXT 4 5 6 7 8 9 Instruction MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd R:W:M NEXT R:W:M 3rd R:W:M 3rd R:W:M NEXT R:W EA+2 R:W NEXT R:W EA+2 R:W:M EA R:W EA+2 R:W EA+2 R:W:M EA R:W EA+2 R:W EA+2 R:W:M EA R:W 5th R:W:M EA 1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd W:W EA+2 R:W NEXT W:W EA+2 W:W:M EA W:W EA+2 W:W:M EA W:W EA+2 W:W EA+2 W:W:M EA R:W NEXT R:W:M EA R:W NEXT R:W:M 4th Internal operation, 1 state R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W 4th R:W 2nd R:W:M NEXT W:W:M EA R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W:M 4th R:W 2nd R:W:M NEXT Internal operation, 1 state R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W 4th Cannot be used in this LSI R:W:M EA R:W NEXT W:W EA+2 W:W:M EA R:W 5th W:W:M EA R:W NEXT Internal operation, 2 states R:W NEXT Internal operation, 3 states Internal operation, 2 states Internal operation, 3 states R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W NEXT MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1151 of 1484 REJ09B0103-0600 Instruction POP.W Rn R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W stack (EXR) R:W:M stack (H) R:W stack (H) R:W stack (L) 1 state R:W stack (L) R:W NEXT R:W NEXT Internal operation, R:W*4 1 state Internal operation, R:W*4 1 R:W NEXT R:W EA+2 5 6 7 8 9 POP.L ERn PUSH.W Rn W:W EA+2 Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1152 of 1484 REJ09B0103-0600 2 3 4 Internal operation, R:W EA 1 state R:W:M NEXT Internal operation, R:W:M EA 1 state Internal operation, W:W EA 1 state R:W:M NEXT Internal operation, W:W:M EA 1 state PUSH.L ERn ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd RTE RTS SHAL.B Rd 2 3 4 5 6 7 8 9 Internal operation:M Instruction SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@-ERd R:W NEXT R:W NEXT R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W NEXT W:W EA W:W EA R:W 5th R:W 5th W:W EA 1 R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT W:W EA W:W EA STC EXR,@-ERd R:W 2nd R:W 2nd R:W 3rd R:W 3rd R:W 2nd R:W NEXT W:W EA W:W EA W:W EA Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1153 of 1484 REJ09B0103-0600 W:W EA W:W EA R:W NEXT R:W NEXT R:W 4th R:W 4th Internal operation, 1 state Internal operation, 1 state R:W NEXT R:W NEXT STC CCR,@aa:16 STC EXR,@aa:16 1 Instruction STC CCR,@aa:32 R:W 2nd STC EXR,@aa:32 R:W 2nd STM.L(ERn-ERn+1),@-SP*9 R:W 2nd W:W:M stack (H)*3 W:W stack (L)*3 W:W:M stack (H)*3 W:W stack (L)*3 4 5 R:W NEXT W:W EA R:W NEXT W:W EA W:W:M stack (H)*3 W:W stack (L)*3 6 7 8 9 STM.L(ERn-ERn+2),@-SP*9 R:W 2nd Appendix A Instruction Set STM.L(ERn-ERn+3),@-SP*9 R:W 2nd 2 3 R:W 3rd R:W 4th R:W 3rd R:W 4th R:W:M NEXT Internal operation, 1 state R:W:M NEXT Internal operation, 1 state R:W:M NEXT Internal operation, 1 state R:W NEXT R:W 3rd R:W NEXT Rev. 6.00 Feb 22, 2005 page 1154 of 1484 REJ09B0103-0600 R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:B:M EA Internal operation, W:W stack (L) 1 state W:B EA W:W stack (H) W:W stack (EXR) R:W:M VEC R:W VEC+2 Internal operation, R:W*7 1 state R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd STMAC MACH,ERd STMAC MACL,ERd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd*8 TRAPA #x:2 XOR.B #xx8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC #xx:8,CCR XORC #xx:8,EXR R:W NEXT Instruction Reset exception handling W:W stack (EXR) R:W:M VEC R:W VEC+2 Internal operation, R:W*7 1 state 1 R:W VEC 2 R:W VEC+2 5 6 7 8 9 Interrupt exception handling R:W*6 3 4 Internal operation, R:W*5 1 state Internal operation, W:W stack (L) W:W stack (H) 1 state Notes: 1. EAs is the contents of ER5. EAd is the contents of ER6. 2. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these bus cycles are not executed. 3. Repeated two times to save or restore two registers, three times for three registers, or four times for four registers. 4. Start address after return. 5. Start address of the program. 6. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery from sleep mode or software standby mode the read operation is replaced by an internal operation. 7. Start address of the interrupt-handling routine. 8. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 9. Only register ER0 to ER6 should be used when using the STM/LDM instruction. Appendix A Instruction Set Rev. 6.00 Feb 22, 2005 page 1155 of 1484 REJ09B0103-0600 Appendix A Instruction Set A.6 Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below. m= 31 for longword operands 15 for word operands 7 for byte operands Si Di Ri Dn -- The i-th bit of the source operand The i-th bit of the destination operand The i-th bit of the result The specified bit in the destination operand Not affected Modified according to the result of the instruction (see definition) 0 1 * Z' C' Always cleared to 0 Always set to 1 Undetermined (no guaranteed value) Z flag before instruction execution C flag before instruction execution Rev. 6.00 Feb 22, 2005 page 1156 of 1484 REJ09B0103-0600 Appendix A Instruction Set Table A-7 Instruction ADD Condition Code Modification H N Z V C Definition N = Rm Z= * * ...... * + V = Sm * Dm * ADDS ADDX ---------- * * Rm C = Sm * Dm + Dm * + Sm * N = Rm V = Sm * Dm * AND ANDC BAND Bcc BCLR BIAND BILD BIOR BIST BIXOR BLD BNOT BOR BSET BSR BST BTST BXOR -------- ---------- ---------- -------- -------- ---------- -------- -------- ---------- -------- ---------- ---------- ---------- -------- C = C' * ---- ---- Z= C = C' + Dn C = Dn C= -------- C = C' * -- 0 -- N = Rm Z= * C = Sm * Dm + Dm * Stores the corresponding bits of the result. No flags change when the operand is EXR. C = C' * Dn 'C nD + nD 'C C = C' * Dn + nD C = C' + mR mR mD mS mR 0R * * Dn Rev. 6.00 Feb 22, 2005 page 1157 of 1484 REJ09B0103-0600 0R 1-mR mR mR Z = Z' * * ...... * + * * Rm + Sm * * ...... * 4-mR 4-mR H = Sm-4 * Dm-4 + Dm-4 * + Sm-4 * 4-mR mR mR mD mS mR 0R 1-mR mR nD nD nD 4-mR H = Sm-4 * Dm-4 + Dm-4 * + Sm-4 * Appendix A Instruction Set Instruction CLRMAC CMP H N Z V C Definition ---------- N = Rm Z= V= * C = Sm * DAA * * N = Rm Z= DAS * * * + * Rm + Sm * Rm C: decimal arithmetic carry N = Rm C: decimal arithmetic borrow DEC -- -- N = Rm V = Dm * DIVXS DIVXU EEPMOV EXTS EXTU INC -- -- ---- ---- Z= Z= ---------- -- --0 -- 0 0 -- -- -- Z= Z= Z= V= JMP JSR LDC LDM LDMAC MAC ---------- ---------- ---------- ---------- ---------- Stores the corresponding bits of the result. No flags change when the operand is EXR. * * Z= * * ...... * Z= * * ...... * N = Sm * N = Sm + N = Rm * * N = Rm * Rm Rev. 6.00 Feb 22, 2005 page 1158 of 1484 REJ09B0103-0600 0R * ...... * 0R 0R 1-mR mR 1-mR mR * * ...... * * ...... * 0S * ...... * 0S * Dm ...... * * 0R * ...... * mD * Dm * 4-mD 4-mD + Sm * H = Sm-4 * + * Rm-4 + Sm-4 * Rm-4 0R 0R 0R * ...... * mD mD mR mS 1-mR mR 1-mS mS mS mD mR 1-mR mR 1-mR mR 1-mR mR mD 1-mR mR 1-mS mS * Rm Appendix A Instruction Set Instruction MOV MOVFPE MOVTPE MULXS MULXU NEG -- ---- N = R2m Z= ---------- * * ...... * H -- N Z V 0 C -- Definition N = Rm Can not be used in this LSI. * ...... * H = Dm-4 + Rm-4 N = Rm V = Dm * Rm Z= * * ...... * C = Dm + Rm NOP NOT OR ORC POP PUSH ROTL -- -- -- 0 0 0 -- -- ---------- -- -- 0 0 -- -- N = Rm N = Rm Z= Z= * * * ...... * * ...... * Stores the corresponding bits of the result. No flags change when the operand is EXR. N = Rm N = Rm Z= Z= N = Rm Z= * * ...... * * ...... * * ...... * C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) ROTR -- 0 N = Rm C = D0 (1-bit shift) or C = D1 (2-bit shift) Z= * * ...... * Rev. 6.00 Feb 22, 2005 page 1159 of 1484 REJ09B0103-0600 0R 0R 1-mR mR * 0R 1-mR mR * 0R 0R 0R 0R 0R 0R 1-m2R m2R 1-mR mR 1-mR mR 1-mR mR 1-mR mR Z= * 1-mR mR 1-mR mR Appendix A Instruction Set Instruction ROTXL H -- N Z V 0 C Definition N = Rm C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) ROTXR -- 0 N = Rm C = D0 (1-bit shift) or C = D1 (2-bit shift) RTE RTS SHAL ---------- -- N = Rm V = Dm * Dm-1 + Z= * * ...... * Stores the corresponding bits of the result. Z= * * ...... * * ...... * V = Dm * Dm-1 * Dm-2 * SHAR -- 0 N = Rm C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) Z= SHLL -- 0 * * ...... * C = D0 (1-bit shift) or C = D1 (2-bit shift) N = Rm C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) SHLR --0 0 N = Rm C = D0 (1-bit shift) or C = D1 (2-bit shift) SLEEP STC STM STMAC ---------- ---------- ---------- -- -- N = 1 if MAC instruction resulted in negative value in MAC register Z = 1 if MAC instruction resulted in zero value in MAC register V = 1 if MAC instruction resulted in overflow Z= * * ...... * Z= * * ...... * Rev. 6.00 Feb 22, 2005 page 1160 of 1484 REJ09B0103-0600 2-mD 1-mD mD 1-mD mD 0R 1-mR mR * 0R 0R 0R 0R 0R 1-mR mR 1-mR mR 1-mR mR 1-mR mR 1-mR mR Z= * (1-bit shift) * * (2-bit shift) Appendix A Instruction Set Instruction SUB H N Z V C Definition N = Rm Z= V= SUBS SUBX ---------- * C = Sm * + * Rm + Sm * Rm * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Z' * V= TAS TRAPA XOR XORC -- 0 -- C = Sm * N = Dm Z= ---------- -- 0 -- Z= * + * Rm + Sm * Rm N = Rm Stores the corresponding bits of the result. No flags change when the operand is EXR. Rev. 6.00 Feb 22, 2005 page 1161 of 1484 REJ09B0103-0600 0R 1-mR mR * * ...... * 0D * ...... * mD * Dm * 0R mD mD mR mS mR * ...... * 4-mD 4-mD H = Sm-4 * + + Sm * mD * Dm * 4-mD 4-mD + Sm * H = Sm-4 * + * Rm-4 + Sm-4 * Rm-4 0R * ...... * mD mD mR mS 1-mR mR 1-mD mD * Rm * Rm Appendix B Internal I/O Register Appendix B Internal I/O Register B.1 Address Address Register Name Bit 7 SM1 CHNE Bit 6 SM0 DISEL Bit 5 DM1 -- Bit 4 DM0 -- Bit 3 MD1 -- Bit 2 MD0 -- Bit 1 DTS -- Bit 0 Sz -- Module Name DTC* 7 Data Bus Width 8/16/32 H'EBC0 to MRA H'EFBF MRB SAR DAR CRA CRB H'F800 H'F801 H'F802 H'F803 H'F804 H'F805 H'F806 H'F807 H'F808 H'F809 H'F80A H'F80B H'F80C H'F80D H'F80E H'F80F H'F810 H'F811 H'F812 H'F813 H'F814 H'F815 H'F816 H'F817 H'F818 H'F819 MCR0 GSR0 BCR0 MCR7 -- BCR7 BCR15 -- -- BCR6 BCR14 MBCR6 MBCR14 TXPR6 TXPR14 TXCR6 TXCR14 TXACK6 TXACK14 ABACK6 ABACK14 RXPR6 RXPR14 RFPR6 RFPR14 IRR6 -- MBIMR6 MBIMR14 IMR6 -- MCR5 -- BCR5 BCR13 MBCR5 MBCR13 TXPR5 TXPR13 TXCR5 TXCR13 TXACK5 TXACK13 ABACK5 ABACK13 RXPR5 RXPR13 RFPR5 RFPR13 IRR5 -- MBIMR5 MBIMR13 IMR5 -- -- -- BCR4 BCR12 MBCR4 MBCR12 TXPR4 TXPR12 TXCR4 TXCR12 TXACK4 TXACK12 ABACK4 ABACK12 RXPR4 RXPR12 RFPR4 RFPR12 IRR4 IRR12 MBIMR4 MBIMR12 IMR4 IMR12 -- GSR3 BCR3 BCR11 MBCR3 MBCR11 TXPR3 TXPR11 TXCR3 TXCR11 TXACK3 TXACK11 ABACK3 ABACK11 RXPR3 RXPR11 RFPR3 RFPR11 IRR3 -- MBIMR3 MBIMR11 IMR3 -- MCR2 GSR2 BCR2 BCR10 MBCR2 MBCR10 TXPR2 TXPR10 TXCR2 TXCR10 TXACK2 TXACK10 ABACK2 ABACK10 RXPR2 RXPR10 RFPR2 RFPR10 IRR2 -- MBIMR2 MBIMR10 IMR2 -- MCR1 GSR1 BCR1 BCR9 MBCR1 MBCR9 TXPR1 TXPR9 TXCR1 TXCR9 TXACK1 TXACK9 ABACK1 ABACK9 RXPR1 RXPR9 RFPR1 RFPR9 IRR1 IRR9 MBIMR1 MBIMR9 IMR1 IMR9 MCR0 GSR0 BCR0 BCR8 -- MBCR8 -- TXPR8 -- TXCR8 -- TXACK8 -- ABACK8 RXPR0 RXPR8 RFPR0 RFPR8 IRR0 IRR8 MBIMR0 MBIMR8 -- IMR8 HCAN0 8/16 MBCR MBCR7 MBCR15 TXPR TXPR7 TXPR15 TXCR TXCR7 TXCR15 TXACK TXACK7 TXACK15 ABACK ABACK7 ABACK15 RXPR RXPR7 RXPR15 RFPR RFPR7 RFPR15 HCAN0 8/16 IRR IRR7 -- MBIMR MBIMR7 MBIMR15 IMR IMR7 -- REC TEC Rev. 6.00 Feb 22, 2005 page 1162 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Address H'F81A H'F81B H'F81C H'F81D H'F81E H'F81F H'F820 H'F821 H'F822 H'F823 H'F824 H'F825 H'F826 H'F827 H'F828 H'F829 H'F82A H'F82B H'F82C H'F82D H'F82E H'F82F H'F830 H'F831 H'F832 H'F833 H'F834 H'F835 H'F836 H'F837 H'F838 H'F839 H'F83A H'F83B H'F83C H'F83D H'F83E H'F83F MC0[1] MC0[2] MC0[3] MC0[4] MC0[5] MC0[6] MC0[7] MC0[8] MC1[1] MC1[2] MC1[3] MC1[4] MC1[5] MC1[6] MC1[7] MC1[8] MC2[1] MC2[2] MC2[3] MC2[4] MC2[5] MC2[6] MC2[7] MC2[8] MC3[1] MC3[2] MC3[3] MC3[4] MC3[5] MC3[6] MC3[7] MC3[8] LAFMH LAFML Register Name UMSR Bit 7 UMSR7 UMSR15 LAFML7 LAFML15 LAFMH7 LAFMH15 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 Bit 6 UMSR6 UMSR14 LAFML6 LAFML14 LAFMH6 LAFMH14 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 Bit 5 UMSR5 UMSR13 LAFML5 LAFML13 LAFMH5 LAFMH13 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 Bit 4 UMSR4 UMSR12 LAFML4 LAFML12 -- LAFMH12 -- -- -- -- RTR STD_ID7 EXD_ID4 Bit 3 UMSR3 UMSR11 LAFML3 LAFML11 -- LAFMH11 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 Bit 2 UMSR2 UMSR10 LAFML2 LAFML10 -- LAFMH10 DLC2 -- -- -- -- STD_ID5 EXD_ID2 Bit 1 UMSR1 UMSR9 LAFML1 LAFML9 LAFMH1 LAFMH9 DLC1 -- -- -- Bit 0 UMSR0 UMSR8 LAFML0 LAFML8 LAFMH0 LAFMH8 DLC0 -- -- -- HCAN0 8/16 Module Name HCAN0 Data Bus Width 8/16 EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- HCAN0 8/16 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- HCAN0 8/16 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 Rev. 6.00 Feb 22, 2005 page 1163 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Address H'F840 H'F841 H'F842 H'F843 H'F844 H'F845 H'F846 H'F847 H'F848 H'F849 H'F84A H'F84B H'F84C H'F84D H'F84E H'F84F H'F850 H'F851 H'F852 H'F853 H'F854 H'F855 H'F856 H'F857 H'F858 H'F859 H'F85A H'F85B H'F85C H'F85D H'F85E H'F85F H'F860 H'F861 H'F862 H'F863 H'F864 H'F865 H'F866 H'F867 Register Name MC4[1] MC4[2] MC4[3] MC4[4] MC4[5] MC4[6] MC4[7] MC4[8] MC5[1] MC5[2] MC5[3] MC5[4] MC5[5] MC5[6] MC5[7] MC5[8] MC6[1] MC6[2] MC6[3] MC6[4] MC6[5] MC6[6] MC6[7] MC6[8] MC7[1] MC7[2] MC7[3] MC7[4] MC7[5] MC7[6] MC7[7] MC7[8] MC8[1] MC8[2] MC8[3] MC8[4] MC8[5] MC8[6] MC8[7] MC8[8] Bit 7 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 Bit 6 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 Bit 5 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 Bit 4 -- -- -- -- RTR STD_ID7 EXD_ID4 Bit 3 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 Bit 2 DLC2 -- -- -- -- STD_ID5 EXD_ID2 Bit 1 DLC1 -- -- -- Bit 0 DLC0 -- -- -- Module Name HCAN0 Data Bus Width 8/16 EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- HCAN0 8/16 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- HCAN0 8/16 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- HCAN0 8/16 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 Rev. 6.00 Feb 22, 2005 page 1164 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Address H'F868 H'F869 H'F86A H'F86B H'F86C H'F86D H'F86E H'F86F H'F870 H'F871 H'F872 H'F873 H'F874 H'F875 H'F876 H'F877 H'F878 H'F879 H'F87A H'F87B H'F87C H'F87D H'F87E H'F87F H'F880 H'F881 H'F882 H'F883 H'F884 H'F885 H'F886 H'F887 H'F888 H'F889 H'F88A H'F88B H'F88C H'F88D H'F88E H'F88F Register Name MC9[1] MC9[2] MC9[3] MC9[4] MC9[5] MC9[6] MC9[7] MC9[8] MC10[1] MC10[2] MC10[3] MC10[4] MC10[5] MC10[6] MC10[7] MC10[8] MC11[1] MC11[2] MC11[3] MC11[4] MC11[5] MC11[6] MC11[7] MC11[8] MC12[1] MC12[2] MC12[3] MC12[4] MC12[5] MC12[6] MC12[7] MC12[8] MC13[1] MC13[2] MC13[3] MC13[4] MC13[5] MC13[6] MC13[7] MC13[8] Bit 7 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 Bit 6 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 Bit 5 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 Bit 4 -- -- -- -- RTR STD_ID7 EXD_ID4 Bit 3 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 Bit 2 DLC2 -- -- -- -- STD_ID5 EXD_ID2 Bit 1 DLC1 -- -- -- Bit 0 DLC0 -- -- -- Module Name HCAN0 Data Bus Width 8/16 EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- HCAN0 8/16 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- HCAN0 8/16 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- HCAN0 8/16 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 Rev. 6.00 Feb 22, 2005 page 1165 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Address H'F890 H'F891 H'F892 H'F893 H'F894 H'F895 H'F896 H'F897 H'F898 H'F899 H'F89A H'F89B H'F89C H'F89D H'F89E H'F89F H'F8B0 H'F8B1 H'F8B2 H'F8B3 H'F8B4 H'F8B5 H'F8B6 H'F8B7 H'F8B8 H'F8B9 H'F8BA H'F8BB H'F8BC H'F8BD H'F8BE H'F8BF H'F8C0 H'F8C1 H'F8C2 H'F8C3 H'F8C4 H'F8C5 H'F8C6 H'F8C7 Register Name MC14[1] MC14[2] MC14[3] MC14[4] MC14[5] MC14[6] MC14[7] MC14[8] MC15[1] MC15[2] MC15[3] MC15[4] MC15[5] MC15[6] MC15[7] MC15[8] MD01 MD02 MD03 MD04 MD05 MD06 MD07 MD08 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 HCAN0 8/16 HCAN0 8/16 Bit 7 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 Bit 6 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 Bit 5 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 Bit 4 -- -- -- -- RTR STD_ID7 EXD_ID4 Bit 3 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 Bit 2 DLC2 -- -- -- -- STD_ID5 EXD_ID2 Bit 1 DLC1 -- -- -- Bit 0 DLC0 -- -- -- Module Name HCAN0 Data Bus Width 8/16 EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 HCAN0 8/16 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 Rev. 6.00 Feb 22, 2005 page 1166 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Address H'F8C8 H'F8C9 H'F8CA H'F8CB H'F8CC H'F8CD H'F8CE H'F8CF H'F8D0 H'F8D1 H'F8D2 H'F8D3 H'F8D4 H'F8D5 H'F8D6 H'F8D7 H'F8D8 H'F8D9 H'F8DA H'F8DB H'F8DC H'F8DD H'F8DE H'F8DF H'F8E0 H'F8E1 H'F8E2 H'F8E3 H'F8E4 H'F8E5 H'F8E6 H'F8E7 H'F8E8 H'F8E9 H'F8EA H'F8EB H'F8EC H'F8ED H'F8EE H'F8EF Register Name MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD61 MD62 MD63 MD64 MD65 MD66 MD67 MD68 MD71 MD72 MD73 MD74 MD75 MD76 MD77 MD78 HCAN0 8/16 HCAN0 8/16 HCAN0 8/16 HCAN0 8/16 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name HCAN0 Data Bus Width 8/16 Rev. 6.00 Feb 22, 2005 page 1167 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Address H'F8F0 H'F8F1 H'F8F2 H'F8F3 H'F8F4 H'F8F5 H'F8F6 H'F8F7 H'F8F8 H'F8F9 H'F8FA H'F8FB H'F8FC H'F8FD H'F8FE H'F8FF H'F900 H'F901 H'F902 H'F903 H'F904 H'F905 H'F906 H'F907 H'F908 H'F909 H'F90A H'F90B H'F90C H'F90D H'F90E H'F90F H'F910 H'F911 H'F912 H'F913 H'F914 H'F915 H'F916 H'F917 Register Name MD81 MD82 MD83 MD84 MD85 MD86 MD87 MD88 MD91 MD92 MD93 MD94 MD95 MD96 MD97 MD98 MD101 MD102 MD103 MD104 MD105 MD106 MD107 MD108 MD111 MD112 MD113 MD114 MD115 MD116 MD117 MD118 MD121 MD122 MD123 MD124 MD125 MD126 MD127 MD128 HCAN0 8/16 HCAN0 8/16 HCAN0 8/16 HCAN0 8/16 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name HCAN0 Data Bus Width 8/16 Rev. 6.00 Feb 22, 2005 page 1168 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Address H'F918 H'F919 H'F91A H'F91B H'F91C H'F91D H'F91E H'F91F H'F920 H'F921 H'F922 H'F923 H'F924 H'F925 H'F926 H'F927 H'F928 H'F929 H'F92A H'F92B H'F92C H'F92D H'F92E H'F92F H'FA00 H'FA01 H'FA02 H'FA03 H'FA04 H'FA05 H'FA06 H'FA07 H'FA08 H'FA09 H'FA0A H'FA0B H'FA0C H'FA0D H'FA0E H'FA0F RXPR ABACK TXACK TXCR TXPR MBCR Register Name MD131 MD132 MD133 MD134 MD135 MD136 MD137 MD138 MD141 MD142 MD143 MD144 MD145 MD146 MD147 MD148 MD151 MD152 MD153 MD154 MD155 MD156 MD157 MD158 MCR GSR BCR MCR7 -- BCR7 BCR15 MBCR7 MBCR15 TXPR7 TXPR15 TXCR7 TXCR15 TXACK7 TXACK15 ABACK7 ABACK15 RXPR7 RXPR15 -- -- BCR6 BCR14 MBCR6 MBCR14 TXPR6 TXPR14 TXCR6 TXCR14 TXACK6 TXACK14 ABACK6 ABACK14 RXPR6 RXPR14 MCR5 -- BCR5 BCR13 MBCR5 MBCR13 TXPR5 TXPR13 TXCR5 TXCR13 TXACK5 TXACK13 ABACK5 ABACK13 RXPR5 RXPR13 -- -- BCR4 BCR12 MBCR4 MBCR12 TXPR4 TXPR12 TXCR4 TXCR12 TXACK4 TXACK12 ABACK4 ABACK12 RXPR4 RXPR12 -- GSR3 BCR3 BCR11 MBCR3 MBCR11 TXPR3 TXPR11 TXCR3 TXCR11 TXACK3 TXACK11 ABACK3 ABACK11 RXPR3 RXPR11 MCR2 GSR2 BCR2 BCR10 MBCR2 MBCR10 TXPR2 TXPR10 TXCR2 TXCR10 TXACK2 TXACK10 ABACK2 ABACK10 RXPR2 RXPR10 MCR1 GSR1 BCR1 BCR9 MBCR1 MBCR9 TXPR1 TXPR9 TXCR1 TXCR9 TXACK1 TXACK9 ABACK1 ABACK9 RXPR1 RXPR9 MCR0 GSR0 BCR0 BCR8 -- MBCR8 -- TXPR8 -- TXCR8 -- TXACK8 -- ABACK8 RXPR0 RXPR8 HCAN1* 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name HCAN0 Data Bus Width 8/16 HCAN0 8/16 8/16 Rev. 6.00 Feb 22, 2005 page 1169 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Register Address H'FA10 H'FA11 H'FA12 H'FA13 H'FA14 H'FA15 H'FA16 H'FA17 H'FA18 H'FA19 H'FA1A H'FA1B H'FA1C H'FA1D H'FA1E H'FA1F H'FA20 H'FA21 H'FA22 H'FA23 H'FA24 H'FA25 H'FA26 H'FA27 H'FA28 H'FA29 H'FA2A H'FA2B H'FA2C H'FA2D H'FA2E H'FA2F H'FA30 H'FA31 H'FA32 H'FA33 H'FA34 H'FA35 H'FA36 H'FA37 H'FA38 H'FA39 MC0[1] MC0[2] MC0[3] MC0[4] MC0[5] MC0[6] MC0[7] MC0[8] MC1[1] MC1[2] MC1[3] MC1[4] MC1[5] MC1[6] MC1[7] MC1[8] MC2[1] MC2[2] MC2[3] MC2[4] MC2[5] MC2[6] MC2[7] MC2[8] MC3[1] MC3[2] LAFMH LAFML REC TEC UMSR UMSR7 UMSR15 LAFML7 LAFML15 LAFMH7 LAFMH15 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 UMSR6 UMSR14 LAFML6 LAFML14 LAFMH6 LAFMH14 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 UMSR5 UMSR13 LAFML5 LAFML13 LAFMH5 LAFMH13 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 UMSR4 UMSR12 LAFML4 LAFML12 -- LAFMH12 -- -- -- -- RTR STD_ID7 EXD_ID4 UMSR3 UMSR11 LAFML3 LAFML11 -- LAFMH11 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 UMSR2 UMSR10 LAFML2 LAFML10 -- LAFMH10 DLC2 -- -- -- -- STD_ID5 EXD_ID2 UMSR1 UMSR9 LAFML1 LAFML9 LAFMH1 LAFMH9 DLC1 -- -- -- UMSR0 UMSR8 LAFML0 LAFML8 LAFMH0 LAFMH8 DLC0 -- -- -- HCAN1* 7 Module Bit 7 RFPR7 RFPR15 Bit 6 RFPR6 RFPR14 IRR6 -- MBIMR6 MBIMR14 IMR6 -- Bit 5 RFPR5 RFPR13 IRR5 -- MBIMR5 MBIMR13 IMR5 -- Bit 4 RFPR4 RFPR12 IRR4 IRR12 MBIMR4 MBIMR12 IMR4 IMR12 Bit 3 RFPR3 RFPR11 IRR3 -- MBIMR3 MBIMR11 IMR3 -- Bit 2 RFPR2 RFPR10 IRR2 -- MBIMR2 MBIMR10 IMR2 -- Bit 1 RFPR1 RFPR9 IRR1 IRR9 MBIMR1 MBIMR9 IMR1 IMR9 Bit 0 RFPR0 RFPR8 IRR0 IRR8 MBIMR0 MBIMR8 IMR0 IMR8 Name 7 HCAN1* Data Bus Width 8/16 Name RFPR IRR IRR7 -- MBIMR MBIMR7 MBIMR15 IMR IMR7 -- 8/16 EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- HCAN1* 7 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- 8/16 EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- -- -- -- -- DLC3 -- DLC2 -- DLC1 -- Rev. 6.00 Feb 22, 2005 page 1170 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Register Address H'FA3A H'FA3B H'FA3C H'FA3D H'FA3E H'FA3F H'FA40 H'FA41 H'FA42 H'FA43 H'FA44 H'FA45 H'FA46 H'FA47 H'FA48 H'FA49 H'FA4A H'FA4B H'FA4C H'FA4D H'FA4E H'FA4F H'FA50 H'FA51 H'FA52 H'FA53 H'FA54 H'FA55 H'FA56 H'FA57 H'FA58 H'FA59 H'FA5A H'FA5B H'FA5C H'FA5D H'FA5E H'FA5F Name MC3[3] MC3[4] MC3[5] MC3[6] MC3[7] MC3[8] MC4[1] MC4[2] MC4[3] MC4[4] MC4[5] MC4[6] MC4[7] MC4[8] MC5[1] MC5[2] MC5[3] MC5[4] MC5[5] MC5[6] MC5[7] MC5[8] MC6[1] MC6[2] MC6[3] MC6[4] MC6[5] MC6[6] MC6[7] MC6[8] MC7[1] MC7[2] MC7[3] MC7[4] MC7[5] MC7[6] MC7[7] MC7[8] Bit 7 -- -- STD_ID2 STD_ID10 EXD_ID7 Bit 6 -- -- STD_ID1 STD_ID9 EXD_ID6 Bit 5 -- -- STD_ID0 STD_ID8 EXD_ID5 Bit 4 -- -- RTR STD_ID7 EXD_ID4 Bit 3 -- -- IDE STD_ID6 EXD_ID3 Bit 2 -- -- -- STD_ID5 EXD_ID2 Bit 1 -- -- Bit 0 -- -- Module Name 7 HCAN1* Data Bus Width 8/16 EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- HCAN1* 7 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- 8/16 EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- HCAN1* 7 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- 8/16 EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 Rev. 6.00 Feb 22, 2005 page 1171 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Register Address H'FA60 H'FA61 H'FA62 H'FA63 H'FA64 H'FA65 H'FA66 H'FA67 H'FA68 H'FA69 H'FA6A H'FA6B H'FA6C H'FA6D H'FA6E H'FA6F H'FA70 H'FA71 H'FA72 H'FA73 H'FA74 H'FA75 H'FA76 H'FA77 H'FA78 H'FA79 H'FA7A H'FA7B H'FA7C H'FA7D H'FA7E H'FA7F H'FA80 H'FA81 H'FA82 H'FA83 H'FA84 H'FA85 H'FA86 H'FA87 H'FA88 H'FA89 Name MC8[1] MC8[2] MC8[3] MC8[4] MC8[5] MC8[6] MC8[7] MC8[8] MC9[1] MC9[2] MC9[3] MC9[4] MC9[5] MC9[6] MC9[7] MC9[8] MC10[1] MC10[2] MC10[3] MC10[4] MC10[5] MC10[6] MC10[7] MC10[8] MC11[1] MC11[2] MC11[3] MC11[4] MC11[5] MC11[6] MC11[7] MC11[8] MC12[1] MC12[2] MC12[3] MC12[4] MC12[5] MC12[6] MC12[7] MC12[8] MC13[1] MC13[2] Bit 7 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 Bit 6 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 Bit 5 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 Bit 4 -- -- -- -- RTR STD_ID7 EXD_ID4 Bit 3 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 Bit 2 DLC2 -- -- -- -- STD_ID5 EXD_ID2 Bit 1 DLC1 -- -- -- Bit 0 DLC0 -- -- -- Module Name 7 HCAN1* Data Bus Width 8/16 EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- HCAN1* 7 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- 8/16 EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- HCAN1* 7 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- 8/16 EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- -- -- -- -- DLC3 -- DLC2 -- DLC1 -- Rev. 6.00 Feb 22, 2005 page 1172 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Register Address H'FA8A H'FA8B H'FA8C H'FA8D H'FA8E H'FA8F H'FA90 H'FA91 H'FA92 H'FA93 H'FA94 H'FA95 H'FA96 H'FA97 H'FA98 H'FA99 H'FA9A H'FA9B H'FA9C H'FA9D H'FA9E H'FA9F H'FAB0 H'FAB1 H'FAB2 H'FAB3 H'FAB4 H'FAB5 H'FAB6 H'FAB7 H'FAB8 H'FAB9 H'FABA H'FABB H'FABC H'FABD H'FABE H'FABF Name MC13[3] MC13[4] MC13[5] MC13[6] MC13[7] MC13[8] MC14[1] MC14[2] MC14[3] MC14[4] MC14[5] MC14[6] MC14[7] MC14[8] MC15[1] MC15[2] MC15[3] MC15[4] MC15[5] MC15[6] MC15[7] MC15[8] MD01 MD02 MD03 MD04 MD05 MD06 MD07 MD08 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 Bit 7 -- -- STD_ID2 STD_ID10 EXD_ID7 Bit 6 -- -- STD_ID1 STD_ID9 EXD_ID6 Bit 5 -- -- STD_ID0 STD_ID8 EXD_ID5 Bit 4 -- -- RTR STD_ID7 EXD_ID4 Bit 3 -- -- IDE STD_ID6 EXD_ID3 Bit 2 -- -- -- STD_ID5 EXD_ID2 Bit 1 -- -- Bit 0 -- -- Module Name 7 HCAN1* Data Bus Width 8/16 EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- HCAN1* 7 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- 8/16 EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 STD_ID10 EXD_ID7 -- -- -- -- STD_ID1 STD_ID9 EXD_ID6 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 HCAN1* 7 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 8/16 Rev. 6.00 Feb 22, 2005 page 1173 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Register Address H'FAC0 H'FAC1 H'FAC2 H'FAC3 H'FAC4 H'FAC5 H'FAC6 H'FAC7 H'FAC8 H'FAC9 H'FACA H'FACB H'FACC H'FACD H'FACE H'FACF H'FAD0 H'FAD1 H'FAD2 H'FAD3 H'FAD4 H'FAD5 H'FAD6 H'FAD7 H'FAD8 H'FAD9 H'FADA H'FADB H'FADC H'FADD H'FADE H'FADF H'FAE0 H'FAE1 H'FAE2 H'FAE3 H'FAE4 H'FAE5 H'FAE6 H'FAE7 H'FAE8 H'FAE9 Name MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD61 MD62 MD63 MD64 MD65 MD66 MD67 MD68 MD71 MD72 HCAN1* 7 Module Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name 7 HCAN1* Data Bus Width 8/16 HCAN1* 7 8/16 8/16 Rev. 6.00 Feb 22, 2005 page 1174 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Register Address H'FAEA H'FAEB H'FAEC H'FAED H'FAEE H'FAEF H'FAF0 H'FAF1 H'FAF2 H'FAF3 H'FAF4 H'FAF5 H'FAF6 H'FAF7 H'FAF8 H'FAF9 H'FAFA H'FAFB H'FAFC H'FAFD H'FAFE H'FAFF H'FB00 H'FB01 H'FB02 H'FB03 H'FB04 H'FB05 H'FB06 H'FB07 H'FB08 H'FB09 H'FB0A H'FB0B H'FB0C H'FB0D H'FB0E H'FB0F Name MD73 MD74 MD75 MD76 MD77 MD78 MD81 MD82 MD83 MD84 MD85 MD86 MD87 MD88 MD91 MD92 MD93 MD94 MD95 MD96 MD97 MD98 MD101 MD102 MD103 MD104 MD105 MD106 MD107 MD108 MD111 MD112 MD113 MD114 MD115 MD116 MD117 MD118 HCAN1* 7 Module Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name 7 HCAN1* Data Bus Width 8/16 HCAN1* 7 8/16 8/16 Rev. 6.00 Feb 22, 2005 page 1175 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Register Address H'FB10 H'FB11 H'FB12 H'FB13 H'FB14 H'FB15 H'FB16 H'FB17 H'FB18 H'FB19 H'FB1A H'FB1B H'FB1C H'FB1D H'FB1E H'FB1F H'FB20 H'FB21 H'FB22 H'FB23 H'FB24 H'FB25 H'FB26 H'FB27 H'FB28 H'FB29 H'FB2A H'FB2B H'FB2C H'FB2D H'FB2E H'FB2F Name MD121 MD122 MD123 MD124 MD125 MD126 MD127 MD128 MD131 MD132 MD133 MD134 MD135 MD136 MD137 MD138 MD141 MD142 MD143 MD144 MD145 MD146 MD147 MD148 MD151 MD152 MD153 MD154 MD155 MD156 MD157 MD158 HCAN1* 7 Module Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name 7 HCAN1* Data Bus Width 8/16 8/16 Rev. 6.00 Feb 22, 2005 page 1176 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Register Address H'FC00 H'FC02 H'FC04 H'FC06 Name PWCR1 PWOCR1 PWPR1 PWCYR1 Bit 7 -- OE1H OPS1H -- Bit 6 -- OE1G OPS1G -- Bit 5 IE OE1F OPS1F -- Bit 4 CMF OE1E OPS1E -- Bit 3 CST OE1D OPS1D -- Bit 2 CKS2 OE1C OPS1C -- Bit 1 CKS1 OE1B OPS1B Bit 0 CKS0 OE1A OPS1A Module Name Data Bus Width Motor 16 control PWM timer 1 H'FC08 PWBFR1A -- DT7 -- DT6 -- DT6 -- DT6 -- DT6 -- OE2G OPS2G -- -- DT5 -- DT5 -- DT5 -- DT5 IE OE2F OPS2F -- OTS DT4 OTS DT4 OTS DT4 OTS DT4 CMF OE2E OPS2E -- -- DT3 -- DT3 -- DT3 -- DT3 CST OE2D OPS2D -- -- DT2 -- DT2 -- DT2 -- DT2 CKS2 OE2C OPS2C -- DT9 DT1 DT9 DT1 DT9 DT1 DT9 DT1 CKS1 OE2B OPS2B DT8 DT0 DT8 DT0 DT8 DT0 DT8 DT0 CKS0 OE2A OPS2A Motor 16 control PWM timer 2 H'FC0A PWBFR1C -- DT7 H'FC0C PWBFR1E -- DT7 H'FC0E PWBFR1G -- DT7 H'FC10 H'FC12 H'FC14 H'FC16 PWCR2 PWOCR2 PWPR2 PWCYR2 -- OE2H OPS2H -- H'FC18 PWBFR2A -- DT7 -- DT6 -- DT6 -- DT6 -- DT6 PH6DDR PJ6DDR PH6DR PJ6DR PH6 PJ6 -- DT5 -- DT5 -- DT5 -- DT5 PH5DDR PJ5DDR PH5DR PJ5DR PH5 PJ5 TDS DT4 TDS DT4 TDS DT4 TDS DT4 PH4DDR PJ4DDR PH4DR PJ4DR PH4 PJ4 -- DT3 -- DT3 -- DT3 -- DT3 PH3DDR PJ3DDR PH3DR PJ3DR PH3 PJ3 -- DT2 -- DT2 -- DT2 -- DT2 PH2DDR PJ2DDR PH2DR PJ2DR PH2 PJ2 DT9 DT1 DT9 DT1 DT9 DT1 DT9 DT1 PH1DDR PJ1DDR PH1DR PJ1DR PH1 PJ1 DT8 DT0 DT8 DT0 DT8 DT0 DT8 DT0 PH0DDR PJ0DDR PH0DR PJ0DR PH0 PJ0 PORT 16 H'FC1A PWBFR2B -- DT7 H'FC1C PWBFR2C -- DT7 H'FC1E PWBFR2D -- DT7 H'FC20 H'FC21 H'FC24 H'FC25 H'FC28 H'FC29 PHDDR PJDDR PHDR PJDR PORTH PORTJ PH7DDR PJ7DDR PH7DR PJ7DR PH7 PJ7 Rev. 6.00 Feb 22, 2005 page 1177 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Register Address H'FC60 H'FDB4 H'FDB5 H'FDE4 H'FDE5 H'FDE6 H'FDE7 H'FDE8 H'FDE9 H'FDEA H'FDEB H'FDEC H'FE00 H'FE01 H'FE02 H'FE03 H'FE04 H'FE05 H'FE06 H'FE07 H'FE08 H'FE09 H'FE12 H'FE13 H'FE14 H'FE15 H'FE16 H'FE17 H'FE18 H'FE19 H'FE1A H'FE1B H'FE1C H'FE1F H'FE26 H'FE27 H'FE28 H'FE29 H'FE2A H'FE2B H'FE2C H'FE2D BCRA BCRB ISCRH ISCRL IER ISR DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF DTCERG DTVECR PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL BARB Name Bit 7 Bit 6 -- IICX1 SW STS2 -- -- -- MSTPA6 MSTPB6 MSTPC6 -- 3 Module Bit 5 -- IICX0 IE STS1 INTM1 -- -- MSTPA5 MSTPB5 MSTPC5 -- 3 Data Bus Width 8 8 Bit 4 -- IICE IF STS0 INTM0 -- -- MSTPA4 MSTPB4 MSTPC4 -- 3 Bit 3 -- -- CLR3 OPE NMIEG STCS -- MSTPA3 MSTPB3 MSTPC3 AE3 3 Bit 2 -- -- CLR2 -- -- SCK2 MDS2 MSTPA2 MSTPB2 MSTPC2 AE2 3 Bit 1 -- -- CLR1 -- -- SCK1 MDS1 MSTPA1 MSTPB1 MSTPC1 AE1 STC1 -- BAA17 BAA9 BAA1 -- BAA17 BAA9 BAA1 CSELA0 CSELA0 IRQ4SCB IRQ0SCB IRQ1E IRQ1F DTCEA1 DTCEB1 DTCEC1 DTCED1 DTCEE1 DTCEF1 DTCEG1 DTVEC1 G0CMS1 G1NOV NDER9 NDER1 POD9 POD1 NDR9 NDR1 Bit 0 -- -- CLR0 -- RAME SCK0 MDS1 MSTPA0 MSTPB0 MSTPC0 AE0 STC0 -- BAA16 BAA8 BAA0 -- BAA16 BAA8 BAA0 BIEA BIEA IRQ4SCA IRQ0SCA IRQ0E IRQ0F DTCEA0 DTCEB0 DTCEC0 DTCED0 DTCEE0 DTCEF0 DTCEG0 DTVEC0 G0CMS0 G0NOV NDER8 NDER0 POD8 POD0 NDR8 NDR0 Name SYSTEM IIC * 4 MSTPCRD MSTPD7 4 SCKX* 4 -- DDCSWR* SWE SBYCR SYSCR SCKCR MDCR SSBY MACS PSTOP -- SYSTEM 8 MSTPCRA MSTPA7 MSTPCRB MSTPB7 MSTPCRC MSTPC7 PFCR LPWRCR BARA -- DTON* -- BAA23 BAA15 BAA7 -- BAA23 BAA15 BAA7 CMFA CMFA -- IRQ3SCB -- -- DTCEA7 DTCEB7 DTCEC7 DTCED7 DTCEE7 DTCEF7 DTCEG7 SWDTE G3CMS1 G3INV NDER15 NDER7 POD15 POD7 NDR15 NDR7 LSON * -- BAA22 BAA14 BAA6 -- BAA22 BAA14 BAA6 CDA CDA -- NESEL* -- BAA21 BAA13 BAA5 -- BAA21 BAA13 BAA5 SUBSTP* -- BAA20 BAA12 BAA4 -- BAA20 BAA12 BAA4 BAMRA1 BAMRA1 -- IRQ2SCA IRQ4E IRQ4F DTCEA4 DTCEB4 DTCEC4 DTCED4 DTCEE4 DTCEF4 DTCEG4 DTVEC4 G2CMS0 G0INV NDER12 NDER4 POD12 POD4 NDR12 NDR4 RFCUT * -- BAA19 BAA11 BAA3 -- BAA19 BAA11 BAA3 -- -- BAA18 BAA10 BAA2 -- BAA18 BAA10 BAA2 CSELA1 CSELA1 IRQ5SCA IRQ1SCA IRQ2E IRQ2F DTCEA2 DTCEB2 DTCEC2 DTCED2 DTCEE2 DTCEF2 DTCEG2 DTVEC2 G1CMS0 G2NOV NDER10 NDER2 POD10 POD2 NDR10 NDR2 PBC * 7 8 BAMRA2 BAMRA2 -- IRQ2SCB IRQ5E IRQ5F DTCEA5 DTCEB5 DTCEC5 DTCED5 DTCEE5 DTCEF5 DTCEG5 DTVEC5 G2CMS1 G1INV NDER13 NDER5 POD13 POD5 NDR13 NDR5 BAMRA0 BAMRA0 IRQ5SCB IRQ1SCB IRQ3E IRQ3F DTCEA3 DTCEB3 DTCEC3 DTCED3 DTCEE3 DTCEF3 DTCEG3 DTVEC3 G1CMS1 G3NOV NDER11 NDER3 POD11 POD3 NDR11 NDR3 INT 8 IRQ3SCA -- -- DTCEA6 DTCEB6 DTCEC6 DTCED6 DTCEE6 DTCEF6 DTCEG6 DTVEC6 G3CMS0 G2INV NDER14 NDER6 POD14 POD6 NDR14 NDR6 DTC* 7 8 PPG * 7 8 Rev. 6.00 Feb 22, 2005 page 1178 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Register Address H'FE2E H'FE2F H'FE30 H'FE32 H'FE39 H'FE3A H'FE3B H'FE3C H'FE3D H'FE3E H'FE40 H'FE41 H'FE42 H'FE43 H'FE44 H'FE46 H'FE47 H'FE48 H'FE49 H'FE80 H'FE81 H'FE82 H'FE83 H'FE84 H'FE85 H'FE86 H'FE87 H'FE88 H'FE89 H'FE8A H'FE8B H'FE8C H'FE8D H'FE8E H'FE8F H'FE90 H'FE91 H'FE92 H'FE94 H'FE95 TCR4 TMDR4 TIOR4 TIER4 TSR4 -- -- IOB3 TTGE TCFD CCLR1 -- IOB2 -- -- CCLR0 -- IOB1 TCIEU TCFU CKEG1 -- IOB0 TCIEV TCFV CKEG0 MD3 IOA3 -- -- TPSC2 MD2 IOA2 -- -- TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU4 8/16 TGR3D TGR3C TGR3B TGR3A Name NDRH NDRL P1DDR P3DDR PADDR PBDDR PCDDR PDDDR PEDDR PFDDR PAPCR PBPCR PCPCR PDPCR PEPCR P3ODR PAODR PBODR PCODR TCR3 TMDR3 TIOR3H TIOR3L TIER3 TSR3 TCNT3 Bit 7 -- -- P17DDR -- -- PB7DDR PC7DDR PD7DDR PE7DDR PF7DDR -- PB7PCR PC7PCR PD7PCR PE7PCR -- -- PB7ODR PC7ODR CCLR2 -- IOB3 IOD3 TTGE -- Bit 6 -- -- P16DDR -- -- PB6DDR PC6DDR PD6DDR PE6DDR PF6DDR -- PB6PCR PC6PCR PD6PCR PE6PCR -- -- PB6ODR PC6ODR CCLR1 -- IOB2 IOD2 -- -- Bit 5 -- -- P15DDR P35DDR -- PB5DDR PC5DDR PD5DDR PE5DDR PF5DDR -- PB5PCR PC5PCR PD5PCR PE5PCR P35ODR -- PB5ODR PC5ODR CCLR0 BFB IOB1 IOD1 -- -- Bit 4 -- -- P14DDR P34DDR -- PB4DDR PC4DDR PD4DDR PE4DDR PF4DDR -- PB4PCR PC4PCR PD4PCR PE4PCR P34ODR -- PB4ODR PC4ODR CKEG1 BFA IOB0 IOD0 TCIEV TCFV Bit 3 NDR11 NDR3 P13DDR P33DDR PA3DDR PB3DDR PC3DDR PD3DDR PE3DDR PF3DDR PA3PCR PB3PCR PC3PCR PD3PCR PE3PCR P33ODR PA3ODR PB3ODR PC3ODR CKEG0 MD3 IOA3 IOC3 TGIED TGFD Bit 2 NDR10 NDR2 P12DDR P32DDR PA2DDR PB2DDR PC2DDR PD2DDR PE2DDR -- PA2PCR PB2PCR PC2PCR PD2PCR PE2PCR P32ODR PA2ODR PB2ODR PC2ODR TPSC2 MD2 IOA2 IOC2 TGIEC TGFC Bit 1 NDR9 NDR1 P11DDR P31DDR PA1DDR PB1DDR PC1DDR PD1DDR PE1DDR -- PA1PCR PB1PCR PC1PCR PD1PCR PE1PCR P31ODR PA1ODR PB1ODR PC1ODR TPSC1 MD1 IOA1 IOC1 TGIEB TGFB Bit 0 NDR8 NDR0 P10DDR P30DDR PA0DDR PB0DDR PC0DDR PD0DDR PE0DDR PF0DDR PA0PCR PB0PCR PC0PCR PD0PCR PE0PCR P30ODR PA0ODR PB0ODR PC0ODR TPSC0 MD0 IOA0 IOC0 TGIEA TGFA TPU3 8/16 PORT 8 PORT 8 Module Name 7 PPG * Data Bus Width 8 Rev. 6.00 Feb 22, 2005 page 1179 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Register Address H'FE96 H'FE97 H'FE98 H'FE99 H'FE9A H'FE9B H'FEA0 H'FEA1 H'FEA2 H'FEA4 H'FEA5 H'FEA6 H'FEA7 H'FEA8 H'FEA9 H'FEAA H'FEAB H'FEB0 H'FEB1 H'FEC0 H'FEC1 H'FEC2 H'FEC3 H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC9 H'FECA H'FECC H'FECE H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FEDB H'FF00 H'FF02 H'FF09 TSTR TSYR IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRJ IPRK IPRM Reserved ABWCR ASTCR WCRH WCRL BCRH BCRL RAMER P1DR P3DR PADR ABW7 AST7 W71 W31 ICIS1 -- -- P17DR -- -- ABW6 AST6 W70 W30 ICIS0 -- -- P16DR -- -- ABW5 AST5 W61 W21 BRSTRM -- -- P15DR P35DR -- ABW4 AST4 W60 W20 BRSTS1 -- -- P14DR P34DR -- ABW3 AST3 W51 W11 BRSTS0 -- RAMS P13DR P33DR PA3DR ABW2 AST2 W50 W10 -- -- RAM2 P12DR P32DR PA2DR ABW1 AST1 W41 W01 -- WDBE RAM1 P11DR P31DR PA1DR ABW0 AST0 W40 W00 -- -- RAM0 P10DR P30DR PA0DR ROM PORT 8 8 Bus controller 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IPR6 IPR6 -- IPR6 IPR6* IPR6 IPR6 IPR6 -- IPR6 IPR6 7 Module Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name TPU4 Data Bus Width 8/16 Name TCNT4 TGR4A TGR4B TCR5 TMDR5 TIOR5 TIER5 TSR5 TCNT5 -- -- IOB3 TTGE TCFD CCLR1 -- IOB2 -- -- CCLR0 -- IOB1 TCIEU TCFU CKEG1 -- IOB0 TCIEV TCFV CKEG0 MD3 IOA3 -- -- TPSC2 MD2 IOA2 -- -- TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU5 8/16 TGR5A TGR5B CST5 SYNC5 IPR5 IPR5 -- IPR5 IPR5* IPR5 IPR5 IPR5 -- IPR5 IPR5 7 CST4 SYNC4 IPR4 IPR4 -- IPR4 IPR4* IPR4 IPR4 IPR4 -- IPR4 IPR4 7 CST3 SYNC3 -- -- -- -- -- -- -- -- -- -- -- CST2 SYNC2 IPR2 IPR2 IPR2* -- IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 7 CST1 SYNC1 IPR1 IPR1 IPR1* -- IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 7 CST0 SYNC0 IPR0 IPR0 IPR0* -- IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 7 TPU All 8 INT 8 Rev. 6.00 Feb 22, 2005 page 1180 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Register Address H'FF0A H'FF0B H'FF0C H'FF0D H'FF0E H'FF10 H'FF11 H'FF12 H'FF13 H'FF14 H'FF15 H'FF16 H'FF17 H'FF18 H'FF19 H'FF1A H'FF1B H'FF1C H'FF1D H'FF1E H'FF1F H'FF20 H'FF21 H'FF22 H'FF24 H'FF25 H'FF26 H'FF27 H'FF28 H'FF29 H'FF2A H'FF2B H'FF30 H'FF31 H'FF32 H'FF34 H'FF35 H'FF36 H'FF37 H'FF38 H'FF39 H'FF3A H'FF3B TGR2B TGR2A TCR2 TMDR2 TIOR2 TIER2 TSR2 TNCT2 -- -- IOB3 TTGE TCFD CCLR1 -- IOB2 -- -- CCLR0 -- IOB1 TCIEU TCFU CKEG1 -- IOB0 TCIEV TCFV CKEG0 MD3 IOA3 -- -- TPSC2 MD2 IOA2 -- -- TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU2 8/16 TGR1B TGR1A TCR1 TMDR1 TIOR1 TIER1 TSR1 TNCT1 -- -- IOB3 TTGE TCFD CCLR1 -- IOB2 -- -- CCLR0 -- IOB1 TCIEU TCFU CKEG1 -- IOB0 TCIEV TCFV CKEG0 MD3 IOA3 -- -- TPSC2 MD2 IOA2 -- -- TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU1 8/16 TGR0D TGR0C TGR0B TGR0A Name PBDR PCDR PDDR PEDR PFDR TCR0 TMDR0 TIOR0H TIOR0L TIER0 TSR0 TNCT0 Bit 7 PB7DR PC7DR PD7DR PE7DR PF7DR CCLR2 -- IOB3 IOD3 TTGE -- Bit 6 PB6DR PC6DR PD6DR PE6DR PF6DR CCLR1 -- IOB2 IOD2 -- -- Bit 5 PB5DR PC5DR PD5DR PE5DR PF5DR CCLR0 BFB IOB1 IOD1 -- -- Bit 4 PB4DR PC4DR PD4DR PE4DR PF4DR CKEG1 BFA IOB0 IOD0 TCIEV TCFV Bit 3 PB3DR PC3DR PD3DR PE3DR PF3DR CKEG0 MD3 IOA3 IOC3 TGIED TGFD Bit 2 PB2DR PC2DR PD2DR PE2DR -- TPSC2 MD2 IOA2 IOC2 TGIEC TGFC Bit 1 PB1DR PC1DR PD1DR PE1DR -- TPSC1 MD1 IOA1 IOC1 TGIEB TGFB Bit 0 PB0DR PC0DR PD0DR PE0DR PF0DR TPSC0 MD0 IOA0 IOC0 TGIEA TGFA TPU0 8/16 Module Name PORT Data Bus Width 8 Rev. 6.00 Feb 22, 2005 page 1181 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Register Address Name Bit 7 OVF Bit 6 WT/IT Bit 5 TME Bit 4 -- Bit 3 -- Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Module Name WDT0 Data Bus Width 8 TCSR0 H'FF74 (read/write) H'FF75 (read) H'FF76 H'FF77 (read) H'FF78 TCNT0 -- -- -- RSTE CHR BLK IEIC -- -- PE PE MST -- -- O/E O/E TRS -- -- STOP BCP1 ACKE -- -- MP BCP0 BBSY -- -- CKS1 CKS1 IRIC -- -- CKS0 CKS0 SCP SCI0, 8 4 IIC0* , Smart card interface 0 RSTCSR0 WOVF SMR0 SMR0 ICCR0* 4 C/A GM ICE H'FF79 BRR0 ICSR0* 4 ESTP TIE STOP RIE IRTR TE AASX RE AL MPIE AAS TEIE ADZ CKE1 ACKB CKE0 H'FF7A H'FF7B H'FF7C SCR0 TDR0 SSR0 SSR0 TDRE TDRE RDRF RDRF ORER ORER FER ERS PER PER TEND TEND MPB MPB MPBT MPBT H'FF7D H'FF7E RDR0 SCMR0 ICDR0/ 4 SARX0* -- ICDR7/ SVAX6 MLS/ SVA6 C/A GM 4 -- ICDR6/ SVAX5 WAIT/ SVA5 CHR BLK IEIC -- ICDR5/ SVAX4 CKS2/ SVA4 PE PE MST -- ICDR4/ SVAX3 CKS1/ SVA3 O/E O/E TRS SDIR ICDR3/ SVAX2 CKS0/ SVA2 STOP BCP1 ACKE SINV ICDR2/ SVAX1 BC2/ SVA1 MP BCP0 BBSY -- ICDR1/ SVAX0 BC1/ SVA0 CKS1 CKS1 IRIC SMIF ICDR0/FSX BC0/FS CKS0 CKS0 SCP IIC0* 4 H'FF7F H'FF80 ICMR0/ SAR0 SMR1 SMR1 ICCR1* ICE 8 SCI1, 4 IIC1* , Smart card interface 1 H'FF81 BRR1 ICSR1* 4 ESTP TIE STOP RIE IRTR TE AASX RE AL MPIE AAS TEIE ADZ CKE1 ACKB CKE0 H'FF82 H'FF83 H'FF84 SCR1 TDR1 SSR1 SSR1 TDRE TDRE RDRF RDRF ORER ORER FER ERS PER PER TEND TEND MPB MPB MPBT MPBT H'FF85 H'FF86 RDR1 SCMR1 ICDR1/ 4 SARX1* -- ICDR7/ SVARX6 MLS/ SVA6 C/A GM -- ICDR6/ SVARX5 WAIT/ SVA5 CHR BLK -- ICDR5/ SVARX4 CKS2/ SVA4 PE PE -- ICDR4/ SVARX3 CKS1/ SVA3 O/E O/E SDIR ICDR3/ SVARX2 CKS0/ SVA2 STOP BCP1 SINV ICDR2/ SVARX1 BC2/ SVA1 MP BCP0 -- ICDR1/ SVARX0 BC1/ SVA0 CKS1 CKS1 SMIF ICDR0/FSX BC0/FS CKS0 CKS0 IIC1* 4 H'FF87 H'FF88 ICMR1/ 4 SAR1* SMR2 SMR2 SCI2, 8 Smart card interface 2 H'FF89 H'FF8A H'FF8B H'FF8C BRR2 SCR2 TDR2 SSR2 SSR2 TDRE TDRE RDRF RDRF ORER ORER FER ERS PER PER TEND TEND MPB MPB MPBT MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 H'FF8D H'FF8E RDR2 SCMR2 -- -- -- -- SDIR SINV -- SMIF Rev. 6.00 Feb 22, 2005 page 1182 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Register Address H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 Name ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR Bit 7 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 ADF TRGS1 OVF Bit 6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE TRGS0 WT/IT Bit 5 AD7 -- AD7 -- AD7 -- AD7 -- ADST -- TME Bit 4 AD6 -- AD6 -- AD6 -- AD6 -- SCAN -- PSS* 1 Module Bit 3 AD5 -- AD5 -- AD5 -- AD5 -- CH3 CKS1 RST/NMI Bit 2 AD4 -- AD4 -- AD4 -- AD4 -- CH2 CKS0 CKS2 Bit 1 AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- CKS1 Bit 0 AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- CKS0 WDT1 Name A/D Data Bus Width 8 TCSR1 H'FFA2 (read/write) H'FFA3 (read) H'FFA4 H'FFA5 H'FFA6 H'FFA8 H'FFA9 H'FFAA H'FFAB H'FFAC H'FFB0 H'FFB2 H'FFB3 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBC H'FFBD H'FFBE TCNT1 DADR0 DADR1 DACR01 FLMCR1 FLMCR2 EBR1 EBR2 FLPWCR PORT1 PORT3 PORT4 PORT9 PORTA PORTB PORTC PORTD PORTE PORTF 16 D/A0, 1 8 DAOE1 FWE FLER EB7 -- PDWND* P17 -- P47 -- -- PB7 PC7 PD7 PE7 PF7 2 DAOE0 SWE -- EB6 -- -- P16 -- P46 -- -- PB6 PC6 PD6 PE6 PF6 DAE ESU -- EB5 EB13* -- P15 P35 P45 -- -- PB5 PC5 PD5 PE5 PF5 8 -- PSU -- EB4 EB12* -- P14 P34 P44 -- -- PB4 PC4 PD4 PE4 PF4 8 -- EV -- EB3 EB11* -- P13 P33 P43 P93 PA3 PB3 PC3 PD3 PE3 PF3 6 -- PV -- EB2 EB10* -- P12 P32 P42 P92 PA2 PB2 PC2 PD2 PE2 -- 5 -- E -- EB1 EB9 -- P11 P31 P41 P91 PA1 PB1 PC1 PD1 PE1 -- -- P -- EB0 EB8 -- P10 P30 P40 P90 PA0 PB0 PC0 PD0 PE0 PF0 PORT 8 FLASH 8 Notes: 1. Bit 4 (PSS) in TCSR of WDT1 is valid in the U-mask and W-mask versions, and H8S/2635 Group. In versions other than the U-mask and W-mask versions, and H8S/2635 Group, however, the PSS bit must always be written with 0 since no subclock functions are available. 2. Subclock functions (subactive mode, subsleep mode, and watch mode) are not available in versions other than the U-mask and W-mask versions, and H8S/2635 Group. Subclock functions may be used with the U-mask and W-mask versions, and H8S/2635 Group. 3. Bits DTON, LSON, NESEL, and SUBSTP in LPWRCR are valid in the U-mask and W-mask versions, and H8S/2635 Group. In versions other than the U-mask and W-mask versions, and H8S/2635 Group, however, these bits must always be written with 0 since no subclock functions are available. 4. An I2C bus interface can only be added to the H8S/2638, H8S/2639, and H8S/2630. Therefore, IIC related registers are valid only in the H8S/2638, H8S/2639, and H8S/2630. 5. This bit is reserved in the H8S/2636. 6. This bit is reserved in the H8S/2636 and H8S/2635. 7. These bits are not available in the H8S/2635 and H8S/2634. 8. These bits are reserved in the H8S/2636, H8S/2638, H8S/2639, and H8S/2635. These bits are valid in the H8S/2630 only. Rev. 6.00 Feb 22, 2005 page 1183 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register B.2 Functions Register name Address to which the register is mapped Name of on-chip supporting module D/A Converter Register acronym DACRD/A Control Register H'FFFA Bit numbers Bit 7 DAOE1 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 1 3 1 2 1 1 1 0 1 Initial bit values Initial value Read/Write Names of the bits. Dashes () indicate reserved bits. D/A Enabled DAOE1 DAOE0 DAE * 0 1 1 0 0 1 1 * Conversion result Channel 0 and 1 D/A conversion disabled Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled Channel 0 and 1 D/A conversion enabled Channel 0 D/A conversion disabled Channel 1 D/A conversion enabled Channel 0 and 1 D/A conversion enabled Channel 0 and 1 D/A conversion enabled Possible types of access R W Read only Write only 0 0 1 Full name of bit R/W Read and write Descriptions of bit settings D/A Output Enable 0 0 1 Analog output DA0 disabled Channel 0 D/A conversion enabled. Analog output DA0 enabled D/A Output Enable 1 0 1 Analog output DA1 disabled Channel 1 D/A conversion enabled. Analog output DA1 enabled Rev. 6.00 Feb 22, 2005 page 1184 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MRA--DTC Mode Register A Bit Initial value Read/Write 7 SM1 6 SM0 5 DM1 4 DM0 H'EBC0 to H'EFBF 3 MD1 2 MD0 1 DTS 0 Sz DTC* Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined DTC Data Transfer Size 0 Byte-size transfer 1 Word-size transfer DTC Transfer Mode Select 0 Destination side is repeat area or block area 1 Source side is repeat area or block area DTC Mode 0 1 0 Normal mode 1 Repeat mode 0 Block transfer mode 1 Destination Address Mode 0 DAR is fixed 1 0 DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 1 DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) Source Address Mode 0 SAR is fixed 1 0 SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 1 SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) Note: * This register is not available in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 1185 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MRB--DTC Mode Register B Bit Initial value Read/Write 7 CHNE 6 DISEL 5 4 H'EBC0 to H'EFBF 3 2 1 0 DTC* Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined DTC Interrupt Select 0 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 1 After a data transfer ends, the CPU interrupt is enabled DTC Chain Transfer Enable 0 End of DTC data transfer 1 DTC chain transfer Note: * This register is not available in the H8S/2635 and H8S/2634. SAR--DTC Source Address Register Bit Initial value Read/Write 23 22 21 20 19 H'EBC0 to H'EFBF --------4 3 2 1 0 DTC* Unde- Unde- Unde- Unde- Undefined fined fined fined fined Unde- Unde- Unde- Unde- Undefined fined fined fined fined Specify DTC transfer data source address Note: * This register is not available in the H8S/2635 and H8S/2634. DAR--DTC Destination Address Register Bit Initial value Read/Write 23 22 21 20 19 H'EBC0 to H'EFBF --------4 3 2 1 0 DTC* Unde- Unde- Unde- Unde- Undefined fined fined fined fined Unde- Unde- Unde- Unde- Undefined fined fined fined fined Specify DTC transfer data destination address Note: * This register is not available in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 1186 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register CRA--DTC Transfer Count Register A Bit Initial value Read/Write 15 14 13 12 11 10 9 8 H'EBC0 to H'EFBF 7 6 5 4 3 2 1 DTC* 0 Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined CRAH CRAL Specify the number of DTC data transfers Note: * This register is not available in the H8S/2635 and H8S/2634. CRB--DTC Transfer Count Register B Bit Initial value Read/Write 15 14 13 12 11 10 9 8 H'EBC0 to H'EFBF 7 6 5 4 3 2 1 DTC* 0 Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined Specify the number of DTC block data transfers Note: * This register is not available in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 1187 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MCR0--Master Control Register MCR1--Master Control Register Bit Initial value Read/Write 7 MCR7 0 R/W 6 0 R 5 MCR5 0 R/W 4 0 R H'F800 H'FA00 3 0 R 2 MCR2 0 R/W 1 MCR1 0 R/W HCAN0 HCAN1* 0 MCR0 1 R/W Reset Request 0 Normal operating mode (MCR0 = 0 and GSR3 = 0) [Setting condition] * When 0 is written after an HCAN reset 1 HCAN reset mode transition request Halt Request 0 HCAN normal operating mode 1 HCAN halt mode transition request Message Transmission Method 0 Transmission order determined by message identifier priority 1 Transmission order determined by mailbox (buffer) number priority (TXPR1 > TXPR15) HCAN Sleep Mode 0 HCAN sleep mode released 1 Transition to HCAN sleep mode enabled HCAN Sleep Mode Release 0 HCAN sleep mode release by CAN bus operation disabled 1 HCAN sleep mode release by CAN bus operation enabled Note: * This register is not available in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 1188 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register GSR0--General Status Register GSR1--General Status Register Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R H'F801 H'FA01 3 GSR3 1 R 2 GSR2 1 R 1 GSR1 0 R HCAN0 HCAN1* 0 GSR0 0 R Bus Off Flag 0 [Reset condition] * Recovery from bus off state 1 When TEC 256 (bus off state) Transmit/Receive Warning Flag 0 [Reset condition] * When TEC < 96 and REC < 96 or TEC 256 1 When TEC 96 or REC 96 Message Transmission Status Flag 0 Message transmission period 1 [Reset condition] * Idle state Reset Status Bit 0 Normal operating state [Setting condition] * After an HCAN internal reset 1 Configuration mode [Reset condition] * MCR0 reset mode and sleep mode Note: * This register is not available in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 1189 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register BCR0--Bit Configuration Register BCR1--Bit Configuration Register Bit Initial value Read/Write 15 BCR7 0 R/W 14 BCR6 0 R/W 13 BCR5 0 R/W 12 BCR4 0 R/W H'F802 H'FA02 11 BCR3 0 R/W 10 BCR2 0 R/W 9 BCR1 0 R/W HCAN0 HCAN1* 8 BCR0 0 R/W Resynchronization Jump Width 0 1 0 Bit synchronization width = 1 time quantum 1 Bit synchronization width = 2 time quanta 0 Bit synchronization width = 3 time quanta 1 Bit synchronization width = 4 time quanta Baud Rate Prescaler 0 0 0 . . 1 0 0 0 . . 1 0 0 0 . . 1 0 0 0 . . 1 0 0 1 . . 1 0 2 x system clock 1 4 x system clock 0 6 x system clock . . . . 1 128 x system clock Bit Initial value Read/Write 7 BCR15 0 R/W 6 BCR14 0 R/W 5 BCR13 0 R/W 4 BCR12 0 R/W 3 BCR11 0 R/W 2 BCR10 0 R/W 1 BCR9 0 R/W 0 BCR8 0 R/W Time Segment 2 0 0 1 1 0 1 0 Setting prohibited 1 TSEG2 = 2 time quanta 0 TSEG2 = 3 time quanta 1 TSEG2 = 4 time quanta 0 TSEG2 = 5 time quanta 1 TSEG2 = 6 time quanta 0 TSEG2 = 7 time quanta 1 TSEG2 = 8 time quanta Bit Sample Point Time Segment 1 0 0 0 0 0 . . 1 0 0 0 0 1 . . 1 0 0 1 1 0 . . 1 0 Setting prohibited 1 Setting prohibited 0 Setting prohibited 1 TSEG1 = 4 time quanta 0 TSEG1 = 5 time quanta . . . . 1 TSEG1 = 16 time quanta 0 Bit sampling at one point (end of time segment 1 (TSEG1)) 1 Bit sampling at three points (end of time segment 1 (TSEG1) and preceding and following time quanta) Note: * This register is not available in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 1190 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MBCR0--Mailbox Configuration Register MBCR1--Mailbox Configuration Register Bit Initial value Read/Write Bit Initial value Read/Write 15 MBCR7 0 R/W 7 0 R/W 14 0 R/W 6 0 R/W 13 0 R/W 5 0 R/W 12 0 R/W 4 0 R/W H'F804 H'FA04 11 0 R/W 3 0 R/W 10 0 R/W 2 0 R/W 9 MBCR1 0 R/W 1 0 R/W HCAN0 HCAN1* 8 1 R 0 0 R/W MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8 Mailbox Setting Register 0 1 Corresponding mailbox is set for transmission Corresponding mailbox is set for reception Note: * This register is not available in the H8S/2635 and H8S/2634. TXPR0--Transmit Wait Register TXPR1--Transmit Wait Register Bit Initial value Read/Write Bit Initial value Read/Write 15 TXPR7 0 R/W 7 0 R/W 14 TXPR6 0 R/W 6 0 R/W 13 TXPR5 0 R/W 5 0 R/W 12 TXPR4 0 R/W 4 0 R/W H'F806 H'FA06 11 TXPR3 0 R/W 3 0 R/W 10 TXPR2 0 R/W 2 0 R/W 9 TXPR1 0 R/W 1 TXPR9 0 R/W HCAN0 HCAN1* 8 0 R 0 TXPR8 0 R/W TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 Transmit Wait Register 0 Transmit message idle state in corresponding mailbox [Clearing condition] * Message transmission completion and cancellation completion Transmit message transmit wait in corresponding mailbox (CAN bus arbitration) 1 Note: * This register is not available in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 1191 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TXCR0--Transmit Wait Cancel Register TXCR1--Transmit Wait Cancel Register Bit Initial value Read/Write Bit Initial value Read/Write 15 TXCR7 0 R/W 7 0 R/W 14 TXCR6 0 R/W 6 0 R/W 13 TXCR5 0 R/W 5 0 R/W 12 TXCR4 0 R/W 4 0 R/W H'F808 H'FA08 11 TXCR3 0 R/W 3 0 R/W 10 TXCR2 0 R/W 2 0 R/W 9 TXCR1 0 R/W 1 0 R/W HCAN0 HCAN1* 8 0 R 0 TXCR8 0 R/W TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 Transmit Wait Cancel Register 0 Transmit message cancellation idle state in corresponding mailbox [Clearing condition] * Completion of TXPR clearing (when transmit message is canceled normally) TXPR cleared for corresponding mailbox (transmit message cancellation) 1 Note: * This register is not available in the H8S/2635 and H8S/2634. TXACK0--Transmit Acknowledge Register TXACK1--Transmit Acknowledge Register Bit Initial value Read/Write Bit Initial value Read/Write 15 0 R/W 7 0 R/W 14 0 R/W 6 0 R/W 13 0 R/W 5 0 R/W 12 0 R/W 4 0 R/W H'F80A H'FA04 11 0 R/W 3 0 R/W 10 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W HCAN0 HCAN1* 8 0 R 0 0 R/W TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8 Transmit Acknowledge Register 0 1 [Clearing condition] * Writing 1 Completion of message transmission for corresponding mailbox Note: * This register is not available in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 1192 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register ABACK0--Abort Acknowledge Register ABACK1--Abort Acknowledge Register Bit Initial value Read/Write Bit Initial value Read/Write 15 ABACK7 0 R/W 7 0 R/W 14 0 R/W 6 0 R/W 13 0 R/W 5 0 R/W 12 0 R/W 4 0 R/W H'F80C H'FA0C 11 0 R/W 3 0 R/W 10 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W HCAN0 HCAN1* 8 0 R 0 0 R/W ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8 Abort Acknowledge Register 0 1 [Clearing condition] * Writing 1 Completion of transmit message cancellation for corresponding mailbox Note: * This register is not available in the H8S/2635 and H8S/2634. RXPR0--Receive Complete Register RXPR1--Receive Complete Register Bit Initial value Read/Write Bit Initial value Read/Write 15 RXPR7 0 R/W 7 0 R/W 14 RXPR6 0 R/W 6 0 R/W 13 RXPR5 0 R/W 5 0 R/W 12 RXPR4 0 R/W 4 0 R/W H'F80E H'FA0E 11 RXPR3 0 R/W 3 0 R/W 10 RXPR2 0 R/W 2 0 R/W 9 RXPR1 0 R/W 1 0 R/W HCAN0 HCAN1* 8 RXPR0 0 R/W 0 RXPR8 0 R/W RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 Receive Complete Register 0 1 [Clearing condition] * Writing 1 Completion of message (data frame or remote frame) reception in corresponding mailbox Note: * This register is not available in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 1193 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register RFPR0--Remote Request Register RFPR1--Remote Request Register Bit Initial value Read/Write Bit Initial value Read/Write 15 RFPR7 0 R/W 7 0 R/W 14 RFPR6 0 R/W 6 0 R/W 13 RFPR5 0 R/W 5 0 R/W 12 RFPR4 0 R/W 4 0 R/W H'F810 H'FA10 11 RFPR3 0 R/W 3 0 R/W 10 RFPR2 0 R/W 2 0 R/W 9 RFPR1 0 R/W 1 0 R/W HCAN0 HCAN1* 8 RFPR0 0 R/W 0 RFPR8 0 R/W RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 Remote Request Register 0 1 [Clearing condition] * Writing 1 Completion of remote frame reception in corresponding mailbox Note: * This register is not available in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 1194 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register IRR0--Interrupt Register IRR1--Interrupt Register H'F812 H'FA12 HCAN0 HCAN1* Note: * This register is not available in the H8S/2635 and H8S/2634. Bit Initial value Read/Write 15 IRR7 0 R/W 14 IRR6 0 R/W 13 IRR5 0 R/W 12 IRR4 0 R/W 11 IRR3 0 R/W 10 IRR2 0 R 9 IRR1 0 R 8 IRR0 1 R/W Reset Interrupt Flag 0 1 [Clearing condition] * Writing 1 Hardware reset (HCAN module stop*, software standby) [Setting condition] * When reset processing is completed after a hardware reset (HCAN module stop*, software standby) Note: * After reset or hardware standby release, the module stop bit is initialized to 1, and so the HCAN enters the module stop state. Receive Message Interrupt Flag 0 [Clearing condition] * Clearing of all bits in RXPR (receive complete register) of mailbox for which receive interrupt requests are enabled by MBIMR Data frame or remote frame received and stored in mailbox [Setting condition] * When data frame or remote frame reception is completed, when corresponding MBIMR = 0 1 Remote Frame Request Interrupt Flag 0 [Clearing condition] * Clearing of all bits in RFPR (remote request register) of mailbox for which receive interrupt requests are enabled by MBIMR Remote frame received and stored in mailbox [Setting condition] * When remote frame reception is completed, when corresponding MBIMR = 0 1 Transmit Overload Warning Interrupt Flag 0 [Clearing condition] * Writing 1 1 Error warning state caused by transmit error [Setting condition] * When TEC 96 Receive Overload Warning Interrupt Flag 0 [Clearing condition] * Writing 1 1 Error warning state caused by receive error [Setting condition] * When REC 96 Error Passive Interrupt Flag 0 [Clearing condition] * Writing 1 1 Error passive state caused by transmit/receive error [Setting condition] * When TEC 128 or REC 128 Bus Off Interrupt Flag 0 1 [Clearing condition] * Writing 1 Bus off state caused by transmit error [Setting condition] * When TEC 256 Overload Frame Interrupt Flag 0 [Clearing condition] * Writing 1 1 Overload frame transmission [Setting condition] * Overload frame is transmitted Rev. 6.00 Feb 22, 2005 page 1195 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Bit Initial value Read/Write 7 0 6 0 5 0 4 IRR12 0 R/W 3 0 2 0 1 IRR9 0 R 0 IRR8 0 R/W Mailbox Empty Interrupt Flag 0 [Clearing condition] * Writing 1 1 Transmit message has been transmitted or aborted, and new message can be stored [Setting condition] * When TXPR (transmit wait register) is cleared by completion of transmission or completion of transmission abort Unread Interrupt Flag 0 [Clearing condition] * Clearing of all bits in UMSR (unread message status register) 1 Unread message overwrite [Setting condition] * When UMSR (unread message status register) is set Bus Operation Interrupt Flag 0 CAN bus idle state [Clearing condition] * Writing 1 1 CAN bus operation in HCAN sleep mode [Setting condition] * Bus operation (dominant bit detection) in HCAN sleep mode Rev. 6.00 Feb 22, 2005 page 1196 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MBIMR0--Mailbox Interrupt Mask Register MBIMR1--Mailbox Interrupt Mask Register Bit Initial value Read/Write Bit Initial value Read/Write 15 1 R/W 7 1 R/W 14 1 R/W 6 1 R/W 13 1 R/W 5 1 R/W 12 1 R/W 4 1 R/W H'F814 H'FA14 11 1 R/W 3 1 R/W 10 1 R/W 2 1 R/W 9 1 R/W 1 1 R/W HCAN0 HCAN1* 8 1 R/W 0 1 R/W MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0 MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8 Mailbox Interrupt Mask 0 [Transmitting] * Interrupt request to CPU due to TXPR clearing [Receiving] * Interrupt request to CPU due to RXPR setting Interrupt requests to CPU disabled 1 Note: * This register is not available in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 1197 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register IMR0--Interrupt Mask Register IMR1--Interrupt Mask Register H'F816 H'FA16 HCAN0 HCAN1* Note: * This register is not available in the H8S/2635 and H8S/2634. 15 14 13 12 11 10 Bit IMR7 Initial value Read/Write 1 R/W IMR6 1 R/W IMR5 1 R/W IMR4 1 R/W IMR3 1 R/W IMR2 1 R/W 9 IMR1 1 R/W 8 0 R Receive Message Interrupt Mask 0 1 Message reception interrupt request (RM1) to CPU by IRR1 enabled Message reception interrupt request (RM1) to CPU by IRR1 disabled Remote Frame Request Interrupt Mask 0 1 Remote frame reception interrupt request (OVR0) to CPU by IRR2 enabled Remote frame reception interrupt request (OVR0) to CPU by IRR2 disabled Transmit Overload Warning Interrupt Mask 0 1 TEC error warning interrupt request (OVR0) to CPU by IRR3 enabled TEC error warning interrupt request (OVR0) to CPU by IRR3 disabled Receive Overload Warning Interrupt Mask 0 1 REC error warning interrupt request (OVR0) to CPU by IRR4 enabled REC error warning interrupt request (OVR0) to CPU by IRR4 disabled Error Passive Interrupt Mask 0 1 Error passive interrupt request to CPU by IRR5 enabled Error passive interrupt request to CPU by IRR5 disabled Bus Off Interrupt Mask 0 1 Bus off interrupt request to CPU by IRR6 enabled Bus off interrupt request to CPU by IRR6 disabled Overload Frame/Bus Off Recovery Interrupt Mask 0 1 Overload frame/bus off recovery interrupt request to CPU by IRR7 enabled Overload frame/bus off recovery interrupt request to CPU by IRR7 disabled Rev. 6.00 Feb 22, 2005 page 1198 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Bit Initial value Read/Write 7 1 R 6 1 R 5 1 R 4 IMR12 1 R/W 3 1 R 2 1 R 1 IMR9 1 R/W 0 IMR8 1 R/W Mailbox Empty Interrupt Mask 0 1 Mailbox empty interrupt request (SLE0) to CPU by IRR8 enabled Mailbox empty interrupt request (SLE0) to CPU by IRR8 disabled Unread Interrupt Mask 0 1 Unread message overwrite interrupt request (OVR0) to CPU by IRR9 enabled Unread message overwrite interrupt request (OVR0) to CPU by IRR9 disabled Bus Operation Interrupt Mask 0 1 Bus operation interrupt request (OVR0) to CPU by IRR12 enabled Bus operation interrupt request (OVR0) to CPU by IRR12 disabled Rev. 6.00 Feb 22, 2005 page 1199 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register REC0--Receive Error Counter REC1--Receive Error Counter Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R H'F818 H'FA18 3 0 R 2 0 R 1 0 R HCAN0 HCAN1* 0 0 R Note: * This register is not available in the H8S/2635 and H8S/2634. TEC0--Transmit Error Counter TEC1--Transmit Error Counter Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R H'F819 H'FA19 3 0 R 2 0 R 1 0 R HCAN0 HCAN1* 0 0 R Note: * This register is not available in the H8S/2635 and H8S/2634. UMSR0--Unread Message Status Register UMSR1--Unread Message Status Register Bit Initial value Read/Write Bit Initial value Read/Write 15 UMSR7 0 R/(W)*2 7 0 14 0 13 0 12 0 H'F81A H'FA1A 11 0 10 0 9 HCAN0 HCAN1*1 8 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 0 0 *2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W) 6 5 4 3 2 1 0 UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8 0 0 0 0 0 0 0 *2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W) Unread Message Status Flags 0 1 [Clearing condition] * Writing 1 Unread receive message is overwritten by a new message [Setting condition] * When a new message is received before RXPR is cleared Notes: 1. This register is not available in the H8S/2635 and H8S/2634. 2. Only 1 can be written, to clear the flag to 0. Rev. 6.00 Feb 22, 2005 page 1200 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register LAFML0--Local Acceptance Filter Masks L LAFMH0--Local Acceptance Filter Masks H LAFML1--Local Acceptance Filter Masks L LAFMH1--Local Acceptance Filter Masks H Bit Initial value Read/Write Bit Initial value Read/Write LAFMH Bit Initial value Read/Write Bit Initial value Read/Write 15 LAFMH7 0 R/W 7 0 R/W 14 0 R/W 6 0 R/W 13 0 R/W 5 0 R/W 12 0 R 4 0 R/W 15 LAFML7 0 R/W 7 0 R/W 14 0 R/W 6 0 R/W 13 0 R/W 5 0 R/W 12 0 R/W 4 0 R/W H'F81C H'F81E H'FA1C H'FA1E 11 0 R/W 3 0 R/W 10 LAFML2 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W HCAN0 HCAN0 HCAN1* HCAN1* 8 0 R/W 0 0 R/W LAFML6 LAFML5 LAFML4 LAFML3 LAFML1 LAFML0 LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFML8 11 0 R 3 0 R/W 10 0 R 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W LAFMH6 LAFMH5 LAFMH1 LAFMH0 LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8 LAFMH Bits 7 to 0 and 15 to 13--11-Bit Identifier Filter 0 1 Stored in MC0 and MD0 (receive-only mailbox) depending on bit match between MC0 message identifier and receive message identifier (Care) Stored in MC0 and MD0 (receive-only mailbox) regardless of bit match between MC0 message identifier and receive message identifier (Don't Care) LAFMH Bits 9 and 8, LAFML bits 15 to 0--18-Bit Identifier Filter 0 1 Stored in MC0 (receive-only mailbox) depending on bit match between MC0 message identifier and receive message identifier (Care) Stored in MC0 (receive-only mailbox) regardless of bit match between MC0 message identifier and receive message identifier (Don't Care) Note: * These registers are not available in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 1201 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC0[1]--Message Control 0[1] MC0[2]--Message Control 0[2] MC0[3]--Message Control 0[3] MC0[4]--Message Control 0[4] MC0[5]--Message Control 0[5] MC0[6]--Message Control 0[6] MC0[7]--Message Control 0[7] MC0[8]--Message Control 0[8] MC0[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W H'F820 H'F821 H'F822 H'F823 H'F824 H'F825 H'F826 H'F827 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC0[2] Bit Initial value Read/Write MC0[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1202 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC0[4] Bit Initial value Read/Write MC0[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC0[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1203 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC0[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC0[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1204 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC1[1]--Message Control 1[1] MC1[2]--Message Control 1[2] MC1[3]--Message Control 1[3] MC1[4]--Message Control 1[4] MC1[5]--Message Control 1[5] MC1[6]--Message Control 1[6] MC1[7]--Message Control 1[7] MC1[8]--Message Control 1[8] MC1[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W H'F828 H'F829 H'F82A H'F82B H'F82C H'F82D H'F82E H'F82F HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC1[2] Bit Initial value Read/Write MC1[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1205 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC1[4] Bit Initial value Read/Write MC1[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC1[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1206 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC1[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC1[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1207 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC2[1]--Message Control 2[1] MC2[2]--Message Control 2[2] MC2[3]--Message Control 2[3] MC2[4]--Message Control 2[4] MC2[5]--Message Control 2[5] MC2[6]--Message Control 2[6] MC2[7]--Message Control 2[7] MC2[8]--Message Control 2[8] MC2[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W H'F830 H'F831 H'F832 H'F833 H'F834 H'F835 H'F836 H'F837 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC2[2] Bit Initial value Read/Write MC2[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1208 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC2[4] Bit Initial value Read/Write MC2[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC2[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1209 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC2[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC2[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1210 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC3[1]--Message Control 3[1] MC3[2]--Message Control 3[2] MC3[3]--Message Control 3[3] MC3[4]--Message Control 3[4] MC3[5]--Message Control 3[5] MC3[6]--Message Control 3[6] MC3[7]--Message Control 3[7] MC3[8]--Message Control 3[8] MC3[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W H'F838 H'F839 H'F83A H'F83B H'F83C H'F83D H'F83E H'F83F HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC3[2] Bit Initial value Read/Write MC3[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1211 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC3[4] Bit Initial value Read/Write MC3[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC3[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1212 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC3[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC3[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1213 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC4[1]--Message Control 4[1] MC4[2]--Message Control 4[2] MC4[3]--Message Control 4[3] MC4[4]--Message Control 4[4] MC4[5]--Message Control 4[5] MC4[6]--Message Control 4[6] MC4[7]--Message Control 4[7] MC4[8]--Message Control 4[8] MC4[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W H'F840 H'F841 H'F842 H'F843 H'F844 H'F845 H'F846 H'F847 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC4[2] Bit Initial value Read/Write MC4[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1214 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC4[4] Bit Initial value Read/Write MC4[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC4[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1215 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC4[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC4[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1216 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC5[1]--Message Control 5[1] MC5[2]--Message Control 5[2] MC5[3]--Message Control 5[3] MC5[4]--Message Control 5[4] MC5[5]--Message Control 5[5] MC5[6]--Message Control 5[6] MC5[7]--Message Control 5[7] MC5[8]--Message Control 5[8] MC5[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W H'F848 H'F849 H'F84A H'F84B H'F84C H'F84D H'F84E H'F84F HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC5[2] Bit Initial value Read/Write MC5[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1217 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC5[4] Bit Initial value Read/Write MC5[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC5[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1218 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC5[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC5[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1219 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC6[1]--Message Control 6[1] MC6[2]--Message Control 6[2] MC6[3]--Message Control 6[3] MC6[4]--Message Control 6[4] MC6[5]--Message Control 6[5] MC6[6]--Message Control 6[6] MC6[7]--Message Control 6[7] MC6[8]--Message Control 6[8] MC6[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W H'F850 H'F851 H'F852 H'F853 H'F854 H'F855 H'F856 H'F857 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC6[2] Bit Initial value Read/Write MC6[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1220 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC6[4] Bit Initial value Read/Write MC6[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC6[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1221 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC6[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC6[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1222 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC7[1]--Message Control 7[1] MC7[2]--Message Control 7[2] MC7[3]--Message Control 7[3] MC7[4]--Message Control 7[4] MC7[5]--Message Control 7[5] MC7[6]--Message Control 7[6] MC7[7]--Message Control 7[7] MC7[8]--Message Control 7[8] MC7[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W H'F858 H'F859 H'F85A H'F85B H'F85C H'F85D H'F85E H'F85F HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC7[2] Bit Initial value Read/Write MC7[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1223 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC7[4] Bit Initial value Read/Write MC7[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC7[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1224 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC7[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC7[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1225 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC8[1]--Message Control 8[1] MC8[2]--Message Control 8[2] MC8[3]--Message Control 8[3] MC8[4]--Message Control 8[4] MC8[5]--Message Control 8[5] MC8[6]--Message Control 8[6] MC8[7]--Message Control 8[7] MC8[8]--Message Control 8[8] MC8[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W H'F860 H'F861 H'F862 H'F863 H'F864 H'F865 H'F866 H'F867 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC8[2] Bit Initial value Read/Write MC8[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1226 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC8[4] Bit Initial value Read/Write MC8[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC8[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1227 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC8[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC8[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1228 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC9[1]--Message Control 9[1] MC9[2]--Message Control 9[2] MC9[3]--Message Control 9[3] MC9[4]--Message Control 9[4] MC9[5]--Message Control 9[5] MC9[6]--Message Control 9[6] MC9[7]--Message Control 9[7] MC9[8]--Message Control 9[8] MC9[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W H'F868 H'F869 H'F86A H'F86B H'F86C H'F86D H'F86E H'F86F HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC9[2] Bit Initial value Read/Write MC9[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1229 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC9[4] Bit Initial value Read/Write MC9[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC9[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1230 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC9[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC9[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1231 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC10[1]--Message Control 10[1] MC10[2]--Message Control 10[2] MC10[3]--Message Control 10[3] MC10[4]--Message Control 10[4] MC10[5]--Message Control 10[5] MC10[6]--Message Control 10[6] MC10[7]--Message Control 10[7] MC10[8]--Message Control 10[8] MC10[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W H'F870 H'F871 H'F872 H'F873 H'F874 H'F875 H'F876 H'F877 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC10[2] Bit Initial value Read/Write MC10[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1232 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC10[4] Bit Initial value Read/Write MC10[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC10[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1233 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC10[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC10[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1234 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC11[1]--Message Control 11[1] MC11[2]--Message Control 11[2] MC11[3]--Message Control 11[3] MC11[4]--Message Control 11[4] MC11[5]--Message Control 11[5] MC11[6]--Message Control 11[6] MC11[7]--Message Control 11[7] MC11[8]--Message Control 11[8] MC11[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W H'F878 H'F879 H'F87A H'F87B H'F87C H'F87D H'F87E H'F87F HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC11[2] Bit Initial value Read/Write MC11[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1235 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC11[4] Bit Initial value Read/Write MC11[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC11[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1236 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC11[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC11[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1237 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC12[1]--Message Control 12[1] MC12[2]--Message Control 12[2] MC12[3]--Message Control 12[3] MC12[4]--Message Control 12[4] MC12[5]--Message Control 12[5] MC12[6]--Message Control 12[6] MC12[7]--Message Control 12[7] MC12[8]--Message Control 12[8] MC12[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W H'F880 H'F881 H'F882 H'F883 H'F884 H'F885 H'F886 H'F887 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC12[2] Bit Initial value Read/Write MC12[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1238 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC12[4] Bit Initial value Read/Write MC12[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC12[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1239 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC12[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC12[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1240 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC13[1]--Message Control 13[1] MC13[2]--Message Control 13[2] MC13[3]--Message Control 13[3] MC13[4]--Message Control 13[4] MC13[5]--Message Control 13[5] MC13[6]--Message Control 13[6] MC13[7]--Message Control 13[7] MC13[8]--Message Control 13[8] MC13[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W H'F888 H'F889 H'F88A H'F88B H'F88C H'F88D H'F88E H'F88F HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC13[2] Bit Initial value Read/Write MC13[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1241 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC13[4] Bit Initial value Read/Write MC13[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC13[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1242 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC13[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC13[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1243 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC14[1]--Message Control 14[1] MC14[2]--Message Control 14[2] MC14[3]--Message Control 14[3] MC14[4]--Message Control 14[4] MC14[5]--Message Control 14[5] MC14[6]--Message Control 14[6] MC14[7]--Message Control 14[7] MC14[8]--Message Control 14[8] MC14[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W H'F890 H'F891 H'F892 H'F893 H'F894 H'F895 H'F896 H'F897 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC14[2] Bit Initial value Read/Write MC14[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1244 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC14[4] Bit Initial value Read/Write MC14[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC14[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1245 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC14[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC14[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1246 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC15[1]--Message Control 15[1] MC15[2]--Message Control 15[2] MC15[3]--Message Control 15[3] MC15[4]--Message Control 15[4] MC15[5]--Message Control 15[5] MC15[6]--Message Control 15[6] MC15[7]--Message Control 15[7] MC15[8]--Message Control 15[8] MC15[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W H'F898 H'F899 H'F89A H'F89B H'F89C H'F89D H'F89E H'F89F HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC15[2] Bit Initial value Read/Write MC15[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1247 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC15[4] Bit Initial value Read/Write MC15[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC15[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1248 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC15[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC15[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1249 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD0[1]--Message Data 0[1] MD0[2]--Message Data 0[2] MD0[3]--Message Data 0[3] MD0[4]--Message Data 0[4] MD0[5]--Message Data 0[5] MD0[6]--Message Data 0[6] MD0[7]--Message Data 0[7] MD0[8]--Message Data 0[8] MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W H'F8B0 H'F8B1 H'F8B2 H'F8B3 H'F8B4 H'F8B5 H'F8B6 H'F8B7 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 Rev. 6.00 Feb 22, 2005 page 1250 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD1[1]--Message Data 1[1] MD1[2]--Message Data 1[2] MD1[3]--Message Data 1[3] MD1[4]--Message Data 1[4] MD1[5]--Message Data 1[5] MD1[6]--Message Data 1[6] MD1[7]--Message Data 1[7] MD1[8]--Message Data 1[8] MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W H'F8B8 H'F8B9 H'F8BA H'F8BB H'F8BC H'F8BD H'F8BE H'F8BF 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 Rev. 6.00 Feb 22, 2005 page 1251 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD2[1]--Message Data 2[1] MD2[2]--Message Data 2[2] MD2[3]--Message Data 2[3] MD2[4]--Message Data 2[4] MD2[5]--Message Data 2[5] MD2[6]--Message Data 2[6] MD2[7]--Message Data 2[7] MD2[8]--Message Data 2[8] MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W H'F8C0 H'F8C1 H'F8C2 H'F8C3 H'F8C4 H'F8C5 H'F8C6 H'F8C7 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 Rev. 6.00 Feb 22, 2005 page 1252 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD3[1]--Message Data 3[1] MD3[2]--Message Data 3[2] MD3[3]--Message Data 3[3] MD3[4]--Message Data 3[4] MD3[5]--Message Data 3[5] MD3[6]--Message Data 3[6] MD3[7]--Message Data 3[7] MD3[8]--Message Data 3[8] MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W H'F8C8 H'F8C9 H'F8CA H'F8CB H'F8CC H'F8CD H'F8CE H'F8CF 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 Rev. 6.00 Feb 22, 2005 page 1253 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD4[1]--Message Data 4[1] MD4[2]--Message Data 4[2] MD4[3]--Message Data 4[3] MD4[4]--Message Data 4[4] MD4[5]--Message Data 4[5] MD4[6]--Message Data 4[6] MD4[7]--Message Data 4[7] MD4[8]--Message Data 4[8] MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W H'F8D0 H'F8D1 H'F8D2 H'F8D3 H'F8D4 H'F8D5 H'F8D6 H'F8D7 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 Rev. 6.00 Feb 22, 2005 page 1254 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD5[1]--Message Data 5[1] MD5[2]--Message Data 5[2] MD5[3]--Message Data 5[3] MD5[4]--Message Data 5[4] MD5[5]--Message Data 5[5] MD5[6]--Message Data 5[6] MD5[7]--Message Data 5[7] MD5[8]--Message Data 5[8] MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W H'F8D8 H'F8D9 H'F8DA H'F8DB H'F8DC H'F8DD H'F8DE H'F8DF 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 Rev. 6.00 Feb 22, 2005 page 1255 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD6[1]--Message Data 6[1] MD6[2]--Message Data 6[2] MD6[3]--Message Data 6[3] MD6[4]--Message Data 6[4] MD6[5]--Message Data 6[5] MD6[6]--Message Data 6[6] MD6[7]--Message Data 6[7] MD6[8]--Message Data 6[8] MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W H'F8E0 H'F8E1 H'F8E2 H'F8E3 H'F8E4 H'F8E5 H'F8E6 H'F8E7 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 Rev. 6.00 Feb 22, 2005 page 1256 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD7[1]--Message Data 7[1] MD7[2]--Message Data 7[2] MD7[3]--Message Data 7[3] MD7[4]--Message Data 7[4] MD7[5]--Message Data 7[5] MD7[6]--Message Data 7[6] MD7[7]--Message Data 7[7] MD7[8]--Message Data 7[8] MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W H'F8E8 H'F8E9 H'F8EA H'F8EB H'F8EC H'F8ED H'F8EE H'F8EF 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 Rev. 6.00 Feb 22, 2005 page 1257 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD8[1]--Message Data 8[1] MD8[2]--Message Data 8[2] MD8[3]--Message Data 8[3] MD8[4]--Message Data 8[4] MD8[5]--Message Data 8[5] MD8[6]--Message Data 8[6] MD8[7]--Message Data 8[7] MD8[8]--Message Data 8[8] MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W H'F8F0 H'F8F1 H'F8F2 H'F8F3 H'F8F4 H'F8F5 H'F8F6 H'F8F7 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 Rev. 6.00 Feb 22, 2005 page 1258 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD9[1]--Message Data 9[1] MD9[2]--Message Data 9[2] MD9[3]--Message Data 9[3] MD9[4]--Message Data 9[4] MD9[5]--Message Data 9[5] MD9[6]--Message Data 9[6] MD9[7]--Message Data 9[7] MD9[8]--Message Data 9[8] MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W H'F8F8 H'F8F9 H'F8FA H'F8FB H'F8FC H'F8FD H'F8FE H'F8FF 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 Rev. 6.00 Feb 22, 2005 page 1259 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD10[1]--Message Data 10[1] MD10[2]--Message Data 10[2] MD10[3]--Message Data 10[3] MD10[4]--Message Data 10[4] MD10[5]--Message Data 10[5] MD10[6]--Message Data 10[6] MD10[7]--Message Data 10[7] MD10[8]--Message Data 10[8] MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W H'F900 H'F901 H'F902 H'F903 H'F904 H'F905 H'F906 H'F907 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 Rev. 6.00 Feb 22, 2005 page 1260 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD11[1]--Message Data 11[1] MD11[2]--Message Data 11[2] MD11[3]--Message Data 11[3] MD11[4]--Message Data 11[4] MD11[5]--Message Data 11[5] MD11[6]--Message Data 11[6] MD11[7]--Message Data 11[7] MD11[8]--Message Data 11[8] MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W H'F908 H'F909 H'F90A H'F90B H'F90C H'F90D H'F90E H'F90F 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 Rev. 6.00 Feb 22, 2005 page 1261 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD12[1]--Message Data 12[1] MD12[2]--Message Data 12[2] MD12[3]--Message Data 12[3] MD12[4]--Message Data 12[4] MD12[5]--Message Data 12[5] MD12[6]--Message Data 12[6] MD12[7]--Message Data 12[7] MD12[8]--Message Data 12[8] MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W H'F910 H'F911 H'F912 H'F913 H'F914 H'F915 H'F916 H'F917 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 Rev. 6.00 Feb 22, 2005 page 1262 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD13[1]--Message Data 13[1] MD13[2]--Message Data 13[2] MD13[3]--Message Data 13[3] MD13[4]--Message Data 13[4] MD13[5]--Message Data 13[5] MD13[6]--Message Data 13[6] MD13[7]--Message Data 13[7] MD13[8]--Message Data 13[8] MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W H'F918 H'F919 H'F91A H'F91B H'F91C H'F91D H'F91E H'F91F 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 Rev. 6.00 Feb 22, 2005 page 1263 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD14[1]--Message Data 14[1] MD14[2]--Message Data 14[2] MD14[3]--Message Data 14[3] MD14[4]--Message Data 14[4] MD14[5]--Message Data 14[5] MD14[6]--Message Data 14[6] MD14[7]--Message Data 14[7] MD14[8]--Message Data 14[8] MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W H'F920 H'F921 H'F922 H'F923 H'F924 H'F925 H'F926 H'F927 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 Rev. 6.00 Feb 22, 2005 page 1264 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD15[1]--Message Data 15[1] MD15[2]--Message Data 15[2] MD15[3]--Message Data 15[3] MD15[4]--Message Data 15[4] MD15[5]--Message Data 15[5] MD15[6]--Message Data 15[6] MD15[7]--Message Data 15[7] MD15[8]--Message Data 15[8] MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W H'F928 H'F929 H'F92A H'F92B H'F92C H'F92D H'F92E H'F92F 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 HCAN0 Rev. 6.00 Feb 22, 2005 page 1265 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC0[1]--Message Control 0[1] MC0[2]--Message Control 0[2] MC0[3]--Message Control 0[3] MC0[4]--Message Control 0[4] MC0[5]--Message Control 0[5] MC0[6]--Message Control 0[6] MC0[7]--Message Control 0[7] MC0[8]--Message Control 0[8] H'FA20 H'FA21 H'FA22 H'FA23 H'FA24 H'FA25 H'FA26 H'FA27 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MC0[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC0[2] Bit Initial value Read/Write MC0[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1266 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC0[4] Bit Initial value Read/Write MC0[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC0[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1267 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC0[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC0[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1268 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC1[1]--Message Control 1[1] MC1[2]--Message Control 1[2] MC1[3]--Message Control 1[3] MC1[4]--Message Control 1[4] MC1[5]--Message Control 1[5] MC1[6]--Message Control 1[6] MC1[7]--Message Control 1[7] MC1[8]--Message Control 1[8] H'FA28 H'FA29 H'FA2A H'FA2B H'FA2C H'FA2D H'FA2E H'FA2F HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MC1[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC1[2] Bit Initial value Read/Write MC1[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1269 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC1[4] Bit Initial value Read/Write MC1[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC1[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1270 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC1[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC1[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1271 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC2[1]--Message Control 2[1] MC2[2]--Message Control 2[2] MC2[3]--Message Control 2[3] MC2[4]--Message Control 2[4] MC2[5]--Message Control 2[5] MC2[6]--Message Control 2[6] MC2[7]--Message Control 2[7] MC2[8]--Message Control 2[8] H'FA30 H'FA31 H'FA32 H'FA33 H'FA34 H'FA35 H'FA36 H'FA37 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MC2[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC2[2] Bit Initial value Read/Write MC2[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1272 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC2[4] Bit Initial value Read/Write MC2[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC2[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1273 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC2[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC2[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1274 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC3[1]--Message Control 3[1] MC3[2]--Message Control 3[2] MC3[3]--Message Control 3[3] MC3[4]--Message Control 3[4] MC3[5]--Message Control 3[5] MC3[6]--Message Control 3[6] MC3[7]--Message Control 3[7] MC3[8]--Message Control 3[8] H'FA38 H'FA39 H'FA3A H'FA3B H'FA3C H'FA3D H'FA3E H'FA3F HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MC3[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC3[2] Bit Initial value Read/Write MC3[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1275 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC3[4] Bit Initial value Read/Write MC3[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC3[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1276 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC3[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC3[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1277 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC4[1]--Message Control 4[1] MC4[2]--Message Control 4[2] MC4[3]--Message Control 4[3] MC4[4]--Message Control 4[4] MC4[5]--Message Control 4[5] MC4[6]--Message Control 4[6] MC4[7]--Message Control 4[7] MC4[8]--Message Control 4[8] H'FA40 H'FA41 H'FA42 H'FA43 H'FA44 H'FA45 H'FA46 H'FA47 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MC4[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC4[2] Bit Initial value Read/Write MC4[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1278 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC4[4] Bit Initial value Read/Write MC4[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC4[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1279 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC4[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC4[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1280 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC5[1]--Message Control 5[1] MC5[2]--Message Control 5[2] MC5[3]--Message Control 5[3] MC5[4]--Message Control 5[4] MC5[5]--Message Control 5[5] MC5[6]--Message Control 5[6] MC5[7]--Message Control 5[7] MC5[8]--Message Control 5[8] H'FA48 H'FA49 H'FA4A H'FA4B H'FA4C H'FA4D H'FA4E H'FA4F HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MC5[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC5[2] Bit Initial value Read/Write MC5[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1281 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC5[4] Bit Initial value Read/Write MC5[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC5[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1282 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC5[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC5[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1283 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC6[1]--Message Control 6[1] MC6[2]--Message Control 6[2] MC6[3]--Message Control 6[3] MC6[4]--Message Control 6[4] MC6[5]--Message Control 6[5] MC6[6]--Message Control 6[6] MC6[7]--Message Control 6[7] MC6[8]--Message Control 6[8] H'FA50 H'FA51 H'FA52 H'FA53 H'FA54 H'FA55 H'FA56 H'FA57 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MC6[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC6[2] Bit Initial value Read/Write MC6[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1284 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC6[4] Bit Initial value Read/Write MC6[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC6[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1285 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC6[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC6[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1286 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC7[1]--Message Control 7[1] MC7[2]--Message Control 7[2] MC7[3]--Message Control 7[3] MC7[4]--Message Control 7[4] MC7[5]--Message Control 7[5] MC7[6]--Message Control 7[6] MC7[7]--Message Control 7[7] MC7[8]--Message Control 7[8] H'FA58 H'FA59 H'FA5A H'FA5B H'FA5C H'FA5D H'FA5E H'FA5F HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MC7[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC7[2] Bit Initial value Read/Write MC7[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1287 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC7[4] Bit Initial value Read/Write MC7[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC7[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1288 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC7[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC7[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1289 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC8[1]--Message Control 8[1] MC8[2]--Message Control 8[2] MC8[3]--Message Control 8[3] MC8[4]--Message Control 8[4] MC8[5]--Message Control 8[5] MC8[6]--Message Control 8[6] MC8[7]--Message Control 8[7] MC8[8]--Message Control 8[8] H'FA60 H'FA61 H'FA62 H'FA63 H'FA64 H'FA65 H'FA66 H'FA67 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MC8[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC8[2] Bit Initial value Read/Write MC8[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1290 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC8[4] Bit Initial value Read/Write MC8[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC8[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1291 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC8[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC8[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1292 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC9[1]--Message Control 9[1] MC9[2]--Message Control 9[2] MC9[3]--Message Control 9[3] MC9[4]--Message Control 9[4] MC9[5]--Message Control 9[5] MC9[6]--Message Control 9[6] MC9[7]--Message Control 9[7] MC9[8]--Message Control 9[8] H'FA68 H'FA69 H'FA6A H'FA6B H'FA6C H'FA6D H'FA6E H'FA6F HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MC9[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC9[2] Bit Initial value Read/Write MC9[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1293 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC9[4] Bit Initial value Read/Write MC9[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC9[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1294 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC9[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC9[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1295 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC10[1]--Message Control 10[1] MC10[2]--Message Control 10[2] MC10[3]--Message Control 10[3] MC10[4]--Message Control 10[4] MC10[5]--Message Control 10[5] MC10[6]--Message Control 10[6] MC10[7]--Message Control 10[7] MC10[8]--Message Control 10[8] H'FA70 H'FA71 H'FA72 H'FA73 H'FA74 H'FA75 H'FA76 H'FA77 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MC10[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC10[2] Bit Initial value Read/Write MC10[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1296 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC10[4] Bit Initial value Read/Write MC10[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC10[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1297 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC10[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC10[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1298 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC11[1]--Message Control 11[1] MC11[2]--Message Control 11[2] MC11[3]--Message Control 11[3] MC11[4]--Message Control 11[4] MC11[5]--Message Control 11[5] MC11[6]--Message Control 11[6] MC11[7]--Message Control 11[7] MC11[8]--Message Control 11[8] H'FA78 H'FA79 H'FA7A H'FA7B H'FA7C H'FA7D H'FA7E H'FA7F HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MC11[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC11[2] Bit Initial value Read/Write MC11[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1299 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC11[4] Bit Initial value Read/Write MC11[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC11[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1300 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC11[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC11[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1301 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC12[1]--Message Control 12[1] MC12[2]--Message Control 12[2] MC12[3]--Message Control 12[3] MC12[4]--Message Control 12[4] MC12[5]--Message Control 12[5] MC12[6]--Message Control 12[6] MC12[7]--Message Control 12[7] MC12[8]--Message Control 12[8] H'FA80 H'FA81 H'FA82 H'FA83 H'FA84 H'FA85 H'FA86 H'FA87 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MC12[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC12[2] Bit Initial value Read/Write MC12[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1302 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC12[4] Bit Initial value Read/Write MC12[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC12[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1303 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC12[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC12[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1304 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC13[1]--Message Control 13[1] MC13[2]--Message Control 13[2] MC13[3]--Message Control 13[3] MC13[4]--Message Control 13[4] MC13[5]--Message Control 13[5] MC13[6]--Message Control 13[6] MC13[7]--Message Control 13[7] MC13[8]--Message Control 13[8] H'FA88 H'FA89 H'FA8A H'FA8B H'FA8C H'FA8D H'FA8E H'FA8F HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MC13[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC13[2] Bit Initial value Read/Write MC13[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1305 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC13[4] Bit Initial value Read/Write MC13[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC13[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1306 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC13[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC13[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1307 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC14[1]--Message Control 14[1] MC14[2]--Message Control 14[2] MC14[3]--Message Control 14[3] MC14[4]--Message Control 14[4] MC14[5]--Message Control 14[5] MC14[6]--Message Control 14[6] MC14[7]--Message Control 14[7] MC14[8]--Message Control 14[8] H'FA90 H'FA91 H'FA92 H'FA93 H'FA94 H'FA95 H'FA96 H'FA97 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MC14[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC14[2] Bit Initial value Read/Write MC14[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1308 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC14[4] Bit Initial value Read/Write MC14[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC14[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1309 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC14[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC14[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1310 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC15[1]--Message Control 15[1] MC15[2]--Message Control 15[2] MC15[3]--Message Control 15[3] MC15[4]--Message Control 15[4] MC15[5]--Message Control 15[5] MC15[6]--Message Control 15[6] MC15[7]--Message Control 15[7] MC15[8]--Message Control 15[8] H'FA98 H'FA99 H'FA9A H'FA9B H'FA9C H'FA9D H'FA9E H'FA9F HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MC15[1] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 DLC3 R/W 2 DLC2 R/W 1 DLC1 R/W 0 DLC0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Data Length Code 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes 1 0/1 0/1 0/1 Data length = 8 bytes MC15[2] Bit Initial value Read/Write MC15[3] Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1311 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC15[4] Bit Initial value Read/Write MC15[5] Bit Initial value Read/Write 7 6 5 4 RTR R/W 3 IDE R/W 2 R/W 1 0 STD_ID2 STD_ID1 STD_ID0 R/W R/W R/W EXD_ID17 EXD_ID16 R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Identifier Extension 0 Standard format 1 Extended format Remote Transmission Request 0 Data frame 1 Remote frame Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Standard Identifier Set the identifier (standard identifier) of data frames and remote frames MC15[6] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Standard Identifier Set the identifier (standard identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1312 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MC15[7] Bit Initial value Read/Write 7 EXD_ID7 R/W 6 5 4 3 2 1 0 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC15[8] Bit Initial value Read/Write 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Rev. 6.00 Feb 22, 2005 page 1313 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD0[1]--Message Data 0[1] MD0[2]--Message Data 0[2] MD0[3]--Message Data 0[3] MD0[4]--Message Data 0[4] MD0[5]--Message Data 0[5] MD0[6]--Message Data 0[6] MD0[7]--Message Data 0[7] MD0[8]--Message Data 0[8] H'FAB0 H'FAB1 H'FAB2 H'FAB3 H'FAB4 H'FAB5 H'FAB6 H'FAB7 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 Rev. 6.00 Feb 22, 2005 page 1314 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD1[1]--Message Data 1[1] MD1[2]--Message Data 1[2] MD1[3]--Message Data 1[3] MD1[4]--Message Data 1[4] MD1[5]--Message Data 1[5] MD1[6]--Message Data 1[6] MD1[7]--Message Data 1[7] MD1[8]--Message Data 1[8] H'FAB8 H'FAB9 H'FABA H'FABB H'FABC H'FABD H'FABE H'FABF HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 Rev. 6.00 Feb 22, 2005 page 1315 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD2[1]--Message Data 2[1] MD2[2]--Message Data 2[2] MD2[3]--Message Data 2[3] MD2[4]--Message Data 2[4] MD2[5]--Message Data 2[5] MD2[6]--Message Data 2[6] MD2[7]--Message Data 2[7] MD2[8]--Message Data 2[8] H'FAC0 H'FAC1 H'FAC2 H'FAC3 H'FAC4 H'FAC5 H'FAC6 H'FAC7 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 Rev. 6.00 Feb 22, 2005 page 1316 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD3[1]--Message Data 3[1] MD3[2]--Message Data 3[2] MD3[3]--Message Data 3[3] MD3[4]--Message Data 3[4] MD3[5]--Message Data 3[5] MD3[6]--Message Data 3[6] MD3[7]--Message Data 3[7] MD3[8]--Message Data 3[8] H'FAC8 H'FAC9 H'FACA H'FACB H'FACC H'FACD H'FACE H'FACF HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 Rev. 6.00 Feb 22, 2005 page 1317 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD4[1]--Message Data 4[1] MD4[2]--Message Data 4[2] MD4[3]--Message Data 4[3] MD4[4]--Message Data 4[4] MD4[5]--Message Data 4[5] MD4[6]--Message Data 4[6] MD4[7]--Message Data 4[7] MD4[8]--Message Data 4[8] H'FAD0 H'FAD1 H'FAD2 H'FAD3 H'FAD4 H'FAD5 H'FAD6 H'FAD7 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 Rev. 6.00 Feb 22, 2005 page 1318 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD5[1]--Message Data 5[1] MD5[2]--Message Data 5[2] MD5[3]--Message Data 5[3] MD5[4]--Message Data 5[4] MD5[5]--Message Data 5[5] MD5[6]--Message Data 5[6] MD5[7]--Message Data 5[7] MD5[8]--Message Data 5[8] H'FAD8 H'FAD9 H'FADA H'FADB H'FADC H'FADD H'FADE H'FADF HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 Rev. 6.00 Feb 22, 2005 page 1319 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD6[1]--Message Data 6[1] MD6[2]--Message Data 6[2] MD6[3]--Message Data 6[3] MD6[4]--Message Data 6[4] MD6[5]--Message Data 6[5] MD6[6]--Message Data 6[6] MD6[7]--Message Data 6[7] MD6[8]--Message Data 6[8] H'FAE0 H'FAE1 H'FAE2 H'FAE3 H'FAE4 H'FAE5 H'FAE6 H'FAE7 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 Rev. 6.00 Feb 22, 2005 page 1320 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD7[1]--Message Data 7[1] MD7[2]--Message Data 7[2] MD7[3]--Message Data 7[3] MD7[4]--Message Data 7[4] MD7[5]--Message Data 7[5] MD7[6]--Message Data 7[6] MD7[7]--Message Data 7[7] MD7[8]--Message Data 7[8] H'FAE8 H'FAE9 H'FAEA H'FAEB H'FAEC H'FAED H'FAEE H'FAEF HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 Rev. 6.00 Feb 22, 2005 page 1321 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD8[1]--Message Data 8[1] MD8[2]--Message Data 8[2] MD8[3]--Message Data 8[3] MD8[4]--Message Data 8[4] MD8[5]--Message Data 8[5] MD8[6]--Message Data 8[6] MD8[7]--Message Data 8[7] MD8[8]--Message Data 8[8] H'FAF0 H'FAF1 H'FAF2 H'FAF3 H'FAF4 H'FAF5 H'FAF6 H'FAF7 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 Rev. 6.00 Feb 22, 2005 page 1322 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD9[1]--Message Data 9[1] MD9[2]--Message Data 9[2] MD9[3]--Message Data 9[3] MD9[4]--Message Data 9[4] MD9[5]--Message Data 9[5] MD9[6]--Message Data 9[6] MD9[7]--Message Data 9[7] MD9[8]--Message Data 9[8] H'FAF8 H'FAF9 H'FAFA H'FAFB H'FAFC H'FAFD H'FAFE H'FAFF HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 Rev. 6.00 Feb 22, 2005 page 1323 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD10[1]--Message Data 10[1] MD10[2]--Message Data 10[2] MD10[3]--Message Data 10[3] MD10[4]--Message Data 10[4] MD10[5]--Message Data 10[5] MD10[6]--Message Data 10[6] MD10[7]--Message Data 10[7] MD10[8]--Message Data 10[8] H'FB00 H'FB01 H'FB02 H'FB03 H'FB04 H'FB05 H'FB06 H'FB07 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 Rev. 6.00 Feb 22, 2005 page 1324 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD11[1]--Message Data 11[1] MD11[2]--Message Data 11[2] MD11[3]--Message Data 11[3] MD11[4]--Message Data 11[4] MD11[5]--Message Data 11[5] MD11[6]--Message Data 11[6] MD11[7]--Message Data 11[7] MD11[8]--Message Data 11[8] H'FB08 H'FB09 H'FB0A H'FB0B H'FB0C H'FB0D H'FB0E H'FB0F HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 Rev. 6.00 Feb 22, 2005 page 1325 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD12[1]--Message Data 12[1] MD12[2]--Message Data 12[2] MD12[3]--Message Data 12[3] MD12[4]--Message Data 12[4] MD12[5]--Message Data 12[5] MD12[6]--Message Data 12[6] MD12[7]--Message Data 12[7] MD12[8]--Message Data 12[8] H'FB10 H'FB11 H'FB12 H'FB13 H'FB14 H'FB15 H'FB16 H'FB17 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 Rev. 6.00 Feb 22, 2005 page 1326 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD13[1]--Message Data 13[1] MD13[2]--Message Data 13[2] MD13[3]--Message Data 13[3] MD13[4]--Message Data 13[4] MD13[5]--Message Data 13[5] MD13[6]--Message Data 13[6] MD13[7]--Message Data 13[7] MD13[8]--Message Data 13[8] H'FB18 H'FB19 H'FB1A H'FB1B H'FB1C H'FB1D H'FB1E H'FB1F HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 Rev. 6.00 Feb 22, 2005 page 1327 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD14[1]--Message Data 14[1] MD14[2]--Message Data 14[2] MD14[3]--Message Data 14[3] MD14[4]--Message Data 14[4] MD14[5]--Message Data 14[5] MD14[6]--Message Data 14[6] MD14[7]--Message Data 14[7] MD14[8]--Message Data 14[8] H'FB20 H'FB21 H'FB22 H'FB23 H'FB24 H'FB25 H'FB26 H'FB27 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 Rev. 6.00 Feb 22, 2005 page 1328 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MD15[1]--Message Data 15[1] MD15[2]--Message Data 15[2] MD15[3]--Message Data 15[3] MD15[4]--Message Data 15[4] MD15[5]--Message Data 15[5] MD15[6]--Message Data 15[6] MD15[7]--Message Data 15[7] MD15[8]--Message Data 15[8] H'FB28 H'FB29 H'FB2A H'FB2B H'FB2C H'FB2D H'FB2E H'FB2F HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 HCAN1 Note: These registers are not available in the H8S/2635 and H8S/2634. MDx[1] Bit Initial value Read/Write MDx[2] Bit Initial value Read/Write MDx[3] Bit Initial value Read/Write MDx[4] Bit Initial value Read/Write MDx[5] Bit Initial value Read/Write MDx[6] Bit Initial value Read/Write MDx[7] Bit Initial value Read/Write MDx[8] Bit Initial value Read/Write 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 7 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 6 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 5 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 4 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 3 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 2 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 1 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W 0 * R/W *: Undefined x = 0 to 15 Rev. 6.00 Feb 22, 2005 page 1329 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register PWCR1--PWM Control Register 1 Bit Initial value Read/Write 7 1 6 1 5 IE 0 R/W 4 CMF 0 R/(W)* H'FC00 3 CST 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 PWM1 CKS0 0 R/W Clock Select 0 0 1 1 * 0 Internal clock: counts on /1 1 Internal clock: counts on /2 0 Internal clock: counts on /4 1 Internal clock: counts on /8 * Internal clock: counts on /16 *: Don't care Counter Start 0 1 Compare Match Flag 0 PWCNT is stopped PWCNT is started [Clearing conditions] * When 0 is written to CMF after reading CMF = 1 * When the DTC is activated by a compare match interrupt, and the DISEL bit in the DTC's MRB register is 0 [Setting condition] * When PWCNT = PWCYR 1 Interrupt Enable 0 1 Interrupt disabled Interrupt enabled Note: * Only 0 can be written, to clear the flag. Rev. 6.00 Feb 22, 2005 page 1330 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register PWOCR1--PWM Output Control Register 1 Bit Initial value Read/Write 7 OE1H 0 R/W 6 OE1G 0 R/W 5 OE1F 0 R/W 4 OE1E 0 R/W H'FC02 3 OE1D 0 R/W 2 OE1C 0 R/W 1 OE1B 0 R/W PWM1 0 OE1A 0 R/W Output Enable 0 1 PWM output is disabled PWM output is enabled PWPR1--PWM Polarity Register 1 Bit Initial value Read/Write 7 OPS1H 0 R/W 6 OPS1G 0 R/W 5 OPS1F 0 R/W 4 OPS1E 0 R/W H'FC04 3 OPS1D 0 R/W 2 OPS1C 0 R/W 1 OPS1B 0 R/W PWM1 0 OPS1A 0 R/W Output Polarity Select 0 1 PWM direct output PWM inverse output PWCYR1--PWM Cycle Register 1 Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 1 1 9 8 H'FC06 7 1 6 1 5 1 4 1 3 1 2 1 PWM1 1 1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Set the PWM conversion cycle Rev. 6.00 Feb 22, 2005 page 1331 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register PWBFR1A--PWM Buffer Register 1A PWBFR1C--PWM Buffer Register 1C PWBFR1E--PWM Buffer Register 1E PWBFR1G--PWM Buffer Register 1G Bit Initial value Read/Write 15 1 14 1 13 1 12 0 11 1 10 1 9 0 8 0 H'FC08 H'FC0A H'FC0C H'FC0E 7 0 6 0 5 0 4 0 3 0 2 0 1 0 PWM1 PWM1 PWM1 PWM1 0 0 OTS R/W DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Duty Bits 9 to 0 comprise the data transferred to bits 9 to 0 in PWDTR1 Description PWM1A output selected PWM1B output selected PWM1C output selected PWM1D output selected PWM1E output selected PWM1F output selected PWM1G output selected PWM1H output selected Output Terminal Select Bit 12 is the data transferred to bit 12 of PWDTR1 Register PWDTR1A PWDTR1C PWDTR1E PWDTR1G OTS 0 1 0 1 0 1 0 1 Note: When a PWCYR1 compare match occurs, data is transferred from PWBFR1A to PWDTR1A, from PWBFR1C to PWDTR1C, from PWBFR1E to PWDTR1E, and from PWBFR1G to PWDTR1G. Rev. 6.00 Feb 22, 2005 page 1332 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register PWCR2--PWM Control Register 2 Bit Initial value Read/Write 7 1 6 1 5 IE 0 R/W 4 CMF 0 R/(W)* H'FC10 3 CST 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 PWM2 CKS0 0 R/W Clock Select 0 0 1 1 * 0 Internal clock: counts on /1 1 Internal clock: counts on /2 0 Internal clock: counts on /4 1 Internal clock: counts on /8 * Internal clock: counts on /16 *: Don't care Counter Start 0 1 Compare Match Flag 0 PWCNT is stopped PWCNT is started [Clearing conditions] * When 0 is written to CMF after reading CMF = 1 * When the DTC is activated by a compare match interrupt, and the DISEL bit in the DTC's MRB register is 0 [Setting condition] * When PWCNT = PWCYR 1 Interrupt Enable 0 1 Interrupt disabled Interrupt enabled Note: * Only 0 can be written, to clear the flag. Rev. 6.00 Feb 22, 2005 page 1333 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register PWOCR2--PWM Output Control Register 2 Bit Initial value Read/Write 7 OE2H 0 R/W 6 OE2G 0 R/W 5 OE2F 0 R/W 4 OE2E 0 R/W H'FC12 3 OE2D 0 R/W 2 OE2C 0 R/W 1 OE2B 0 R/W PWM2 0 OE2A 0 R/W Output Enable 0 1 PWM output is disabled PWM output is enabled PWPR2--PWM Polarity Register 2 Bit Initial value Read/Write 7 OPS2H 0 R/W 6 OPS2G 0 R/W 5 OPS2F 0 R/W 4 OPS2E 0 R/W H'FC14 3 OPS2D 0 R/W 2 OPS2C 0 R/W 1 OPS2B 0 R/W PWM2 0 OPS2A 0 R/W Output Polarity Select 0 1 PWM direct output PWM inverse output PWCYR2--PWM Cycle Register 2 Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 1 1 9 8 H'FC16 7 1 6 1 5 1 4 1 3 1 2 1 PWM2 1 1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Set the PWM conversion cycle Rev. 6.00 Feb 22, 2005 page 1334 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register PWBFR2A--PWM Buffer Register 2A PWBFR2B--PWM Buffer Register 2B PWBFR2C--PWM Buffer Register 2C PWBFR2D--PWM Buffer Register 2D Bit Initial value Read/Write 15 1 14 1 13 1 12 0 11 1 10 1 9 0 8 0 7 0 H'FC18 H'FC1A H'FC1C H'FC1E 6 0 5 0 4 0 3 0 2 0 1 0 PWM2 PWM2 PWM2 PWM2 0 0 TDS R/W DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Duty Bits 9 to 0 compromise the data transferred to bits 9 to 0 in PWDTR2 Transfer Destination Select Selects the PWDTR2 register to which data is to be transferred Register PWBFR2A PWBFR2B PWBFR2C PWBFR2D TDS 0 1 0 1 0 1 0 1 Description PWDTR2A selected PWDTR2E selected PWDTR2B selected PWDTR2F selected PWDTR2C selected PWDTR2G selected PWDTR2D selected PWDTR2H selected Note: When a PWCYR2 compare match occurs, data is transferred from PWBFR2A to PWDTR2A or PWDTR2E, from PWBFR2B to PWDTR2B or PWDTR2F, from PWBFR2C to PWDTR2C or PWDTR2G, and from PWBFR2D to PWDTR2D or PWDTR2H. PHDDR--Port H Data Direction Register Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W H'FC20 3 0 W 2 0 W 1 0 W 0 0 W Port PH7DDR PH6DDR PH5DDR PH4DDR PH3DDR PH2DDR PH1DDR PH0DDR Rev. 6.00 Feb 22, 2005 page 1335 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register PJDDR--Port J Data Direction Register Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W H'FC21 3 0 W 2 0 W 1 0 W 0 0 W Port PJ7DDR PJ6DDR PJ5DDR PJ4DDR PJ3DDR PJ2DDR PJ1DDR PJ0DDR PHDR--Port H Data Register Bit Initial value Read/Write 7 PH7DR 0 R/W 6 PH6DR 0 R/W 5 PH5DR 0 R/W 4 PH4DR 0 R/W H'FC24 3 PH3DR 0 R/W 2 PH2DR 0 R/W 1 PH1DR 0 R/W 0 Port PH0DR 0 R/W PJDR--Port J Data Register Bit Initial value Read/Write 7 PJ7DR 0 R/W 6 PJ6DR 0 R/W 5 PJ5DR 0 R/W 4 PJ4DR 0 R/W H'FC25 3 PJ3DR 0 R/W 2 PJ2DR 0 R/W 1 PJ1DR 0 R/W 0 Port PJ0DR 0 R/W PORTH--Port H Register Bit Initial value Read/Write 7 PH7 * R 6 PH6 * R 5 PH5 * R 4 PH4 * R H'FC28 3 PH3 * R 2 PH2 * R 1 PH1 * R 0 PH0 * R Port Note: * Determined by the state of PH7 to PH0. PORTJ--Port J Register Bit Initial value Read/Write 7 PJ7 * R 6 PJ6 * R 5 PJ5 * R 4 PJ4 * R H'FC29 3 PJ3 * R 2 PJ2 * R 1 PJ1 * R 0 PJ0 * R Port Note: * Determined by the state of PJ7 to PJ0. Rev. 6.00 Feb 22, 2005 page 1336 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MSTPCRD--Module Stop Control Register D Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 4 H'FC60 3 2 1 System 0 MSTPD7 MSTPD6 MSTPD5 MSTPD4 MSTPD3 MSTPD2 MSTPD1 MSTPD0 Undefined Undefined Undefined Undefined Undefined Undefined Module Stop 0 PWM module stop mode is cleared 1 PWM module stop mode is set SCRX--Serial Control Register X Bit : 7 Initial value : R/W : 0 R/W 6 IICX1 0 R/W 5 IICX0 0 R/W 4 IICE 0 R/W H'FDB4 3 1 2 0 R/W 1 0 R/W 0 0 R/W IIC I2C master enable 0 Disables CPU access of I2C bus interface data register and control register 1 Enables CPU access of I2C bus interface data register and control register I2C transfer rate select 1, 0 Note: This register is valid only when an I2C bus interface has been added as an H8S/2638, H8S/2639, and H8S/2630 option. Rev. 6.00 Feb 22, 2005 page 1337 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register DDCSWR--DDC Switch Register Bit : 7 Initial value : R/W : 0 R/(W)*1 6 0 5 0 4 0 H'FDB5 3 CLR3 1 W*2 2 CLR2 1 W*2 1 CLR1 1 W*2 0 CLR0 1 W*2 IIC R/(W)*1 R/(W)*1 R/(W)*1 Reserved bit IIC clear 3 to 0 CLR3 CLR2 CLR1 CLR0 0 0 Setting prohibited 1 0 0 Setting prohibited 1 IIC0 internal latch cleared 1 0 IIC1 internal latch cleared IIC0 and IIC1 internal latches cleared 1 Invalid setting 1 Notes: This register is valid only when an I2C bus interface has been added as an H8S/2638, H8S/2639, and H8S/2630 option. 1. Should always be written with 0. 2. Always read as 1. Rev. 6.00 Feb 22, 2005 page 1338 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register SBYCR--Standby Control Register Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 1 R/W 5 STS1 0 R/W 4 STS0 1 R/W H'FDE4 3 OPE 1 R/W 2 0 1 0 System 0 0 Output Port Enable 0 1 In software standby mode, watch mode, and when making a direct transition, address bus and bus control signals are high-impedance In software standby mode, watch mode, and when making a direct transition, the output state of the address bus and bus control signals is retained Standby Timer Select 2 to 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Software Standby 0 * Shifts to sleep mode when the SLEEP instruction is executed in high-speed mode or medium-speed mode * Shifts to sub-sleep mode when the SLEEP instruction is executed in sub-active mode * Shifts to software standby mode, sub-active mode, and watch mode when the SLEEP instruction is executed in high-speed mode or medium-speed mode * Shifts to watch mode or high-speed mode when the SLEEP instruction is executed in sub-active mode Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states (Setting prohibited) 1 Rev. 6.00 Feb 22, 2005 page 1339 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register SYSCR--System Control Register Bit Initial value Read/Write 7 MACS 0 R/W 6 0 5 INTM1 0 R/W 4 INTM0 0 R/W H'FDE5 3 NMIEG 0 R/W 2 0 1 0 System 0 RAME 1 R/W RAM Enable 0 On-chip RAM is disabled 1 On-chip RAM is enabled NMI Edge Select 0 An interrupt is requested at the falling edge of NMI input 1 An interrupt is requested at the rising edge of NMI input Interrupt Control Mode 1 and 0 INTM1 INTM0 0 1 0 1 0 1 MAC Saturation 0 Non-saturating calculation for MAC instruction 1 Saturating calculation for MAC instruction Interrupt Control Mode 0 2 Description Control of interrupts by I bit Setting prohibited Control of interrupts by I2 to I0 bits and IPR Setting prohibited Rev. 6.00 Feb 22, 2005 page 1340 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register SCKCR--System Clock Control Register Bit Initial value Read/Write 7 PSTOP 0 R/W 6 0 5 0 4 0 3 H'FDE6 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W System STCS 0 R/W System Clock Select 0 0 1 1 0 0 Bus master in high-speed mode 1 Medium-speed clock is /2 0 Medium-speed clock is /4 1 Medium-speed clock is /8 0 Medium-speed clock is /16 1 Medium-speed clock is /32 1 Frequency Multiplication Factor Switching Mode Select 0 Specified multiplication factor is valid after transition to software standby mode, watch mode*, or subactive mode* 1 Specified multiplication factor is valid immediately after STC bits are rewritten Clock Output Disable DDR PSTOP Hardware standby mode Software standby mode, watch mode*, and direct transition Sleep mode and subsleep mode* High-speed mode, medium-speed mode, and subactive mode* 0 High impedance High impedance 1 0 High impedance Fixed high 1 1 High impedance Fixed high Fixed high Fixed high High impedance output High impedance output Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used with the other versions. Rev. 6.00 Feb 22, 2005 page 1341 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MDCR--Mode Control Register Bit Initial value Read/Write 7 1 R/W 6 0 5 0 4 0 H'FDE7 3 0 2 MDS2 * R 1 MDS1 * R System 0 MDS0 * R Note: * Determined by pins MD2 to MD0. Mode Select 2 to 0 Indicate the input levels at pins MD2 to MD0 MSTPCRA--Module Stop Control Register A Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 1 R/W 4 1 R/W H'FDE8 3 1 R/W 2 1 R/W 1 1 R/W System 0 1 R/W MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Module Stop 0 1 Module stop mode is cleared Module stop mode is set MSTPCRB--Module Stop Control Register B Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FDE9 3 1 R/W 2 1 R/W 1 1 R/W System 0 1 R/W MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Module Stop 0 1 Module stop mode is cleared Module stop mode is set Rev. 6.00 Feb 22, 2005 page 1342 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register MSTPCRC--Module Stop Control Register C Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FDEA 3 1 R/W 2 1 R/W 1 1 R/W System 0 1 R/W MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Module Stop 0 1 Module stop mode is cleared Module stop mode is set PFCR--Pin Function Control Register Bit Initial value Read/Write 7 0 6 0 5 0 4 0 H'FDEB 3 AE3 1/0 R/W 2 AE2 1/0 R/W 1 AE1 1 R/W 0 System AE0 1/0 R/W Address Output Enable 3 to 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A8 to A23 address output disabled A8 address output enabled; A9 to A23 address output disabled A8, A9 address output enabled; A10 to A23 address output disabled A8 to A10 address output enabled; A11 to A23 address output disabled A8 to A11 address output enabled; A12 to A23 address output disabled A8 to A12 address output enabled; A13 to A23 address output disabled A8 to A13 address output enabled; A14 to A23 address output disabled A8 to A14 address output enabled; A15 to A23 address output disabled A8 to A15 address output enabled; A16 to A23 address output disabled A8 to A16 address output enabled; A17 to A23 address output disabled A8 to A17 address output enabled; A18 to A23 address output disabled A8 to A18 address output enabled; A19 to A23 address output disabled A8 to A19 address output enabled; A20 to A23 address output disabled A8 to A20 address output enabled; A21 to A23 address output disabled (Initial value*) A8 to A21 address output enabled; A22, A23 address output disabled A8 to A23 address output enabled Note: * In on-chip ROM-enabled expansion mode, bits AE3 to AE0 are initialized to B'0000. In on-chip ROM-disabled expansion mode, bits AE3 to AE0 are initialized to B'1101. Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to 1. Rev. 6.00 Feb 22, 2005 page 1343 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register LPWRCR--Low-Power Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FDEC 3 0 R/W 2 0 R/W 1 STC1 0 R/W x1 x2 x4 Setting prohibited System 0 STC0 0 R/W DTON*1 LSON*1 NESEL*1 SUBSTP*1 RFCUT*1 Frequency Multiplication Factor 0 1 0 1 0 1 Oscillation Circuit Feedback Resistance Control Bit 0 When the main clock is oscillating, sets the feedback resistance ON. When the main clock is stopped, sets the feedback resistance OFF Sets the feedback resistance OFF 1 Subclock Enable 0 1 Enables subclock generation Disables subclock generation Noise Elimination Sampling Frequency Select 0 1 Low-Speed ON Flag 0 * When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode* * When the SLEEP instruction is executed in sub-active mode, operation shifts to watch mode or shifts directly to high-speed mode * Operation shifts to high-speed mode when watch mode is cancelled * When the SLEEP instruction is executed in high-speed mode, operation shifts to watch mode or sub-active mode * When the SLEEP instruction is executed in sub-active mode, operation shifts to subsleep mode or watch mode * Operation shifts to sub-active mode when watch mode is cancelled Sampling using 1/32 x Sampling using 1/4 x 1 Note: * Always set high-speed mode when shifting to watch mode or sub-active mode. Direct Transition ON Flag 0 * When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode* * When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-sleep mode or watch mode * When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts directly to sub-active mode*, or shifts to sleep mode or software standby mode * When the SLEEP instruction is executed in sub-active mode, operation shifts directly to high-speed mode, or shifts to sub-sleep mode Note: * Always set high-speed mode when shifting to watch mode or sub-active mode. 1 Note: 1. Bits 7 to 3 in LPWRCR are valid in the U-mask and W-mask versions, and H8S/2635 Group; they are reserved bits in all other versions. See sections 23A.2.3, 23B.2.3, Low-Power Control Register (LPWRCR), for more information. Rev. 6.00 Feb 22, 2005 page 1344 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register BARA--Break Address Register A BARB--Break Address Register B Bit 31 ... ... 24 23 22 21 20 19 18 17 H'FE00 H'FE04 16 ... 7 6 5 4 3 2 1 PBC PBC 0 BAA BAA BAA BAA BAA BAA BAA BAA . . . BAA BAA BAA BAA BAA BAA BAA BAA 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 Read/Write Initial value Unde- . . . Unde- 0 ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fined fined . . . R/W R/W R/W R/W R/W R/W R/W R/W . . . R/W R/W R/W R/W R/W R/W R/W R/W Break Address 23 to 0 Specify the channel A or B break address Notes: 1. The bit configuration of BARB is the same as for BARA. 2. These registers are not available in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 1345 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register BCRA--Break Control Register A BCRB--Break Control Register B Bit Initial value Read/Write 7 CMFA 0 R/(W)* 6 CDA 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'FE08 H'FE09 2 0 R/W 1 0 R/W 0 BIEA 0 R/W PBC PBC BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 Break Interrupt Enable 0 PC break interrupts are disabled 1 PC break interrupts are enabled Break Condition Select 0 1 0 Instruction fetch is used as break condition 1 Data read cycle is used as break condition 0 Data write cycle is used as break condition 1 Data read/write cycle is used as break condition Break Address Mask Register 0 0 1 1 0 1 0 All BARA bits are unmasked and included in break conditions 1 BAA0 (lowest bit) is masked, and not included in break conditions 0 BAA1, BAA0 (lower 2 bits) are masked, and not included in break conditions 1 BAA2 to BAA0 (lower 3 bits) are masked, and not included in break conditions 0 BAA3 to BAA0 (lower 4 bits) are masked, and not included in break conditions 1 BAA7 to BAA0 (lower 8 bits) are masked, and not included in break conditions 0 BAA11 to BAA0 (lower 12 bits) are masked, and not included in break conditions 1 BAA15 to BAA0 (lower 16 bits) are masked, and not included in break conditions CPU Cycle/DTC Cycle Select A 0 PC break is performed when CPU is bus master 1 PC break is performed when CPU or DTC is bus master Condition Match Flag A 0 [Clearing condition] * When 0 is written to CMFA after reading CMFA = 1 1 [Setting condition] * When a condition set for channel A is satisfied Notes: 1. The bit configuration of BCRB is the same as for BCRA. 2. These registers are not available in the H8S/2635 and H8S/2634. * Only a 0 may be written to this bit to clear the flag. Rev. 6.00 Feb 22, 2005 page 1346 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register ISCRH--IRQ Sence Control Register H ISCRL--IRQ Sence Control Register L ISCRH Bit Initial value Read/Write 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W H'FE12 H'FE13 Interrupt Controller Interrupt Controller 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA ISCRL Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA IRQ5 to IRQ0 sense control A and B IRQ5SCB to IRQ0SCB 0 IRQ5SCA to IRQ0SCA 0 1 Description Interrupt request generated at IRQ5 to IRQ0 input at low level Interrupt request generated at falling edge of IRQ5 to IRQ0 input Interrupt request generated at rising edge of IRQ5 to IRQ0 input Interrupt request generated at both falling and rising edges of IRQ5 to IRQ0 input 1 0 1 Rev. 6.00 Feb 22, 2005 page 1347 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register IER--IRQ Enable Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W H'FE14 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W Interrupt Controller 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W IRQ5 to IRQ0 Enable 0 1 IRQn interrupts disabled IRQn interrupts enabled (n = 5 to 0) ISR--IRQ Status Register Bit Initial value Read/Write 7 0 R/(W)* 6 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* H'FE15 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* Interrupt Controller 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* IRQ5 to IRQ0 Flags 0 [Clearing conditions] * Cleared by reading IRQnF when set to 1, then writing 0 in IRQnF * When interrupt exception handling is executed while low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high * When IRQn interrupt exception handling is executed while falling, rising, or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1) * When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 [Setting conditions] * When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA = 0) * When a falling edge occurs in IRQn input while falling edge detection is set (IRQnSCB = 0, IRQnSCA = 1) * When a rising edge occurs in IRQn input while rising edge detection is set (IRQnSCB = 1, IRQnSCA = 0) * When a falling or rising edge occurs in IRQn input while both-edge detection is set (IRQnSCB = IRQnSCA = 1) (n = 5 to 0) Note: * Only 0 can be written, to clear the flag. 1 Rev. 6.00 Feb 22, 2005 page 1348 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register DTCERA--DTC Enable Register A DTCERB--DTC Enable Register B DTCERC--DTC Enable Register C DTCERD--DTC Enable Register D DTCERE--DTC Enable Register E DTCERF--DTC Enable Register F DTCERG--DTC Enable Register G H'FE16 H'FE17 H'FE18 H'FE19 H'FE1A H'FE1B H'FE1C DTC DTC DTC DTC DTC DTC DTC Note: These registers are not available in the H8S/2635 and H8S/2634. Bit Initial value Read/Write 7 DTCE7 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 DTCE4 0 R/W 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTCE0 0 R/W DTC Activation Enable 0 DTC activation by interrupt is disabled [Clearing conditions] * When data transfer ends with the DISEL bit set to 1 * When the specified number of transfers end DTC activation by interrupt is enabled [Holding condition] * When the DISEL bit is 0 and the specified number of transfers have not ended 1 Rev. 6.00 Feb 22, 2005 page 1349 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register DTVECR--DTC Vector Register Bit Initial value Read/Write 7 0 R/(W)*1 6 0 R/W*2 5 0 R/W*2 4 0 H'FE1F 3 0 R/W*2 2 0 R/W*2 1 0 R/W*2 0 0 DTC SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 R/W*2 R/W*2 Set vector number for DTC software activation DTC Software Activation Enable 0 DTC software activation is disabled [Clearing conditions] * When the DISEL bit is 0 and the specified number of transfers have not ended * When 0 is written to DISEL bit after a software-activated data transfer end interrupt (SWDTEND) request has been sent to the CPU. DTC software activation is enabled [Holding conditions] * When data transfer ends with the DISEL bit set to 1 * When the specified number of transfers end * During software-activated deta transfer 1 Notes: This register is not available in the H8S/2635 and H8S/2634. 1. Only 1 can be written to the SWDTE bit. 2. Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0. Rev. 6.00 Feb 22, 2005 page 1350 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register PCR--PPG Output Control Register Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 H'FE26 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W PPG G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 R/W Group 0 Compare Match Select 0 1 0 Compare match in TPU channel 0 1 Compare match in TPU channel 1 0 Compare match in TPU channel 2 1 Compare match in TPU channel 3 Group 1 Compare Match Select 0 1 0 Compare match in TPU channel 0 1 Compare match in TPU channel 1 0 Compare match in TPU channel 2 1 Compare match in TPU channel 3 Group 2 Compare Match Select 0 1 0 Compare match in TPU channel 0 1 Compare match in TPU channel 1 0 Compare match in TPU channel 2 1 Compare match in TPU channel 3 Group 3 Compare Match Select 0 1 0 Compare match in TPU channel 0 1 Compare match in TPU channel 1 0 Compare match in TPU channel 2 1 Compare match in TPU channel 3 Note: This register is not available in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 1351 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register PMR--PPG Output Mode Register Bit Initial value Read/Write 7 G3INV 1 R/W 6 G2INV 1 R/W 5 G1INV 1 R/W 4 H'FE27 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PPG G0INV 1 R/W G3NOV G2NOV G1NOV G0NOV Group 0 Non-Overlap 0 Normal operation in pulse output group 0 (output values updated at compare match A in the selected TPU channel) Non-overlapping operation in pulse output group 0 (independent 1 and 0 output at compare match A or B in the selected TPU channel) 1 Group 1 Non-Overlap 0 Normal operation in pulse output group 1 (output values updated at compare match A in the selected TPU channel) Non-overlapping operation in pulse output group 1 (independent 1 and 0 output at compare match A or B in the selected TPU channel) 1 Group 2 Non-Overlap 0 Normal operation in pulse output group 2 (output values updated at compare match A in the selected TPU channel) Non-overlapping operation in pulse output group 2 (independent 1 and 0 output at compare match A or B in the selected TPU channel) 1 Group 3 Non-Overlap 0 Normal operation in pulse output group 3 (output values updated at compare match A in the selected TPU channel) Non-overlapping operation in pulse output group 3 (independent 1 and 0 output at compare match A or B in the selected TPU channel) 1 Group 0 Inversion 0 1 Inverted output for pulse output group 0 (low-level output at pin for a 1 in PODRL) Direct output for pulse output group 0 (high-level output at pin for a 1 in PODRL) Group 1 Inversion 0 1 Inverted output for pulse output group 1 (low-level output at pin for a 1 in PODRL) Direct output for pulse output group 1 (high-level output at pin for a 1 in PODRL) Group 2 Inversion 0 1 Inverted output for pulse output group 2 (low-level output at pin for a 1 in PODRH) Direct output for pulse output group 2 (high-level output at pin for a 1 in PODRH) Group 3 Inversion 0 1 Inverted output for pulse output group 3 (low-level output at pin for a 1 in PODRH) Direct output for pulse output group 3 (high-level output at pin for a 1 in PODRH) Note: This register is not available in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 1352 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register NDERH--Next Data Enable Register H Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE28 3 0 R/W 2 0 R/W 1 0 R/W 0 NDER8 0 R/W PPG NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 Next Data Enable 0 1 Pulse outputs PO15 to PO8 are disabled (NDR15 to NDR8 are not transferred to POD15 to POD8) Pulse outputs PO15 to PO8 are enabled (NDR15 to NDR8 are transferred to POD15 to POD8) Note: This register is not available in the H8S/2635 and H8S/2634. NDERL--Next Data Enable Register L Bit Initial value Read/Write 7 NDER7 0 R/W 6 NDER6 0 R/W 5 NDER5 0 R/W 4 NDER4 0 R/W H'FE29 3 NDER3 0 R/W 2 NDER2 0 R/W 1 NDER1 0 R/W 0 NDER0 0 R/W PPG Next Data Enable 0 1 Pulse outputs PO7 to PO0 are disabled (NDR7 to NDR0 are not transferred to POD7 to POD0 Pulse outputs PO7 to PO0 are enabled (NDR7 to NDR0 are transferred to POD7 to POD0) Note: This register is not available in the H8S/2635 and H8S/2634. PODRH--Output Data Register H Bit Initial value Read/Write 7 POD15 0 R/(W)* 6 POD14 0 R/(W)* 5 POD13 0 R/(W)* 4 POD12 0 R/(W)* H'FE2A 3 POD11 0 R/(W)* 2 POD10 0 R/(W)* 1 POD9 0 R/(W)* 0 POD8 0 R/(W)* PPG Notes: This register is not available in the H8S/2635 and H8S/2634. * A bit that has been set for pulse output by NDER is read-only. Rev. 6.00 Feb 22, 2005 page 1353 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register PODRL--Output Data Register L Bit Initial value Read/Write 7 POD7 0 R/(W)* 6 POD6 0 R/(W)* 5 POD5 0 R/(W)* 4 POD4 0 R/(W)* H'FE2B 3 POD3 0 R/(W)* 2 POD2 0 R/(W)* 1 POD1 0 R/(W)* 0 POD0 0 R/(W)* PPG Notes: This register is not available in the H8S/2635 and H8S/2634. * A bit that has been set for pulse output by NDER is read-only. Rev. 6.00 Feb 22, 2005 page 1354 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register NDRH--Next Data Register H Same Trigger for Pulse Output Groups Address H'FE2C Bit Initial value Read/Write 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 H'FE2C, H'FE2E PPG 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W NDR12 0 R/W Address H'FE2E Bit Initial value Read/Write 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Different Triggers for Pulse Output Groups Address H'FE2C Bit Initial value Read/Write 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 1 2 1 1 1 0 1 Address H'FE2E Bit Initial value Read/Write 7 1 6 1 5 1 4 1 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Notes: 1. For details, see section 11.2.4, Notes on NDR Access. 2. This register is not available in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 1355 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register NDRL--Next Data Register L Same Trigger for Pulse Output Groups Address H'FE2D Bit Initial value Read/Write 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 H'FE2D, H'FE2F PPG 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W NDR4 0 R/W Address H'FE2F Bit Initial value Read/Write 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Different Triggers for Pulse Output Groups Address H'FE2D Bit Initial value Read/Write 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 1 2 1 1 1 0 1 Address H'FE2F Bit Initial value Read/Write 7 1 6 1 5 1 4 1 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Notes: 1. For details, see section 11.2.4, Notes on NDR Access. 2. This register is not available in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 1356 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register P1DDR--Port 1 Data Direction Register Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W H'FE30 3 0 W 2 0 W 1 0 W 0 0 W Port P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Specify input or output for each of the pins in port 1 P3DDR--Port 3 Data Direction Register Bit Initial value Read/Write 7 6 5 0 W 4 0 W H'FE32 3 0 W 2 0 W 1 0 W 0 0 W Port P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Undefined Undefined Specify input or output for each of the pins in port 3 PADDR--Port A Data Direction Register Bit Initial value Read/Write 7 6 5 4 H'FE39 3 0 W 2 0 W 1 0 W 0 0 W Port PA3DDR PA2DDR PA1DDR PA0DDR Undefined Undefined Undefined Undefined Specify input or output for each of the pins in port A PBDDR--Port B Data Direction Register Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W H'FE3A 3 0 W 2 0 W 1 0 W 0 0 W Port PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Specify input or output for each of the pins in port B Rev. 6.00 Feb 22, 2005 page 1357 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register PCDDR--Port C Data Direction Register Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W H'FE3B 3 0 W 2 0 W 1 0 W 0 0 W Port PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Specify input or output for each of the pins in port C PDDDR--Port D Data Direction Register Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W H'FE3C 3 0 W 2 0 W 1 0 W 0 0 W Port PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Specify input or output for each of the pins in port D PEDDR--Port E Data Direction Register Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W H'FE3D 3 0 W 2 0 W 1 0 W 0 0 W Port PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Specify input or output for each of the pins in port E Rev. 6.00 Feb 22, 2005 page 1358 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register PFDDR--Port F Data Direction Register Bit Modes 4, 5, 6 Initial value Read/Write Mode 7 Initial value Read/Write 0 W 0 W 0 W 0 W 1 W 0 W 0 W 0 W 7 6 5 4 H'FE3E 3 2 1 0 Port PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR 0 W 0 W PF0DDR 0 W 0 W Undefined Undefined Undefined Undefined Specify input or output for each of the pins in port F PAPCR--Port A MOS Pull-Up Control Register Bit Initial value Read/Write 7 6 5 4 H'FE40 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port PA3PCR PA2PCR PA1PCR PA0PCR Undefined Undefined Undefined Undefined Control the MOS input pull-up function incorporated into port A PBPCR--Port B MOS Pull-Up Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE41 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Control the MOS input pull-up function incorporated into port B PCPCR--Port C MOS Pull-Up Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE42 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Control the MOS input pull-up function incorporated into port C Rev. 6.00 Feb 22, 2005 page 1359 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register PDPCR--Port D MOS Pull-Up Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE43 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Control the MOS input pull-up function incorporated into port D PEPCR--Port E MOS Pull-Up Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE44 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Control the MOS input pull-up function incorporated into port E P3ODR--Port 3 Open Drain Control Register Bit Initial value Read/Write 7 6 5 0 R/W 4 0 R/W H'FE46 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR Undefined Undefined PAODR--Port A Open Drain Control Register Bit Initial value Read/Write 7 6 5 4 H'FE47 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port PA3ODR PA2ODR PA1ODR PA0ODR Undefined Undefined Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1360 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register PBODR--Port B Open Drain Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE48 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR PCODR--Port C Open Drain Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE49 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR Rev. 6.00 Feb 22, 2005 page 1361 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TCR3--Timer Control Register 3 Bit Initial value Read/Write 7 CCLR2 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W H'FE80 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W TPU3 Time Prescaler 0 0 1 1 0 1 0 Internal clock: counts on /1 1 Internal clock: counts on /4 0 Internal clock: counts on /16 1 Internal clock: counts on /64 0 External clock: counts on TCLKA pin input 1 Internal clock: counts on /1024 0 Internal clock: counts on /256 1 Internal clock: counts on /4096 Clock Edge 0 0 Count at rising edge 1 Count at falling edge 1 Count at both edges Note: Internal clock edge selection is valid when the input clock is /4 or slower. This setting is ignored if the input clock is /1, or when overflow/underflow of another channel is selected. Counter Clear 0 0 1 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 1 0 1 0 TCNT clearing disabled 1 TCNT cleared by TGRC compare match/input capture*2 0 TCNT cleared by TGRD compare match/input capture*2 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Rev. 6.00 Feb 22, 2005 page 1362 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TMDR3--Timer Mode Register 3 Bit Initial value Read/Write 7 1 6 1 5 BFB 0 R/W 4 BFA 0 R/W H'FE81 3 MD3 0 R/W Mode 0 0 0 1 1 0 1 1 * * 0 1 0 1 0 1 0 1 * Normal operation Reserved PWM mode 1 PWM mode 2 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W TPU3 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 *: Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channel 3. In this case, 0 should always be written to MD2. Buffer Operation A 0 1 TGRA operates normally TGRA and TGRC used together for buffer operation Buffer Operation 0 1 TGRB operates normally TGRB and TGRD used together for buffer operation Rev. 6.00 Feb 22, 2005 page 1363 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TIOR3H--Timer I/O Control Register 3H Bit Initial value Read/Write 7 IOB3 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'FE82 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 TPU3 IOA0 0 R/W TGR3A I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR3A is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR3A is 1 input capture * register * Capture input source is TIOCA3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT4 count-up/ source is channel count-down 4/count clock *: Don't care TGR3B I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR3B is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR3B is 1 input capture * register * Capture input source is TIOCB3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at TCNT4 count-up/ Capture input source is channel count-down*1 4/count clock *: Don't care Note: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and /1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated. Rev. 6.00 Feb 22, 2005 page 1364 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TIOR3L--Timer I/O Control Register 3L Bit Initial value Read/Write 7 IOD3 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W H'FE83 3 IOC3 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W 0 IOC0 0 R/W TPU3 TGR3C I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR3C is Output disabled 1 output Initial output is 0 compare 0 register*1 output 1 0 1 0 1 0 TGR3C is 1 input capture * register*1 * Capture input source is TIOCC3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT4 count-up/ source is channel count-down 4/count clock *: Don't care Note: 1. When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. TGR3D I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR3D is Output disabled 1 output Initial output is 0 compare 0 register*2 output 1 0 1 0 1 0 TGR3D is 1 input capture * register*2 * Capture input source is TIOCD3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT4 count-up/ source is channel count-down*1 4/count clock *: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and /1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. Rev. 6.00 Feb 22, 2005 page 1365 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TIER3--Timer Interrupt Enable Register 3 Bit Initial value Read/Write 7 TTGE 0 R/W 6 1 5 0 4 TCIEV 0 R/W H'FE84 3 TGIED 0 R/W 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TPU3 TGIEA 0 R/W TGR Interrupt Enable A 0 1 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled TGR Interrupt Enable C 0 1 Interrupt requests (TGIC) by TGFC bit disabled Interrupt requests (TGIC) by TGFC bit enabled TGR Interrupt Enable D 0 1 Interrupt requests (TGID) by TGFD bit disabled Interrupt requests (TGID) by TGFD bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev. 6.00 Feb 22, 2005 page 1366 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TSR3--Timer Status Register 3 Bit Initial value Read/Write 7 1 6 1 5 0 4 TCFV 0 R/(W)* H'FE85 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU3 Input Capture/Output Compare Flag A 0 [Clearing conditions] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing conditions] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Input Capture/Output Compare Flag C 0 [Clearing conditions] * When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFC after reading TGFC = 1 [Setting conditions] * When TCNT = TGRC while TGRC is functioning as output compare register * When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register 1 Input Capture/Output Compare Flag D 0 [Clearing conditions] * When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFD after reading TGFD = 1 [Setting conditions] * When TCNT = TGRD while TGRD is functioning as output compare register * When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register 1 Overflow Flag 0 1 [Clearing condition] * When 0 is written to TCFV after reading TCFV = 1 [Setting condition] * When the TCNT value overflows (changes from H'FFFF to H'0000) Note: * Can only be written with 0 for flag clearing. Rev. 6.00 Feb 22, 2005 page 1367 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TCNT3--Timer Counter 3 Bit Initial value 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FE86 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU3 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TGR3A--Timer General Register 3A TGR3B--Timer General Register 3B TGR3C--Timer General Register 3C TGR3D--Timer General Register 3D Bit Initial value 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FE88 H'FE8A H'FE8C H'FE8E 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU3 TPU3 TPU3 TPU3 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 6.00 Feb 22, 2005 page 1368 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TCR4--Timer Control Register 4 Bit Initial value Read/Write 7 0 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W H'FE90 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPU4 TPSC0 0 R/W Time Prescaler 0 0 1 1 0 1 0 Internal clock: counts on /1 1 Internal clock: counts on /4 0 Internal clock: counts on /16 1 Internal clock: counts on /64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKC pin input 0 Internal clock: counts on /1024 1 Counts on TCNT5 overflow/underflow Note: This setting is ignored when channel 4 is in phase counting mode. Clock Edge 0 0 Count at rising edge 1 Count at falling edge 1 Count at both edges Note: This setting is ignored when channel 4 is in phase counting mode. Internal clock edge selection is valid when the input clock is /4 or slower. This setting is ignored if the input clock is /1, or when overflow/underflow of another channel is selected. Counter Clear 0 1 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. Rev. 6.00 Feb 22, 2005 page 1369 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TMDR4--Timer Mode Register 4 Bit Initial value Read/Write 7 1 6 1 5 1 4 1 H'FE91 3 MD3 0 R/W Mode 0 0 0 1 1 0 1 1 * * 0 1 0 1 0 1 0 1 * Normal operation Reserved PWM mode 1 PWM mode 2 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W TPU4 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 *: Don't care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev. 6.00 Feb 22, 2005 page 1370 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TIOR4--Timer I/O Control Register 4 Bit Initial value Read/Write 7 IOB3 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'FE92 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 TPU4 IOA0 0 R/W TGR4A I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR4A is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR4A is 1 input capture * register * Capture input source is TIOCA4 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at generation of TGR3A source is TGR3A compare match/input capture compare match/ input capture *: Don't care TGR4B I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR4B is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR4B is 1 input capture * register * Capture input source is TIOCB4 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at generation of TGR3C source is TGR3C compare match/input capture compare match/ input capture *: Don't care Rev. 6.00 Feb 22, 2005 page 1371 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TIER4--Timer Interrupt Enable Register 4 Bit Initial value Read/Write 7 TTGE 0 R/W H'FE94 4 TPU4 3/4 3/4 1 6 5 TCIEU 0 R/W TCIEV 0 R/W 3/4 3/4 0 3 3/4 3/4 0 2 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev. 6.00 Feb 22, 2005 page 1372 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TSR4--Timer Status Register 4 Bit Initial value Read/Write 7 TCFD 1 R 6 1 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* H'FE95 3 0 2 0 1 TGFB 0 R/(W)* 0 TPU4 TGFA 0 R/(W)* Input Capture/Output Compare Flag A 0 [Clearing conditions] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing conditions] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Overflow Flag 0 1 [Clearing condition] * When 0 is written to TCFV after reading TCFV = 1 [Setting condition] * When the TCNT value overflows (changes from H'FFFF to H'0000) Underflow Flag 0 1 [Clearing condition] * When 0 is written to TCFU after reading TCFU = 1 [Setting condition] * When the TCNT value underflows (changes from H'0000 to H'FFFF) Count Direction Flag 0 1 TCNT counts down TCNT counts up Note: * Can only be written with 0 for flag clearing. Rev. 6.00 Feb 22, 2005 page 1373 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TCNT4--Timer Counter 4 Bit Initial value Read/Write 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FE96 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU4 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. In other cases they function as up-counters. TGR4A--Timer General Register 4A TGR4B--Timer General Register 4B Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FE98 H'FE9A 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU4 TPU4 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 6.00 Feb 22, 2005 page 1374 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TCR5--Timer Control Register 5 Bit Initial value Read/Write 7 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W H'FEA0 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPU5 3/4 0 TPSC0 0 R/W 3/4 Time Prescaler 0 0 1 1 0 1 0 Internal clock: counts on f/1 1 Internal clock: counts on f/4 0 Internal clock: counts on f/16 1 Internal clock: counts on f/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKC pin input 0 Internal clock: counts on f/256 1 External clock: counts on TCLKD pin input Note: This setting is ignored when channel 5 is in phase counting mode. Clock Edge 0 1 0 Count at rising edge 1 Count at falling edge Count at both edges Note: This setting is ignored when channel 5 is in phase counting mode. Internal clock edge selection is valid when the input clock is f/4 or slower. This setting is ignored if the input clock is f/1, or when overflow/underflow of another channel is selected. Counter Clear 0 1 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. Rev. 6.00 Feb 22, 2005 page 1375 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TMDR5--Timer Mode Register 5 Bit Initial value Read/Write H'FEA1 TPU5 2 1 MD1 0 R/W 0 MD0 0 R/W 3/4 3/4 1 7 3/4 3/4 1 6 3/4 3/4 0 5 3/4 3/4 0 0 4 3 MD3 0 R/W Mode 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 * * * MD2 0 R/W Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 3/4 *: Don't care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev. 6.00 Feb 22, 2005 page 1376 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TIOR5--Timer I/O Control Register 5 Bit Initial value Read/Write 7 IOB3 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'FEA2 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 TPU5 IOA0 0 R/W TGR5A I/O Control 0 0 0 1 1 0 1 1 * 0 1 0 TGR5A is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR5A is Capture input source is 1 input capture TIOCA5 pin * register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care TGR5B I/O Control 0 0 0 1 1 0 1 1 * 0 1 0 TGR5B is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR5B is Capture input source is 1 input capture TIOCB5 pin * register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Rev. 6.00 Feb 22, 2005 page 1377 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TIER5--Timer Interrupt Enable Register 5 Bit Initial value Read/Write 7 TTGE 0 R/W H'FEA4 4 TPU5 3/4 3/4 1 6 5 TCIEU 0 R/W TCIEV 0 R/W 3/4 3/4 0 3 3/4 3/4 0 2 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev. 6.00 Feb 22, 2005 page 1378 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TSR5--Timer Status Register 5 Bit Initial value Read/Write 7 TCFD 1 R 6 1 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* H'FEA5 3 0 2 0 1 TGFB 0 R/(W)* 0 TPU5 TGFA 0 R/(W)* Input Capture/Output Compare Flag A 0 [Clearing conditions] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing conditions] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Overflow Flag 0 1 [Clearing condition] * When 0 is written to TCFV after reading TCFV = 1 [Setting condition] * When the TCNT value overflows (changes from H'FFFF to H'0000) Underflow Flag 0 1 [Clearing condition] * When 0 is written to TCFU after reading TCFU = 1 [Setting condition] * When the TCNT value underflows (changes from H'0000 to H'FFFF) Count Direction Flag 0 1 TCNT counts down TCNT counts up Note: * Can only be written with 0 for flag clearing. Rev. 6.00 Feb 22, 2005 page 1379 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TCNT5--Timer Counter 5 Bit Initial value Read/Write 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FEA6 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU5 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. In other cases they function as up-counters. TGR5A--Timer General Register 5A TGR5B--Timer General Register 5B Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FEA8 H'FEAA 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU5 TPU5 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TSTR--Timer Start Register Bit Initial value Read/Write H'FEB0 5 CST5 0 R/W 4 CST4 0 R/W 3 CST3 0 R/W 2 CST2 0 R/W 1 CST1 0 R/W 0 TPU 3/4 3/4 0 7 3/4 3/4 0 6 CST0 0 R/W Counter Start 0 1 TCNTn count operation is stopped TCNTn performs count operation (n = 5 to 0) Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. Rev. 6.00 Feb 22, 2005 page 1380 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TSYR--Timer Synchro Register Bit Initial value Read/Write 7 0 6 0 5 SYNC5 0 R/W 4 SYNC4 0 R/W H'FEB1 3 SYNC3 0 R/W 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 TPU SYNC0 0 R/W Timer Synchro 0 1 TCNTn operates independently (TCNT presetting/ clearing is unrelated to other channels) TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible (n = 5 to 0) Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. 2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. Rev. 6.00 Feb 22, 2005 page 1381 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register IPRA--Interrupt Priority Register A IPRB--Interrupt Priority Register B IPRC--Interrupt Priority Register C IPRD--Interrupt Priority Register D IPRE--Interrupt Priority Register E IPRF--Interrupt Priority Register F IPRG--Interrupt Priority Register G IPRH--Interrupt Priority Register H IPRJ--Interrupt Priority Register J IPRK--Interrupt Priority Register K IPRL--Interrupt Priority Register L IPRM--Interrupt Priority Register M Bit Initial value Read/Write 7 0 6 IPR6 1 R/W 5 IPR5 1 R/W 4 IPR4 1 R/W 3 H'FEC0 H'FEC1 H'FEC2 H'FEC3 H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC9 H'FECA H'FECB H'FECC 2 IPR2 1 R/W 1 IPR1 1 R/W 0 IPR0 1 R/W 0 INT INT INT INT INT INT INT INT INT INT INT INT Correspondence between Interrupt Sources and IPR Settings Register 6 to 4 IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRJ IPRK IPRL IPRM IRQ0 IRQ2 IRQ3 *1 Watchdog timer 0 PC break*3 TPU channel 0 TPU channel 2 TPU channel 4 *1 SCI channel 1 *1 PWM channel 1, 2, HCAN channel 1*3 Notes: 1. Reserved. Read-only bits, always read as 1. 2. I2C bus interface is available as an option in the H8S/2638, H8S/2639, H8S/2630. The IIC bit becomes reserved bit when this optional feature is not used. 3. The DTC, PC break, and HCAN1 are not implemented in the H8S/2635 and H8S/2634. IRQ1 IRQ4 IRQ5 DTC*3 *1 A/D converter, watchdog timer 1 TPU channel 1 TPU channel 3 TPU channel 5 SCI channel 0 SCI channel 2 IIC (Option)*2 HCAN channel 0 Bits 2 to 0 Rev. 6.00 Feb 22, 2005 page 1382 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register ABWCR--Bus Width Control Register Bit Modes 5 to 7 Initial value Read/Write Mode 4 Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 7 ABW7 6 ABW6 5 ABW5 4 ABW4 H'FED0 3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W 1 Bus Controller 0 ABW0 1 R/W 0 R/W ABW1 1 R/W 0 R/W Area 7 to 0 Bus Width Control 0 1 Area n is designated for 16-bit access Area n is designated for 8-bit access (n = 7 to 0) ASTCR--Access State Control Register Bit Initial value Read/Write 7 AST7 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W H'FED1 3 AST3 1 R/W 2 AST2 1 R/W 1 Bus Controller 0 AST0 1 R/W AST1 1 R/W Area 7 to 0 Access State Control 0 1 Area n is designated for 2-state access Wait state insertion in area n external space is disabled Area n is designated for 3-state access Wait state insertion in area n external space is enabled (n = 7 to 0) Rev. 6.00 Feb 22, 2005 page 1383 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register WCRH--Wait Control Register H Bit Initial value Read/Write 7 W71 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W H'FED2 3 W51 1 R/W 2 W50 1 R/W 1 W41 1 R/W Bus Controller 0 W40 1 R/W Area 4 Wait Control 1 and 0 0 0 Program wait not inserted when external space area 4 is accessed 1 1 program wait state inserted when external space area 4 is accessed 1 0 2 program wait states inserted when external space area 4 is accessed 1 3 program wait states inserted when external space area 4 is accessed Area 5 Wait Control 1 and 0 0 0 Program wait not inserted when external space area 5 is accessed 1 1 program wait state inserted when external space area 5 is accessed 1 0 2 program wait states inserted when external space area 5 is accessed 1 3 program wait states inserted when external space area 5 is accessed Area 6 Wait Control 1 and 0 0 0 Program wait not inserted when external space area 6 is accessed 1 1 program wait state inserted when external space area 6 is accessed 1 0 2 program wait states inserted when external space area 6 is accessed 1 3 program wait states inserted when external space area 6 is accessed Area 7 Wait Control 1 and 0 0 0 Program wait not inserted when external space area 7 is accessed 1 1 program wait state inserted when external space area 7 is accessed 1 0 2 program wait states inserted when external space area 7 is accessed 1 3 program wait states inserted when external space area 7 is accessed Rev. 6.00 Feb 22, 2005 page 1384 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register WCRL--Wait Control Register L Bit Initial value Read/Write 7 W31 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W H'FED3 3 W11 1 R/W 2 W10 1 R/W 1 W01 1 R/W Bus Controller 0 W00 1 R/W Area 0 Wait Control 1 and 0 0 0 Program wait not inserted when external space area 0 is accessed 1 1 program wait state inserted when external space area 0 is accessed 1 0 2 program wait states inserted when external space area 0 is accessed 1 3 program wait states inserted when external space area 0 is accessed Area 1 Wait Control 1 and 0 0 0 Program wait not inserted when external space area 1 is accessed 1 1 program wait state inserted when external space area 1 is accessed 1 0 2 program wait states inserted when external space area 1 is accessed 1 3 program wait states inserted when external space area 1 is accessed Area 2 Wait Control 1 and 0 0 0 Program wait not inserted when external space area 2 is accessed 1 1 program wait state inserted when external space area 2 is accessed 1 0 2 program wait states inserted when external space area 2 is accessed 1 3 program wait states inserted when external space area 2 is accessed Area 3 Wait Control 1 and 0 0 0 Program wait not inserted when external space area 3 is accessed 1 1 program wait state inserted when external space area 3 is accessed 1 0 2 program wait states inserted when external space area 3 is accessed 1 3 program wait states inserted when external space area 3 is accessed Rev. 6.00 Feb 22, 2005 page 1385 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register BCRH--Bus Control Register H Bit Initial value Read/Write 7 ICIS1 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W H'FED4 3 0 R/W Bus Controller BRSTRM BRSTS1 BRSTS0 3/4 0 R/W 2 3/4 0 R/W 1 3/4 0 R/W 0 Burst Cycle Select 0 0 1 Max. 4 words in burst access Max. 8 words in burst access Burst Cycle Select 1 0 1 Burst cycle comprises 1 state Burst cycle comprises 2 states Burst ROM Enable 0 1 Area 0 is basic bus interface Area 0 is burst ROM interface Idle Cycle Insert 0 0 1 Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles Idle Cycle Insert 1 0 1 Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas Rev. 6.00 Feb 22, 2005 page 1386 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register BCRL--Bus Control Register L Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 4 0 R/W H'FED5 3 1 R/W 2 0 R/W 1 Bus Controller 0 0 R/W WDBE 0 R/W Write Data Buffer Enable 0 1 Write data buffer function not used Write data buffer function used Rev. 6.00 Feb 22, 2005 page 1387 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register RAMER--RAM Emulation Register Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R/W 4 0 R/W H'FEDB 3 RAMS 0 R/W 2 RAM2 0 R/W 1 RAM1 0 R/W Flash Memory 0 RAM0 0 R/W Flash Memory Area Selection * H8S/2636 Addresses H'FFE000-H'FFE3FF H'000000-H'0003FF H'000400-H'0007FF H'000800-H'000BFF H'000C00-H'000FFF RAMS RAM2 RAM1 RAM0 Block Name * 0 * * RAM area 1 kB 0 1 0 EB0 (1 kB) 1 EB1 (1 kB) 1 0 EB2 (1 kB) 1 EB3 (1 kB) *: Don't care * H8S/2638, H8S/2639, H8S/2630 Addresses H'FFD000-H'FFDFFF H'000000-H'000FFF H'001000-H'001FFF H'002000-H'002FFF H'003000-H'003FFF H'004000-H'004FFF H'005000-H'005FFF H'006000-H'006FFF H'007000-H'007FFF * H8S/2635 Addresses H'FFD800-H'FFE7FF H'000000-H'000FFF H'001000-H'001FFF H'002000-H'002FFF H'003000-H'003FFF H'004000-H'004FFF H'005000-H'005FFF H'006000-H'006FFF H'007000-H'007FFF RAM Select 0 1 Emulation not selected Program/erase-protection of all flash memory blocks is disabled Emulation selected Program/erase-protection of all flash memory blocks is enabled Block Name RAM area 4 kB EB0 (4 kB) EB1 (4 kB) EB2 (4 kB) EB3 (4 kB) EB4 (4 kB) EB5 (4 kB) EB6 (4 kB) EB7 (4 kB) RAMS RAM2 RAM1 RAM0 0 * * * 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 *: Don't care Block Name RAM area 4 kB EB0 (4 kB) EB1 (4 kB) EB2 (4 kB) EB3 (4 kB) EB4 (4 kB) EB5 (4 kB) EB6 (4 kB) EB7 (4 kB) RAMS RAM2 RAM1 RAM0 0 * * * 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 *: Don't care Rev. 6.00 Feb 22, 2005 page 1388 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register P1DR--Port 1 Data Register Bit Initial value Read/Write 7 P17DR 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W 4 P14DR 0 R/W H'FF00 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 Port P10DR 0 R/W P3DR--Port 3 Data Register Bit Initial value Read/Write H'FF02 5 P35DR 0 R/W 4 P34DR 0 R/W 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 Port 3/4 3/4 7 7 3/4 3/4 6 6 P30DR 0 R/W Undefined Undefined PADR--Port A Data Register Bit Initial value Read/Write H'FF09 Port 2 PA2DR 0 R/W 1 PA1DR 0 R/W 0 PA0DR 0 R/W 3/4 3/4 7 PB7DR 0 R/W 3/4 3/4 6 PB6DR 0 R/W 3/4 3/4 5 PB5DR 0 R/W 5 3/4 3/4 4 PB4DR 0 R/W 4 3 PA3DR 0 R/W Undefined Undefined Undefined Undefined PBDR--Port B Data Register Bit Initial value Read/Write H'FF0A 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W 0 Port PB0DR 0 R/W PCDR--Port C Data Register Bit Initial value Read/Write 7 PC7DR 0 R/W 6 PC6DR 0 R/W 5 PC5DR 0 R/W 4 PC4DR 0 R/W H'FF0B 3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W 0 Port PC0DR 0 R/W Rev. 6.00 Feb 22, 2005 page 1389 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register PDDR--Port D Data Register Bit Initial value Read/Write 7 PD7DR 0 R/W 6 PD6DR 0 R/W 5 PD5DR 0 R/W 4 PD4DR 0 R/W H'FF0C 3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W 0 Port PD0DR 0 R/W PEDR--Port E Data Register Bit Initial value Read/Write 7 PE7DR 0 R/W 6 PE6DR 0 R/W 5 PE5DR 0 R/W 4 PE4DR 0 R/W H'FF0D 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W 0 Port PE0DR 0 R/W PFDR--Port F Data Register Bit Initial value Read/Write 7 PF7DR 0 R/W 6 PF6DR 0 R/W 5 PF5DR 0 R/W 4 PF4DR 0 R/W H'FF0E 3 PF3DR 0 R/W Port 3/4 3/4 2 3/4 3/4 1 0 PF0DR 0 R/W Undefined Undefined Rev. 6.00 Feb 22, 2005 page 1390 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TCR0--Timer Control Register 0 Bit Initial value Read/Write 7 CCLR2 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W H'FF10 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W TPU0 Time Prescaler 0 0 1 1 0 1 0 Internal clock: counts on /1 1 Internal clock: counts on /4 0 Internal clock: counts on /16 1 Internal clock: counts on /64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 External clock: counts on TCLKC pin input 1 External clock: counts on TCLKD pin input Clock Edge 0 0 Count at rising edge 1 Count at falling edge 1 Count at both edges Note: Internal clock edge selection is valid when the input clock is /4 or slower. This setting is ignored if the input clock is /1, or when overflow/underflow of another channel is selected. Counter Clear 0 0 1 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 1 0 1 0 TCNT clearing disabled 1 TCNT cleared by TGRC compare match/input capture*2 0 TCNT cleared by TGRD compare match/input capture*2 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Rev. 6.00 Feb 22, 2005 page 1391 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TMDR0--Timer Mode Register 0 Bit Initial value Read/Write H'FF11 5 BFB 0 R/W 4 BFA 0 R/W 3 MD3 0 R/W Mode 0 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W TPU0 3/4 3/4 1 7 3/4 3/4 1 6 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 3/4 *: Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channel 0. In this case, 0 should always be written to MD2. Buffer Operation A 0 1 TGRA operates normally TGRA and TGRC used together for buffer operation Buffer Operation 0 1 TGRB operates normally TGRB and TGRD used together for buffer operation Rev. 6.00 Feb 22, 2005 page 1392 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TIOR0H--Timer I/O Control Register 0H Bit Initial value Read/Write 7 IOB3 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'FF12 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 TPU0 IOA0 0 R/W TGR0A I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR0A is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR0A is 1 input capture * register * Capture input source is TIOCA0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT1 count-up/ source is channel count-down 1/count clock *: Don't care TGR0B I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR0B is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR0B is 1 input capture * register * Capture input source is TIOCB0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT1 count-up/ source is channel count-down*1 1/count clock *: Don't care Note: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and B/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. Rev. 6.00 Feb 22, 2005 page 1393 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TIOR0L--Timer I/O Control Register 0L Bit Initial value Read/Write 7 IOD3 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W H'FF13 3 IOC3 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W 0 IOC0 0 R/W TPU0 TGR0C I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR0C is Output disabled 1 output Initial output is 0 compare 0 register*1 output 1 0 1 0 1 0 TGR0C is 1 input capture * register*1 * Capture input source is TIOCC0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT1 count-up/ source is channel count-down 1/count clock *: Don't care Note: 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. TGR0D I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR0D is Output disabled 1 output Initial output is 0 compare 0 register*2 output 1 0 1 0 1 0 TGR0D is 1 input capture * register*2 * Capture input source is TIOCD0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT1 count-up/ source is channel count-down*1 1/count clock *: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and /1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. Rev. 6.00 Feb 22, 2005 page 1394 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TIER0--Timer Interrupt Enable Register 0 Bit Initial value Read/Write 7 TTGE 0 R/W H'FF14 4 TCIEV 0 R/W 3 TGIED 0 R/W 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TPU0 3/4 3/4 1 6 3/4 3/4 0 5 TGIEA 0 R/W TGR Interrupt Enable A 0 1 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled TGR Interrupt Enable C 0 1 Interrupt requests (TGIC) by TGFC bit disabled Interrupt requests (TGIC) by TGFC bit enabled TGR Interrupt Enable D 0 1 Interrupt requests (TGID) by TGFD bit disabled Interrupt requests (TGID) by TGFD bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev. 6.00 Feb 22, 2005 page 1395 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TSR0--Timer Status Register 0 Bit Initial value Read/Write 7 1 6 1 5 0 4 TCFV 0 R/(W)* H'FF15 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU0 Input Capture/Output Compare Flag A 0 [Clearing conditions] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing conditions] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Input Capture/Output Compare Flag C 0 [Clearing conditions] * When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFC after reading TGFC = 1 [Setting conditions] * When TCNT = TGRC while TGRC is functioning as output compare register * When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register 1 Input Capture/Output Compare Flag D 0 [Clearing conditions] * When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFD after reading TGFD = 1 [Setting conditions] * When TCNT = TGRD while TGRD is functioning as output compare register * When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register 1 Overflow Flag 0 1 [Clearing condition] * When 0 is written to TCFV after reading TCFV = 1 [Setting condition] * When the TCNT value overflows (changes from H'FFFF to H'0000) Note: * Can only be written with 0 for flag clearing. Rev. 6.00 Feb 22, 2005 page 1396 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TCNT0--Timer Counter 0 Bit Initial value 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FF16 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TGR0A--Timer General Register 0A TGR0B--Timer General Register 0B TGR0C--Timer General Register 0C TGR0D--Timer General Register 0D Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FF18 H'FF1A H'FF1C H'FF1E 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU0 TPU0 TPU0 TPU0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 6.00 Feb 22, 2005 page 1397 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TCR1--Timer Control Register 1 Bit Initial value Read/Write 7 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W H'FF20 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPU1 3/4 0 TPSC0 0 R/W 3/4 Time Prescaler 0 0 1 1 0 1 0 Internal clock: counts on f/1 1 Internal clock: counts on f/4 0 Internal clock: counts on f/16 1 Internal clock: counts on f/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 Internal clock: counts on f/256 1 Counts on TCNT2 overflow/underflow Note: This setting is ignored when channel 1 is in phase counting mode. Clock Edge 0 1 0 Count at rising edge 1 Count at falling edge Count at both edges 3/4 Note: This setting is ignored when channel 1 is in phase counting mode. Internal clock edge selection is valid when the input clock is f/4 or slower. This setting is ignored if the input clock is f/1, or when overflow/underflow of another channel is selected. Counter Clear 0 1 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. Rev. 6.00 Feb 22, 2005 page 1398 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TMDR1--Timer Mode Register 1 Bit Initial value Read/Write H'FF21 TPU1 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W 3/4 3/4 1 7 3/4 3/4 1 6 3/4 3/4 0 5 3/4 3/4 0 0 4 3 MD3 0 R/W Mode 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 3/4 *: Don't care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev. 6.00 Feb 22, 2005 page 1399 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TIOR1--Timer I/O Control Register 1 Bit Initial value Read/Write 7 IOB3 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'FF22 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 TPU1 IOA0 0 R/W TGR1A I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR1A is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR1A is 1 input capture * register * Capture input source is TIOCA1 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at generation of source is TGR0A channel 0/TGR0A compare match/ compare match/ input capture input capture *: Don't care TGR1B I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR1B is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR1B is 1 input capture * register * Capture input source is TIOCB1 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at generation of TGR0C source is TGR0C compare match/input capture compare match/ input capture *: Don't care Rev. 6.00 Feb 22, 2005 page 1400 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TIER1--Timer Interrupt Enable Register 1 Bit Initial value Read/Write 7 TTGE 0 R/W H'FF24 4 TPU1 3/4 3/4 1 6 5 TCIEU 0 R/W TCIEV 0 R/W 3/4 3/4 0 3 3/4 3/4 0 2 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev. 6.00 Feb 22, 2005 page 1401 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TSR1--Timer Status Register 1 Bit Initial value Read/Write 7 TCFD 1 R 6 1 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* H'FF25 3 0 2 0 1 TGFB 0 R/(W)* 0 TPU1 TGFA 0 R/(W)* Input Capture/Output Compare Flag A 0 [Clearing conditions] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing conditions] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Overflow Flag 0 1 [Clearing condition] * When 0 is written to TCFV after reading TCFV = 1 [Setting condition] * When the TCNT value overflows (changes from H'FFFF to H'0000) Underflow Flag 0 1 [Clearing condition] * When 0 is written to TCFU after reading TCFU = 1 [Setting condition] * When the TCNT value underflows (changes from H'0000 to H'FFFF) Count Direction Flag 0 1 TCNT counts down TCNT counts up Note: * Can only be written with 0 for flag clearing. Rev. 6.00 Feb 22, 2005 page 1402 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TCNT1--Timer Counter 1 Bit Initial value Read/Write 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FF26 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU1 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. In other cases they function as up-counters. TGR1A--Timer General Register 1A TGR1B--Timer General Register 1B Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FF28 H'FF2A 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU1 TPU1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 6.00 Feb 22, 2005 page 1403 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TCR2--Timer Control Register 2 Bit Initial value Read/Write 7 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W H'FF30 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPU2 3/4 0 TPSC0 0 R/W 3/4 Time Prescaler 0 0 1 1 0 1 0 Internal clock: counts on f/1 1 Internal clock: counts on f/4 0 Internal clock: counts on f/16 1 Internal clock: counts on f/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 External clock: counts on TCLKC pin input 1 Internal clock: counts on f/1024 Note: This setting is ignored when channel 2 is in phase counting mode. Clock Edge 0 1 0 Count at rising edge 1 Count at falling edge Count at both edges 3/4 Note: This setting is ignored when channel 2 is in phase counting mode. Internal clock edge selection is valid when the input clock is f/4 or slower. This setting is ignored if the input clock is f/1, or when overflow/underflow of another channel is selected. Counter Clear 0 1 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. Rev. 6.00 Feb 22, 2005 page 1404 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TMDR2--Timer Mode Register 2 Bit Initial value Read/Write H'FF31 TPU2 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W 3/4 3/4 1 7 3/4 3/4 1 6 3/4 3/4 0 5 3/4 3/4 0 0 4 3 MD3 0 R/W Mode 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 3/4 *: Don't care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev. 6.00 Feb 22, 2005 page 1405 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TIOR2--Timer I/O Control Register 2 Bit Initial value Read/Write 7 IOB3 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'FF32 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 TPU2 IOA0 0 R/W TGR2A I/O Control 0 0 0 1 1 0 1 1 * 0 1 0 TGR2A is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR2A is Capture input source is 1 input capture TIOCA2 pin * register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care TGR2B I/O Control 0 0 0 1 1 0 1 1 * 0 1 0 TGR2B is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR2B is Capture input source is 1 input capture TIOCB2 pin * register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Rev. 6.00 Feb 22, 2005 page 1406 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TIER2--Timer Interrupt Enable Register 2 Bit Initial value Read/Write 7 TTGE 0 R/W H'FF34 4 TPU2 3/4 3/4 1 6 5 TCIEU 0 R/W TCIEV 0 R/W 3/4 3/4 0 3 3/4 3/4 0 2 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev. 6.00 Feb 22, 2005 page 1407 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TSR2--Timer Status Register 2 Bit Initial value Read/Write 7 TCFD 1 R 6 1 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* H'FF35 3 0 2 0 1 TGFB 0 R/(W)* 0 TPU2 TGFA 0 R/(W)* Input Capture/Output Compare Flag A 0 [Clearing conditions] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing conditions] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Overflow Flag 0 1 [Clearing condition] * When 0 is written to TCFV after reading TCFV = 1 [Setting condition] * When the TCNT value overflows (changes from H'FFFF to H'0000) Underflow Flag 0 1 [Clearing condition] * When 0 is written to TCFU after reading TCFU = 1 [Setting condition] * When the TCNT value underflows (changes from H'0000 to H'FFFF) Count Direction Flag 0 1 TCNT counts down TCNT counts up Note: * Can only be written with 0 for flag clearing. Rev. 6.00 Feb 22, 2005 page 1408 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TCNT2--Timer Counter 2 Bit Initial value Read/Write 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FF36 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU2 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. In other cases they function as up-counters. TGR2A--Timer General Register 2A TGR2B--Timer General Register 2B Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FF38 H'FF3A 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU2 TPU2 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 6.00 Feb 22, 2005 page 1409 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TCSR0--Timer Control/Status Register 0 Bit Initial value Read/Write 7 OVF 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 1 H'FF74(W), H'FF74(R) 3 1 2 CKS2 0 R/W 1 CKS1 0 R/W 0 WDT0 CKS0 0 R/W Clock Select 2 to 0 CKS2 CKS1 CKS0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Clock /2 /64 /128 /512 /2048 /8192 /32768 /131072 Overflow Period* (where = 20 MHz) 25.6 s 819.2 s 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s Note: * An overflow period is the time interval between the start of counting up from H'00 on the TCNT and the occurrence of a TCNT overflow. Timer Enable 0 1 TCNT is initialized to H'00 and halted TCNT counts Timer Mode Select 0 1 Interval timer mode: WDT0 requests an interval timer interrupt (WOVI) from the CPU when the TCNT overflows Watchdog timer mode: A reset is issued when the TCNT overflows if the RSTE bit of RSTCSR is set to 1* Note: * For details see section 12.2.3, Reset Control/Status Register (RSTCSR). Overflow Flag 0 [Clearing conditions] * Write 0 in the TME bit (Only applies to WDT1) * Read TCSR* when OVF = 1, then write 0 in OVF [Setting condition] * When TCNT overflows (changes from H'FF to H'00) (When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset) 1 Note: * When interval timer interrupts are disabled and OVF is polled, read the OVF = 1 state at least twice. Notes: TCSR0 register differs from other registers in being more difficult to write to. For details see section 12.2.4, Notes on Register Access. * Only 0 can be written, to clear the flag. Rev. 6.00 Feb 22, 2005 page 1410 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TCNT0--Timer Counter 0 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FF74(W), H'FF75(R) 3 0 R/W 2 0 R/W 1 0 R/W 0 0 WDT0 R/W Up-counter Note: TCNT0 register differs from other registers in being more difficult to write to. For details see section 12.2.4, Notes on Register Access. RSTCSR--Reset Control/Status Register Bit Initial value Read/Write 7 WOVF 0 R/(W)* 6 RSTE 0 R/W 5 RSTS 0 R/W 4 0 H'FF76(W), H'FF77(R) 3 0 2 0 1 0 0 WDT0 0 Reset Select 0 1 Reset Enable 0 1 Reset signal is not generated if TCNT overflows* Reset signal is generated if TCNT overflows Reset Do not set Note: * The modules within the H8S/2646 are not reset, but TCNT and TCSR within the WDT are reset. Watchdog Overflow Flag 0 1 [Clearing condition] * Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF [Setting condition] * Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer operation Notes: RSTCSR register differs from other registers in being more difficult to write to. For details see section 12.2.4, Notes on Register Access. * Can only be written with 0 for flag clearing. Rev. 6.00 Feb 22, 2005 page 1411 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register SMR0--Serial Mode Register 0 SMR1--Serial Mode Register 1 SMR2--Serial Mode Register 2 Bit Initial value Read/Write 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF78 H'FF80 H'FF88 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SCI0 SCI1 SCI2 Clock Select 1 and 0 0 1 0 1 0 1 Multiprocessor Mode 0 1 Multiprocessor function disabled Multiprocessor format selected clock /4 clock /16 clock /64 clock Stop Bit Length 0 1 stop bit: In transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. 2 stop bits: In transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. 1 Parity Mode 0 1 Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled*2 Even parity*3 Odd parity*4 Character Length 0 1 8-bit data 7-bit data*1 Communication Mode 0 1 Asynchronous mode Synchronous mode Rev. 6.00 Feb 22, 2005 page 1412 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Notes: 1. When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible to choose between LSB-first or MSB-first transfer. 2. When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. 3. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 4. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. Rev. 6.00 Feb 22, 2005 page 1413 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register ICCR0--I2C Bus Control Register ICCR1--I2C Bus Control Register Bit : 7 ICE Initial value : R/W : 0 R/W 6 IEIC 0 R/W 5 MST 0 R/W 4 TRS 0 R/W 3 H'FF78 H'FF80 2 BBSY 0 R/W 1 IRIC 0 R/(W)* 0 SCP 0 R/W IIC0 IIC1 ACKE 0 R/W Start condition/stop condition prohibit 0 Writing 0 issues a start or stop condition, in combination with the BBSY flag 1 Reading always returns a value of 1 Writing is ignored I2C Bus interface interrupt request flag 0 1 Waiting for transfer, or transfer in progress Interrupt requested Note: * For details see section 15.2.5, I2C Bus Control Register. Bus busy 0 Bus is free [Clearing condition] * When a stop condition is detected Bus is free [Clearing condition] * When a stop condition is detected 1 Acknowledge bit judgement selection 0 1 The value of the acknowledge bit is ignored, and continuous transfer is performed If the acknowledge bit is 1, continuous transfer is interrupted Master/slave select, transmit/receive select 0 1 0 1 0 1 Slave receive mode Slave transmit mode Master receive mode Master transmit mode Note: * For details see section 15.2.5, I2C Bus Control Register. I2C Bus Interface Interrupt Enable 0 1 Interrupts disabled Interrupts enabled I2C Bus Interface Enable 0 1 I2C bus interface module disabled, with SCL and SDA signal pins set to port function I2C bus interface module internal states initialized SAR and SARX can be accessed I2C bus interface module enabled for transfer operations (pins SCL and SCA are driving the bus) ICMR and ICDR can be accessed Notes: This register is valid only on the H8S/2638, H8S/2639, or H8S/2630 with the I2C bus interface option added. * Only 0 can be written, for flag clearing. Rev. 6.00 Feb 22, 2005 page 1414 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register SMR0--Serial Mode Register 0 SMR1--Serial Mode Register 1 SMR2--Serial Mode Register 2 Bit Initial value Read/Write 7 GM 0 R/W 6 BLK 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF78 H'FF80 H'FF88 3 BCP1 0 R/W 2 BCP0 0 R/W Smart Card Interface 0 Smart Card Interface 1 Smart Card Interface 2 1 CKS1 0 R/W 0 CKS0 0 R/W Clock Select 1 and 0 0 1 0 1 0 1 clock /4 clock /16 clock /64 clock Basic Clock Pulse 0 1 0 1 0 1 Parity Mode 0 1 Parity Enable 0 1 Block Transfer Mode 0 Normal Smart Card interface mode operation * Error signal transmission/detection and automatic data retransmission performed * TXI interrupt generated by TEND flag * TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode) Block transfer mode operation * Error signal transmission/detection and automatic data retransmission not performed * TXI interrupt generated by TDRE flag * TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode) Parity bit addition and checking disabled Parity bit addition and checking enabled*1 Even parity*2 Odd parity*3 32 clock periods 64 clock periods 372 clock periods 256 clock periods 1 Note: etu: Elementary Time Unit (time for transfer of 1 bit) GSM Mode 0 Normal smart card interface mode operation * TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit * Clock output ON/OFF control only GSM mode smart card interface mode operation * TEND flag generation 11.0 etu after beginning of start bit * High/Low fixing control possible in addition to clock output ON/OFF control (set by SCR) 1 Note: etu: Elementary Time Unit (time for transfer of 1 bit) Rev. 6.00 Feb 22, 2005 page 1415 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Notes: When the smart card interface is used, be sure to make the 1 setting shown for bit 5. 1. When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. 2. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 3. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. Rev. 6.00 Feb 22, 2005 page 1416 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register BRR0--Bit Rate Register 0 Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W H'FF79 4 1 R/W 3 1 R/W SCI0, Smart Card Interface 0 2 1 R/W 1 1 R/W 0 1 R/W Set the serial transmit/receive bit rate Note: For details see section 13.2.8, Bit Rate Register (BRR). Rev. 6.00 Feb 22, 2005 page 1417 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register ICSR0--I2C Bus Status Register ICSR1--I2C Bus Status Register Bit : 7 ESTP Initial value : R/W : 0 R/(W)* 6 STOP 0 R/(W)* 5 IRTR 0 R/(W)* 4 AASX 0 R/(W)* 3 AL 0 R/(W)* 2 AAS 0 R/(W)* 1 ADZ 0 H'FF79 H'FF81 0 ACKB 0 R/W IIC0 IIC1 R/(W)* Acknowledge bit 0 When receiving, 0 is output at acknowledge output timing. When transmitting, this bit shows that an acknowledge (0) has not been sent from the receiving device. When receiving, 1 is output at acknowledge output timing. When transmitting, this bit shows that an acknowledge (1) has been sent from the receiving device. 1 General call address confirmation flag 0 General call address not confirmed [Clearings] (1) When data is written to ICDR (when sending), or when data is read from ICDR (when receiving); (2) When 0 is written after reading ADZ=1; (3) In master mode. General call address confirmation [Setting] * When general call address is detected is in slave receive mode and FSX = 0 or FS = 0). 1 Slave address confirmation flag 0 Slave address or general call address not confirmed [Clearings] (1) When data is written to ICDR (when sending), or when data is read from ICDR (when receiving); (2) When 0 is written after reading AAS=1; (3) In master mode. Slave address or general call address confirmed [Setting] * When slave address or general call address is detected in slave receive mode and FS = 0. 1 Arbitration lost flag 0 Secure bus. [Clearings] (1) When data is written to ICDR (when sending), or when data is read (when receiving); (2) When 0 is written after reading AL=1. Bus arbitration lost [Settings] (1) When there is a mismatch between internal SDA and SDA pin at rise in SCL in master transmit mode; (2) When the internal SCL level is HIGH at the fall in SCL in master transmit mode. 1 2nd slave address confirmation flag 0 2nd slave address not confirmed [Clearings] (1) When 0 is written after reading AASX=1; (2) When start conditions are detected; (3) In master mode. 2nd slave address confirmed [Setting] * When 2nd slave address is detected in slave receive mode and FSX = 0. 1 I2C bus interface continuous transmit and receive interrupt request flag 0 Transmit wait state, or transmitting [Clearings] (1) When 0 written after reading IRTR=1; (2) When IRIC flag is cleared to 0. Continuous transmit state [Settings] * In I2C bus interface slave mode When 1 is set in TDRE or RDRF flag when AASX=1. * In other than I2C bus interface slave mode When TDRE or RDRF flag is set to 1. 1 Normal end condition detection flag 0 No normal end condition [Clearings] (1) When 0 is written after reading STOP=1; (2) When IRIC flag is cleared to 0. Normal end condition detected in slave mode in I2C bus format [Setting] On detection of stop condition on completion of sending frame. * No meaning when in other than slave mode in I2C bus format 1 Error stop condition detection flag 0 No error stop condition [Clearings] (1) When 0 written after reading ESTP=1; (2) When IRIC flag is cleared to 0. * Error stop condition detected in slave mode in I2C bus format [Setting] On detection of stop condition while sending frame. * No meaning when in other than slave mode in I2C bus format 1 Notes: This register is valid only on the H8S/2638, H8S/2639, or H8S/2630 with the I2C bus interface option added. * Only 0 can be written to these bits (to clear these flags). Rev. 6.00 Feb 22, 2005 page 1418 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register SCR0--Serial Control Register 0 SCR1--Serial Control Register 1 SCR2--Serial Control Register 2 Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W H'FF7A H'FF82 H'FF8A 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W SCI0 SCI1 SCI2 Clock Enable 1 and 0 0 0 Asynchronous mode Internal clock/SCK pin functions as I/O port Clocked Internal clock/SCK pin synchronous mode functions as serial clock output 1 Asynchronous mode Internal clock/SCK pin functions as clock output*9 Clocked Internal clock/SCK pin synchronous mode functions as serial clock output 1 0 Asynchronous mode External clock/SCK pin functions as clock input*10 Clocked External clock/SCK pin synchronous mode functions as serial clock input 1 Asynchronous mode External clock/SCK pin functions as clock input*10 Clocked External clock/SCK pin synchronous mode functions as serial clock input Transmit End Interrupt Enable 0 1 Transmit-end interrupt (TEI) request disabled*8 Transmit-end interrupt (TEI) request enabled*8 Multiprocessor Interrupt Enable 0 Transmit Interrupt Enable 0 1 Transmit-data-empty interrupt (TXI) request disabled*1 Transmit-data-empty interrupt (TXI) request enabled 1 Multiprocessor interrupts disabled (normal reception mode) [Clearing conditions] * When the MPIE bit is cleared to 0 * When data with MPB = 1 is received Multiprocessor interrupts enabled*7 Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received Receive Interrupt Enable 0 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled*2 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled Receive Enable 0 1 Reception disabled*5 Reception enabled*6 1 Transmit Enable 0 1 Transmission disabled*3 Transmission enabled*4 Rev. 6.00 Feb 22, 2005 page 1419 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Notes: 1. TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. 2. RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0. 3. The TDRE flag in SSR is fixed at 1. 4. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transfer format before setting the TE bit to 1. 5. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 6. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the transfer format before setting the RE bit to 1. 7. When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR , is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. 8. TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0. 9. Outputs a clock of the same frequency as the bit rate. 10. Inputs a clock with a frequency 16 times the bit rate. Rev. 6.00 Feb 22, 2005 page 1420 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register SCR0--Serial Control Register 0 SCR1--Serial Control Register 1 SCR2--Serial Control Register 2 Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 H'FF7A H'FF82 H'FF8A 3 MPIE 0 R/W 2 TEIE 0 R/W Smart Card Interface 0 Smart Card Interface 1 Smart Card Interface 2 1 CKE1 0 R/W 0 CKE0 0 R/W RE 0 R/W Clock Enable 1 and 0 SCMR SMR SCR Setting CKE0 See the SCI 0 0 0 1 1 0 1 1 1 0 Operates as port I/O pin Outputs clock as SCK output pin Operates as SCK output pin, with output fixed low Outputs clock as SCK output pin Operates as SCK output pin, with output fixed high Outputs clock as SCK output pin SCK Pin Function SMIF C/), GM CKE1 0 1 Transmit End Interrupt Enable 0 1 Transmit-end interrupt (TEI) request disabled*8 Transmit-end interrupt (TEI) request enabled*8 Multiprocessor Interrupt Enable 0 Transmit Interrupt Enable 0 1 Transmit-data-empty interrupt (TXI) request disabled*1 Transmit-data-empty interrupt (TXI) request enabled 1 Multiprocessor interrupts disabled (normal reception mode) [Clearing conditions] * When the MPIE bit is cleared to 0 * When data with MPB = 1 is received Multiprocessor interrupts enabled*7 Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received Receive Interrupt Enable 0 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled*2 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled Receive Enable 0 1 Reception disabled*5 Reception enabled*6 1 Transmit Enable 0 1 Transmission disabled*3 Transmission enabled*4 Rev. 6.00 Feb 22, 2005 page 1421 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Notes: 1. TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. 2. RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0. 3. The TDRE flag in SSR is fixed at 1. 4. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transfer format before setting the TE bit to 1. 5. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 6. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the transfer format before setting the RE bit to 1. 7. When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR , is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. 8. TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0. TDR0--Transmit Data Register 0 Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W H'FF7B 4 1 R/W 3 1 R/W SCI0, Smart Card Interface 0 2 1 R/W 1 1 R/W 0 1 R/W Store serial transmit data Rev. 6.00 Feb 22, 2005 page 1422 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register SSR0--Serial Status Register 0 SSR1--Serial Status Register 1 SSR2--Serial Status Register 2 Bit Initial value Read/Write H'FF7C H'FF84 H'FF8C 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 0 1 SCI0 SCI1 SCI2 1 MPB 0 R 0 MPBT 0 R/W 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* Multiprocessor Bit Transfer Data with a 0 multi-processor bit is transmitted Data with a 1 multi-processor bit is transmitted Multiprocessor Bit 0 [Clearing condition] * When data with a 0 multiprocessor bit is received*7 [Setting condition] * When data with a 1 multiprocessor bit is received 1 Transmit End 0 [Clearing conditions] * When 0 is written in TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character 1 Parity Error 0 1 [Clearing condition] * When 0 is written in PER after reading PER = 1*5 [Setting condition] * When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR*6 Framing Error 0 1 [Clearing condition] * When 0 is written in FER after reading FER = 1*3 [Setting condition] * When the SCI checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0*4 Overrun Error 0 1 [Clearing condition] * When 0 is written in ORER after reading ORER = 1*1 [Setting condition] * When the next serial reception is completed while RDRF = 1*2 Receive Data Register Full 0 [Clearing conditions] * When 0 is written in RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR 1 Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Transmit Data Register Empty 0 [Clearing conditions] * When 0 is written in TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written in TDR 1 Rev. 6.00 Feb 22, 2005 page 1423 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Notes: * Only 0 can be written, to clear the flag. 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. 3. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 4. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. 5. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 6. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. 7. Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor format. Rev. 6.00 Feb 22, 2005 page 1424 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register SSR0--Serial Status Register 0 SSR1--Serial Status Register 1 SSR2--Serial Status Register 2 Bit Initial value Read/Write H'FF7C H'FF84 H'FF8C 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R Smart Card Interface 0 Smart Card Interface 1 Smart Card Interface 2 1 MPB 0 R 0 MPBT 0 R/W 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* Multiprocessor Bit Transfer 0 Transmit End 0 Transmission is in progress [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and write data to TDR Transmission has ended [Setting conditions] * Upon reset, and in standby mode or module stop mode * When the TE bit in SCR is 0 and the ERS bit is also 0 * When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 0 * When TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 1 * When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 0 * When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 1 1 Data with a 0 multi-processor bit is transmitted Data with a 1 multi-processor bit is transmitted Multiprocessor Bit 0 [Clearing condition] * When data with a 0 multiprocessor bit is received*5 [Setting condition] * When data with a 1 multiprocessor bit is received 1 1 Note: etu: Elementary Time Unit (time for transfer of 1 bit) Parity Error 0 1 [Clearing condition] * When 0 is written in PER after reading PER = 1*3 [Setting condition] * When, in reception, the number of 1 bits in the receive data plus the parity bit *4 does not match the parity setting (even or odd) specified by the O/E bit in SMR Error Signal Status 0 Normal reception, with no error signal [Clearing conditions] * Upon reset, and in standby mode or module stop mode * When 0 is written to ERS after reading ERS = 1 Error signal sent from receiver indicating detection of parity error [Setting condition] * When the low level of the error signal is sampled 1 Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state. Overrun Error 0 1 [Clearing condition] * When 0 is written in ORER after reading ORER = 1*1 [Setting condition] * When the next serial reception is completed while RDRF = 1*2 Receive Data Register Full 0 [Clearing conditions] * When 0 is written in RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR 1 Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Transmit Data Register Empty 0 [Clearing conditions] * When 0 is written in TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written in TDR 1 Rev. 6.00 Feb 22, 2005 page 1425 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register Notes: * Only 0 can be written, to clear the flag. 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. 3. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 4. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. 5. Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor format. RDR0--Receive Data Register 0 Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R H'FF7D 4 0 R 3 0 R SCI0, Smart Card Interface 0 2 0 R 1 0 R 0 0 R Store serial receive data Rev. 6.00 Feb 22, 2005 page 1426 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register SCMR0--Smart Card Mode Register 0 Bit Initial value Read/Write H'FF7E SCI0, Smart Card Interface 0 3 2 SINV 0 R/W 3/4 3/4 1 7 3/4 3/4 1 6 3/4 3/4 1 5 3/4 3/4 1 4 SDIR 0 R/W 3/4 3/4 1 1 0 SMIF 0 R/W Smart Card Interface Mode Select 0 1 Operates as normal SCI (smart card interface function disabled) Smart card interface function enabled Smart Card Interface Data Invert 0 1 TDR contents are transmitted without modification Receive data is stored in RDR without modification TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Smart Card Interface Data Transfer Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Rev. 6.00 Feb 22, 2005 page 1427 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register ICDR0--I2C Bus Data Register ICDR1--I2C Bus Data Register Bit : 7 ICDR7 Initial value : R/W ICDRR Bit : 7 6 5 4 3 : 6 ICDR6 5 ICDR5 4 ICDR4 3 H'FF7E H'FF86 2 ICDR2 1 ICDR1 0 ICDR0 IIC0 IIC1 3/4 3/4 3/4 3/4 ICDR3 3/4 3/4 2 3/4 1 3/4 0 R/W R/W R/W R/W R/W R/W R/W R/W ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0 Initial value : R/W ICDRS Bit : 7 6 5 4 3 2 1 0 ICDRS7 ICDRS6 ICDRS5 ICDRS4 ICDRS3 ICDRS2 ICDRS1 ICDRS0 Initial value : R/W ICDRT Bit : 7 6 5 4 3 2 1 0 ICDRT7 ICDRT6 ICDRT5 ICDRT4 ICDRT3 ICDRT2 ICDRT1 ICDRT0 Initial value : R/W : : : 3/4 R 3/4 R 3/4 R 3/4 R 3/4 R 3/4 R 3/4 R 3/4 R 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 W 3/4 W 3/4 W 3/4 W 3/4 W 3/4 W 3/4 W 3/4 W TDRE, RDRF (internal flag) Bit : 3/4 TDRE 3/4 RDRF Initial value : R/W : 3/4 0 3/4 0 Note: This register is valid only on the H8S/2638, H8S/2639, or H8S/2630 with the I2C bus interface option added. Rev. 6.00 Feb 22, 2005 page 1428 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register SARX0--2nd Slave Address Register SARX1--2nd Slave Address Register Bit : 7 SVAX6 Initial value : R/W : 0 R/W 6 SVAX5 0 R/W 5 SVAX4 0 R/W 4 SVAX3 0 R/W 2nd slave address H'FF7E H'FF86 3 SVAX2 0 R/W 2 SVAX1 0 R/W 1 SVAX0 0 R/W 0 FSX 1 R/W IIC0 IIC1 Format select X Note: This register is valid only on the H8S/2638, H8S/2639, or H8S/2630 with the I2C bus interface option added. Rev. 6.00 Feb 22, 2005 page 1429 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register ICMR0--I2C Bus Mode Register ICMR1--I2C Bus Mode Register Bit : 7 MLS Initial value : R/W : 0 R/W 6 WAIT 0 R/W 5 CKS2 0 R/W 4 CKS1 0 R/W 3 CKS0 0 R/W H'FF7F H'FF87 2 BC2 0 R/W 1 BC1 0 R/W 0 BC0 0 R/W IIC0 IIC1 Bit counter Bit 2 BC2 0 Bit 1 BC1 0 1 1 0 1 Bit 0 BC0 0 1 0 1 0 1 0 1 Bit/frame Clock sync serial format 8 1 2 3 4 5 6 7 PC bus format 9 2 3 4 5 6 7 8 Transmit clock select SCRX Bit 5 bit 5, 6 IICX CKS2 0 0 Bit 4 Bit 3 Clock Transfer rate CKS1 0 1 1 0 1 1 0 0 1 1 0 1 CKS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 /28 /40 /48 /64 /80 /100 /112 /128 /56 /80 /96 /128 /160 /200 /224 /256 = 5 MHz 179kHz 125kHz 104kHz 78.1kHz 62.5kHz 50.0kHz 44.6kHz 39.1kHz 89.3kHz 62.5kHz 52.1kHz 39.1kHz 31.3kHz 25.0kHz 22.3kHz 19.5kHz = 8 MHz = 10 MHz = 16 MHz = 20 MHz 286 kHz 357 kHz 571 kHz* 714 kHz* 200 kHz 250 kHz 400 kHz 500 kHz* 167 kHz 208 kHz 333 kHz 417 kHz* 125 kHz 156 kHz 250 kHz 313 kHz 100 kHz 125 kHz 200 kHz 250 kHz 80.0 kHz 100 kHz 160 kHz 200 kHz 71.4 kHz 89.3 kHz 143 kHz 179 kHz 62.5 kHz 78.1 kHz 125 kHz 156 kHz 143 kHz 179 kHz 286 kHz 357 kHz 100 kHz 125 kHz 200 kHz 250 kHz 83.3 kHz 104 kHz 167 kHz 208 kHz 62.5 kHz 78.1 kHz 125 kHz 156 kHz 50.0 kHz 62.5 kHz 100 kHz 125 kHz 40.0 kHz 50.0 kHz 80.0 kHz 100 kHz 35.7 kHz 44.6 kHz 71.4 kHz 89.3 kHz 31.3 kHz 39.1 kHz 62.5 kHz 78.1 kHz Note: * These rates are outside the ranges stipulated in the I2C bus interface specifications (normal mode: max. 100 kHz, high-speed mode: max. 400 kHz). Wait insert bit 0 1 Send data followed by acknowledge bit. Insert wait between data and acknowledge bit. MSB-first/LSB-first select 0 1 MSB first LSB first Note: This register is valid only on the H8S/2638, H8S/2639, or H8S/2630 with the I2C bus interface option added. Rev. 6.00 Feb 22, 2005 page 1430 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register SAR0--Slave Address Register SAR1--Slave Address Register Bit : 7 SVA6 Initial value : R/W : 0 R/W 6 SVA5 0 R/W 5 SVA4 0 R/W 4 SVA3 0 R/W Slave address Format select DDCSWR bit 6 SW 0 SAR bit 0 FS 0 SARX bit 0 FSX 0 1 H'FF7F H'FF87 3 SVA2 0 R/W 2 SVA1 0 R/W 1 SVA0 0 R/W 0 FS 0 R/W IIC0 IIC1 Operating mode I2C bus format * SAR and SARX slave addresses recognized 1 0 1 1 3/4 3/4 (initial value) I2C bus format * SAR slave address recognized * SARX slave address ignored I2C bus format * SAR slave address ignored * SARX slave address recognized Synchronous serial format * SAR and SARX slave addresses ignored * Must not be set. Rev. 6.00 Feb 22, 2005 page 1431 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register BRR1--Bit Rate Register 1 Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W H'FF81 4 1 R/W 3 1 R/W SCI1, Smart Card Interface 1 2 1 R/W 1 1 R/W 0 1 R/W Set the serial transmit/receive bit rate Note: For details see section 13.2.8, Bit Rate Register (BRR). TDR1--Transmit Data Register 1 Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W H'FF83 4 1 R/W 3 1 R/W SCI1, Smart Card Interface 1 2 1 R/W 1 1 R/W 0 1 R/W Store serial transmit data RDR1--Receive Data Register 1 Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R H'FF85 4 0 R 3 0 R SCI1, Smart Card Interface 1 2 0 R 1 0 R 0 0 R Store serial receive data Rev. 6.00 Feb 22, 2005 page 1432 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register SCMR1--Smart Card Mode Register 1 Bit Initial value Read/Write H'FF86 SCI1, Smart Card Interface 1 3 2 SINV 0 R/W 3/4 3/4 1 7 3/4 3/4 1 6 3/4 3/4 1 5 3/4 3/4 1 4 SDIR 0 R/W 3/4 3/4 1 1 0 SMIF 0 R/W Smart Card Interface Mode Select 0 1 Operates as normal SCI (smart card interface function disabled) Smart card interface function enabled Smart Card Interface Data Invert 0 1 TDR contents are transmitted without modification Receive data is stored in RDR without modification TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Smart Card Data Interface Transfer Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first BRR2--Bit Rate Register 2 Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W H'FF89 4 1 R/W 3 1 R/W SCI2, Smart Card Interface 2 2 1 R/W 1 1 R/W 0 1 R/W Set the serial transmit/receive bit rate Note: For details see section 13.2.8, Bit Rate Register (BRR). Rev. 6.00 Feb 22, 2005 page 1433 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TDR2--Transmit Data Register 2 Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W H'FF8B 4 1 R/W 3 1 R/W SCI2, Smart Card Interface 2 2 1 R/W 1 1 R/W 0 1 R/W Store serial transmit data RDR2--Receive Data Register 2 Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R H'FF8D 4 0 R 3 0 R SCI2, Smart Card Interface 2 2 0 R 1 0 R 0 0 R Store serial receive data Rev. 6.00 Feb 22, 2005 page 1434 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register SCMR2--Smart Card Mode Register 2 Bit Initial value Read/Write H'FF8E SCI2, Smart Card Interface 2 3 2 SINV 0 R/W 3/4 3/4 1 7 3/4 3/4 1 6 3/4 3/4 1 5 3/4 3/4 1 4 SDIR 0 R/W 3/4 3/4 1 1 0 SMIF 0 R/W Smart Card Interface Mode Select 0 1 Operates as normal SCI (smart card interface function disabled) Smart card interface function enabled Smart Card Interface Data Invert 0 1 TDR contents are transmitted without modification Receive data is stored in RDR without modification TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Smart Card Interface Data Transfer Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first ADDRA--A/D Data Register A ADDRB--A/D Data Register B ADDRC--A/D Data Register C ADDRD--A/D Data Register D Bit Initial value Read/Write 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R H'FF90 H'FF92 H'FF94 H'FF96 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R A/D Converter A/D Converter A/D Converter A/D Converter AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 3/43/43/43/43/43/4 0 R 0 R 0 R 2 1 0 Rev. 6.00 Feb 22, 2005 page 1435 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register ADCSR--A/D Control/Status Register Bit Initial value Read/Write 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W H'FF98 3 CH3 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 A/D Converter CH0 0 R/W Channel Select 2 to 0 CH3 0 CH2 0 CH1 0 1 1 0 1 1 0 0 1 1 0 1 CH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Single Mode (SCAN = 0) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 Setting prohibited Setting prohibited Setting prohibited Setting prohibited Scan Mode (SCAN = 1) AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 AN8 AN8, AN9 AN8 to AN10 AN8 to AN11 Setting prohibited Setting prohibited Setting prohibited Setting prohibited Channel Select 3 0 1 Scan Mode 0 1 A/D Start 0 1 A/D conversion stopped * Single mode: A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends * Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode Single mode Scan mode AN8 to AN11 are group 0 analog input pins AN0 to AN3 are group 0 analog input pins, AN4 to AN7 are group 1 analog input pins A/D Interrupt Enable 0 1 A/D End Flag 0 [Clearing conditions] * When 0 is written in the to ADF flag after reading ADF = 1 * When the DTC is activated by an ADI interrupt, and ADDR is read [Setting conditions] * Single mode: When A/D conversion ends * Scan mode: When A/D conversion ends on all specified channels A/D conversion end interrupt (ADI) request disabled A/D conversion end interrupt (ADI) request enabled 1 Note: * Only 0 can be written, to clear the flag. Rev. 6.00 Feb 22, 2005 page 1436 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register ADCR--A/D Control Register Bit Initial value Read/Write 7 TRGS1 0 R/W 6 TRGS0 0 R/W 5 1 4 1 Clock Select 0 1 0 1 0 1 Timer Trigger Select 0 1 0 1 0 1 H'FF99 3 CKS1 0 R/W 2 CKS0 0 R/W 1 1 A/D Converter 0 1 Conversion time = 530 states (max.) Conversion time = 266 states (max.) Conversion time = 134 states (max.) Conversion time = 68 states (max.) A/D conversion start by software is enabled A/D conversion start by TPU conversion start trigger is enabled Setting prohibited A/D conversion start by external trigger pin (ADTRG) is enabled Rev. 6.00 Feb 22, 2005 page 1437 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TCSR1--Timer Control/Status Register 1 Bit Initial value Read/Write 7 OVF 0 R/(W)*1 6 WT/IT 0 R/W 5 TME 0 R/W 4 0 R/W 3 0 R/W H'FFA2(W), H'FFA2(R) 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W WDT1 PSS*2 RST/NMI Clock Select 2 to 0 PSS CKS2 CKS1 CKS0 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock /2 /64 /128 /512 /2048 /8192 /32768 /131072 SUB/2*2 SUB/4*2 SUB/8*2 SUB/16*2 SUB/32*2 SUB/64*2 SUB/128*2 SUB/256*2 Overflow Period*1 (where = 20 MHz) (where SUB*2 = 32.768 kHz) 25.6 s 819.2 s 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s 15.6 ms 31.3 ms 62.5 ms 125 ms 250 ms 500 ms 1s 2s 0 1 1 0 Notes: 1. An overflow period is the time interval between the start of counting up from H'00 on the TCNT and the occurrence of a TCNT overflow. 2. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask, W-mask versions, and H8S/2635 Group only, but are not available in the other versions. Reset or NMI 0 1 NMI request Internal reset request Prescaler Select 0 1 The TCNT counts frequency-division clock pulses of the based prescaler (PSM) The TCNT counts frequency-division clock pulses of the SUB*-based prescaler (PSS) Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask, W-mask versions, and H8S/2635 Group only. These functions cannot be used with the other versions, and in them the PSS bit is reserved. Only 0 should be written to this bit. Timer Enable 0 1 TCNT is initialized to H'00 and halted TCNT counts Timer Mode Select 0 1 Overflow Flag 0 [Clearing conditions] * Write 0 in the TME bit (Only applies to WDT1) * Read TCSR* when OVF = 1, then write 0 in OVF [Setting condition] * When TCNT overflows (changes from H'FF to H'00) (When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset) Interval timer mode: WDT1 requests an interval timer interrupt (WOVI) from the CPU when the TCNT overflows Watchdog timer mode: WDT1 requests a reset or an NMI interrupt from the CPU when the TCNT overflows 1 Note: * When interval timer interrupts are disabled and OVF is polled, read the OVF = 1 state at least twice. Notes: TCSR1 register differs from other registers in being more difficult to write to. For details see section 12.2.4, Notes on Register Access. 1. Only 0 can be written, to clear the flag. 2. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask, W-mask versions, and H8S/2635 Group only. Rev. 6.00 Feb 22, 2005 page 1438 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register TCNT1--Timer Counter 1 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FFA2(W), H'FFA3(R) 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W WDT1 Up-counter Note: TCNT1 register differs from other registers in being more difficult to write to. For details see section 12.2.4, Notes on Register Access. DADR0-- D/A Data Register 0 DADR1-- D/A Data Register 1 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FFA4 H'FFA5 3 0 R/W 2 0 R/W 1 0 R/W 0 0 D/A0, 1 D/A0, 1 R/W Store data to be converted Note: These registers are not available in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 1439 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register DACR01-- D/A Control Register 01 Bit Initial value Read/Write 7 DAOE1 0 R/(W)* 6 DAOE0 0 R/W 5 DAE 0 R/W 4 1 H'FFA6 3 1 2 1 1 1 0 1 D/A0, 1 D/A Enable 0 0 1 1 0 1 * 0 1 0 1 * Disabled on channels 0 and 1 Enabled on channel 0 Disabled on channel 1 Enabled on channels 0 and 1 Disabled on channel 0Enabled on channel 1 Enabled on channels 0 and 1 Enabled on channels 0 and 1 *: Don't care D/A Output Enable 0 0 1 Analog output DA0 is disabled D/A conversion is enabled on channel 0. Analog output DA0 is enabled D/A Output Enable 1 0 1 Analog output DA1 is disabled D/A conversion is enabled on channel 1. Analog output DA1 is enabled Note: This register is not available in the H8S/2635 and H8S/2634. Rev. 6.00 Feb 22, 2005 page 1440 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register FLMCR1--Flash Memory Control Register 1 Bit Initial value Read/Write 7 FWE * R 6 SWE 0 R/W 5 ESU 0 R/W 4 PSU 0 R/W 3 H'FFA8 2 PV 0 R/W 1 E 0 R/W Flash Memory 0 P 0 R/W EV 0 R/W Erase 0 1 Erase mode cleared Transition to erase mode [Setting condition] * When FWE = 1, SWE = 1, and ESU = 1 Program 0 1 Program mode cleared Transition to program mode [Setting condition] * When FWE = 1, SWE = 1, and PSU = 1 Program-Verify 0 1 Program-verify mode cleared Transition to program-verify mode [Setting condition] * When FWE = 1 and SWE = 1 Erase-Verify 0 Erase-verify mode cleared 1 Transition to erase-verify mode [Setting condition] * When FWE = 1 and SWE = 1 Program Setup 0 1 Program setup cleared Program setup [Setting condition] * When FWE = 1 and SWE = 1 Erase Setup 0 1 Erase setup cleared Erase setup [Setting condition] * When FWE = 1 and SWE = 1 Software Write Enable Bit 0 1 Writes disabled Writes enabled [Setting condition] * When FWE = 1 Flash Write Enable Bit 0 1 When a low level is input to the FWE pin (hardware-protected state) When a high level is input to the FWE pin Note: * Determined by the state of the FWE pin. Rev. 6.00 Feb 22, 2005 page 1441 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register FLMCR2--Flash Memory Control Register 2 Bit Initial value Read/Write 7 FLER 0 R 6 0 5 0 4 0 H'FFA9 3 0 2 0 Flash Memory 1 0 0 0 Flash Memory Error 0 Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] * Power-on reset or hardware standby mode An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] * See section 21A.10.3, 21B.10.3, Error Protection 1 Rev. 6.00 Feb 22, 2005 page 1442 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register EBR1--Erase Block Register 1 EBR2--Erase Block Register 2 EBR1 Bit Initial value Read/Write EBR2 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 EB13*3 0 R/W 4 EB12*3 0 R/W 15 EB7 0 R/W 14 EB6 0 R/W 13 EB5 0 R/W 12 EB4 0 R/W H'FFAA H'FFAB Flash Memory Flash Memory 11 EB3 0 R/W 10 EB2 0 R/W 9 EB1 0 R/W 8 EB0 0 R/W 3 EB11*2 0 R/W 2 EB10*1 0 R/W 1 EB9 0 R/W 0 EB8 0 R/W Specify the flash memory erase area * H8S/2636 Block (Size) EB0 (1 kbyte) EB1 (1 kbyte) EB2 (1 kbyte) EB3 (1 kbyte) EB4 (28 kbytes) EB5 (16 kbytes) EB6 (8 kbytes) EB7 (8 kbytes) EB8 (32 kbytes) EB9 (32 kbytes) Addresses H'000000 to H'0003FF H'000400 to H'0007FF H'000800 to H'000BFF H'000C00 to H'000FFF H'001000 to H'007FFF H'008000 to H'00BFFF H'00C000 to H'00DFFF H'00E000 to H'00FFFF H'010000 to H'017FFF H'018000 to H'01FFFF * H8S/2638, H8S/2639 Block (Size) Addresses EB0 (4 kbytes) H'000000 to H'000FFF EB1 (4 kbytes) H'001000 to H'001FFF EB2 (4 kbytes) H'002000 to H'002FFF EB3 (4 kbytes) H'003000 to H'003FFF EB4 (4 kbytes) H'004000 to H'004FFF EB5 (4 kbytes) H'005000 to H'005FFF EB6 (4 kbytes) H'006000 to H'006FFF EB7 (4 kbytes) H'007000 to H'007FFF EB8 (32 kbytes) H'008000 to H'00FFFF EB9 (64 kbytes) H'010000 to H'01FFFF EB10 (64 kbytes) H'020000 to H'02FFFF EB11 (64 kbytes) H'030000 to H'03FFFF * H8S/2630 Block (Size) EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) EB8 (32 kbytes) EB9 (64 kbytes) EB10 (64 kbytes) EB11 (64 kbytes) EB12 (64 kbytes) EB13 (64 kbytes) * H8S/2635 Block (Size) EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) EB8 (32 kbytes) EB9 (64 kbytes) EB10 (64 kbytes) Addresses H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF H'008000 to H'00FFFF H'010000 to H'01FFFF H'020000 to H'02FFFF Addresses H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF H'008000 to H'00FFFF H'010000 to H'01FFFF H'020000 to H'02FFFF H'030000 to H'03FFFF H'040000 to H'04FFFF H'050000 to H'05FFFF Notes: 1. On the H8S/2636, these bits are reserved. 2. Reserved in the H8S/2636 and H8S/2635. 3. Reserved in the H8S/2638, H8S/2639, and H8S/2635. Rev. 6.00 Feb 22, 2005 page 1443 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register FLPWCR--Flash Memory Power Control Register H'FFAC Bit Initial value Read/Write 7 PDWND 0 R/W Flash Memory 3/4 0 R 6 3/4 0 R 5 3/4 0 R 4 3/4 0 R 3 3/4 0 R 2 3/4 0 R 1 3/4 0 R 0 Power-Down Disable 0 1 Transition to flash memory power-down mode enabled Transition to flash memory power-down mode disabled PORT1--Port 1 Register Bit Initial value Read/Write 7 P17 6 P16 5 P15 4 P14 H'FFB0 3 P13 2 P12 1 P11 0 P10 Port 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R State of the port 1 pins Note: * Determined by state of pins P17 to P10. PORT3--Port 3 Register Bit Initial value Read/Write H'FFB2 Port 2 P32 1 P31 0 P30 3/4 3/4 7 3/4 3/4 6 5 P35 4 P34 3 P33 Undefined Undefined 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R State of the port 3 pins Note: * Determined by state of pins P35 to P30. Rev. 6.00 Feb 22, 2005 page 1444 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register PORT4--Port 4 Register Bit Initial value Read/Write 7 P47 6 P46 5 P45 4 P44 H'FFB3 3 P43 2 P42 1 P41 0 P40 Port 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R State of the port 4 pins Note: * Determined by state of pins P47 to P40. PORT9--Port 9 Register Bit Initial value Read/Write H'FFB8 Port 2 P92 1 P91 0 P90 3/4 3/4 7 3/4 3/4 6 3/4 3/4 5 3/4 3/4 4 3 P93 Undefined Undefined Undefined Undefined 3/4* R 3/4* R 3/4* R 3/4* R State of the port 9 pins Note: * Determined by state of pins P93 to P90. PORTA--Port A Register Bit Initial value Read/Write H'FFB9 Port 2 PA2 1 PA1 0 PA0 3/4 3/4 7 3/4 3/4 6 3/4 3/4 5 3/4 3/4 4 3 PA3 Undefined Undefined Undefined Undefined 3/4* R 3/4* R 3/4* R 3/4* R State of the port A pins Note: * Determined by state of pins PA3 to PA0. Rev. 6.00 Feb 22, 2005 page 1445 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register PORTB--Port B Register Bit Initial value Read/Write 7 PB7 6 PB6 5 PB5 4 PB4 H'FFBA 3 PB3 2 PB2 1 PB1 0 PB0 Port 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R State of the port B pins Note: * Determined by state of pins PB7 to PB0. PORTC--Port C Register Bit Initial value Read/Write 7 PC7 6 PC6 5 PC5 4 PC4 H'FFBB 3 PC3 2 PC2 1 PC1 0 PC0 Port 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R State of the port C pins Note: * Determined by state of pins PC7 to PC0. PORTD--Port D Register Bit Initial value Read/Write 7 PD7 6 PD6 5 PD5 4 PD4 H'FFBC 3 PD3 2 PD2 1 PD1 0 PD0 Port 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R State of the port D pins Note: * Determined by state of pins PD7 to PD0. Rev. 6.00 Feb 22, 2005 page 1446 of 1484 REJ09B0103-0600 Appendix B Internal I/O Register PORTE--Port E Register Bit Initial value Read/Write 7 PE7 6 PE6 5 PE5 4 PE4 H'FFBD 3 PE3 2 PE2 1 PE1 0 PE0 Port 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R State of the port E pins Note: * Determined by state of pins PE7 to PE0. PORTF--Port F Register Bit Initial value Read/Write 7 PF7 6 PF6 5 PF5 4 PF4 H'FFBE 3 PF3 Port 3/4* R 3/4* R 3/4* R 3/4* R 3/4* R 3/4 3/4 2 3/4 3/4 1 0 PF0 Undefined Undefined 3/4* R State of the port F pins Note: * Determined by state of pins PF7 to PF3, PF0. Rev. 6.00 Feb 22, 2005 page 1447 of 1484 REJ09B0103-0600 Appendix C I/O Port Block Diagrams Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagrams Reset Internal data bus R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C P1n *1 From internal address bus Internal address bus System controller Address output enable PPG module*2 Pulse output enable Pulse output WDR1 TPU module Output compare Output/PWM output enable Output compare output/ PWM output RDR1 RPOR1 Input capture input Legend: WDDR1: Write to P1DDR WDR1: Write to P1DR RDR1: Read P1DR RPOR1: Read port 1 n = 0 or 1 Notes: 1. Priority order: Address output > output compare output > PWM output pulse output > DR output 2. The PPG module is not implemented in the H8S/2635 and H8S/2634. Figure C-1 (a) Port 1 Block Diagram (Pins P10 and P11) Rev. 6.00 Feb 22, 2005 page 1448 of 1484 REJ09B0103-0600 Appendix C I/O Port Block Diagrams Reset WDDR1 Reset R Q D P1nDR C *1 WDR1 P1n RDR1 RPOR1 Internal address bus System controller Address output enable PPG module*2 Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input External clock input Legend: WDDR1: WDR1: RDR1: RPOR1: n = 2 or 3 Write to P1DDR Write to P1DR Read P1DR Read port 1 Notes: 1. Priority order: Address output > output compare output/PWM output > pulse output > DR output 2. The PPG module is not implemented in the H8S/2635 and H8S/2634. Figure C-1 (b) Port 1 Block Diagram (Pins P12 and P13) Rev. 6.00 Feb 22, 2005 page 1449 of 1484 REJ09B0103-0600 Internal data bus R Q D P1nDDR C Appendix C I/O Port Block Diagrams Reset R Q D P14DDR C WDDR1 Reset R Q D P14DR C WDR1 P14 *1 RDR1 RPOR1 Internal data bus PPG module*2 Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input Interrupt controller IRQ0 interrupt input Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Notes: 1. Priority order: output compare output/PWM output > pulse output > DR output 2. The PPG module is not implemented in the H8S/2635 and H8S/2634. Figure C-1 (c) Port 1 Block Diagram (Pin P14) Rev. 6.00 Feb 22, 2005 page 1450 of 1484 REJ09B0103-0600 Appendix C I/O Port Block Diagrams Reset R Q D P15DDR C WDDR1 Reset R Q D P15DR C WDR1 PPG module*2 Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 P15 *1 RPOR1 Internal data bus Input capture input External clock input Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Notes: 1. Priority order: output compare output/PWM output > pulse output > DR output 2. The PPG module is not implemented in the H8S/2635 and H8S/2634. Figure C-1 (d) Port 1 Block Diagram (Pin P15) Rev. 6.00 Feb 22, 2005 page 1451 of 1484 REJ09B0103-0600 Appendix C I/O Port Block Diagrams Reset R Q D P16DDR C WDDR1 Reset R Q D P16DR C *1 P16 WDR1 Internal data bus PPG module*2 Pulse output enable Pulse output TPU module Output compare Output/PWM output enable Output compare output/ PWM output Input capture input Input controller IRQ1 interrupt input RDR1 RPOR1 Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Notes: 1. Priority order: output compare output/PWM output > pulse output > DR output 2. The PPG module is not implemented in the H8S/2635 and H8S/2634. Figure C-1 (e) Port 1 Block Diagram (Pin P16) Rev. 6.00 Feb 22, 2005 page 1452 of 1484 REJ09B0103-0600 Appendix C I/O Port Block Diagrams Reset R Q D P17DDR C WDDR1 Reset R Q D P17DR C *1 P17 WDR1 PPG module*2 Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Internal data bus Input capture input External clock input Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Notes: 1. Priority order: output compare output/PWM output > pulse output > DR output 2. The PPG module is not implemented in the H8S/2635 and H8S/2634. Figure C-1 (f) Port 1 Block Diagram (Pin P17) Rev. 6.00 Feb 22, 2005 page 1453 of 1484 REJ09B0103-0600 Appendix C I/O Port Block Diagrams C.2 Port 3 Block Diagrams Reset R Q D P30DDR C *1 WDDR3 REset R Q D P30DR C WDR3 *2 Reset R Q D P30ODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data P30 Internal data bus TxD0 RDR3 RPOR3 Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2. Open drain control signal Figure C-2 (a) Port 3 Block Diagram (Pin P30) Rev. 6.00 Feb 22, 2005 page 1454 of 1484 REJ09B0103-0600 Appendix C I/O Port Block Diagrams Reset R Q D P31DDR C *1 WDDR3 Internal data bus Reset P31 R Q D P31DR C *2 WDR3 Reset R Q D P31ODR C WODR3 RODR3 SCI module RDR3 Serial receive data enable RPOR3 Serial receive data RxD0 Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2. Open drain control signal Figure C-2 (b) Port 3 Block Diagram (Pin P31) Rev. 6.00 Feb 22, 2005 page 1455 of 1484 REJ09B0103-0600 Appendix C I/O Port Block Diagrams Reset Internal data bus R Q D P32DDR C *2 WDDR3 Reset R Q D P32DR C WDR3 *3 Reset R Q D P32ODR C WODR3 RODR3 P32 *1 IIC1 module* SDA1 output 4 IIC1 output enable SDA1 input SCI module Serial clock output enable Serial clock output Serial clock input enable RDR3 RPOR3 Serial clock input Interrupt controller IRQ4 interrupt input Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. 2. 3. 4. Priority order: IIC output > Serial clock output > DR output Output enable signal Open drain control signal The IIC1 module is available as an option in the H8S/2638, H8S/2639, H8S/2630. Figure C-2 (c) Port 3 Block Diagram (Pin P32) Rev. 6.00 Feb 22, 2005 page 1456 of 1484 REJ09B0103-0600 Appendix C I/O Port Block Diagrams Reset R Q D P33DDR C *1 WDDR3 Reset R Q D P33DR C WDR3 *2 Reset R Q D P33ODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data TxD1 P33 RDR3 RPOR3 IIC1 module*3 SCL1 output IIC1 output enable SCL1 input Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2. Open drain control signal 3. The IIC1 module is available as an option in the H8S/2638, H8S/2639, H8S/2630. Figure C-2 (d) Port 3 Block Diagram (Pin P33) Rev. 6.00 Feb 22, 2005 page 1457 of 1484 REJ09B0103-0600 Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D P34DDR C *1 *3 WDDR3 P34 R Q D P34DR C WDR3 Reset R Q D P34ODR C WODR3 RODR3 *2 Internal data bus SCI module Serial receive data enable Serial receive data RxD1 Reset RDR3 RPOR3 IIC0 module*4 SDA0 output IIC0 output enable SDA0 Input Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. 2. 3. 4. Output enable signal Open drain control signal Priority order: IIC output > DR output The IIC0 module is available as an option in the H8S/2638, H8S/2639, H8S/2630. Figure C-2 (e) Port 3 Block Diagram (Pin P34) Rev. 6.00 Feb 22, 2005 page 1458 of 1484 REJ09B0103-0600 Appendix C I/O Port Block Diagrams Reset R Q D P35DDR C *2 WDDR3 Internal data bus Reset R Q D P35DR C WDR3 P35 *1 *3 Reset R Q D P35ODR C WODR3 RODR3 SCI module Serial clock output enable Serial clock output Serial clock input enable RDR3 RPOR3 Serial clock input IIC0 module*4 SCL0 output IIC0 output enable SCL0 input Interrupt controller IRQ5 interrupt input Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Priority order: IIC output > Serial clock output > DR output 2. Output enable signal 3. Open drain control signal 4. The IIC0 module is available as an option in the H8S/2638, H8S/2639, H8S/2630. Figure C-2 (f) Port 3 Block Diagram (Pin P35) Rev. 6.00 Feb 22, 2005 page 1459 of 1484 REJ09B0103-0600 Appendix C I/O Port Block Diagrams C.3 Port 4 Block Diagram Internal data bus A/D converter module Analog input RPOR4 P4n Legend: RPOR4: Read port 4 n = 0 to 5 Figure C-3 (a) Port 4 Block Diagram (Pins P40 to P45) RPOR4 P4n Internal data bus A/D converter module Analog input D/A converter module* Output enable Analog output Legend: RPOR4: Read port 4 Notes: * The D/A converter is not implemented in the H8S/2635 and H8S/2634. n = 6, 7 Figure C-3 (b) Port 4 Block Diagram (Pins P46, P47) Rev. 6.00 Feb 22, 2005 page 1460 of 1484 REJ09B0103-0600 Appendix C I/O Port Block Diagrams C.4 Port 9 Block Diagram Internal data bus A/D converter module Analog input RPOR9 P9n Legend: RPOR9: Read port 9 n = 0 to 3 Figure C-4 Port 9 Block Diagram (Pins P90 to P93) Rev. 6.00 Feb 22, 2005 page 1461 of 1484 REJ09B0103-0600 Appendix C I/O Port Block Diagrams C.5 Port A Block Diagram Reset R Q D PA0PCR C WPCRA RPCRA Reset R Q D PA0DDR C *1 WDDRA Reset R Q D PA0DR C WDRA Reset R Q D PA0ODR C WODRA RODRA PA0 Modes 4/5/6 Address enable *2 RDRA RPORA Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Notes: 1. Output enable signal 2. Open drain control signal Figure C-5 (a) Port A Block Diagram (Pin PA0) Rev. 6.00 Feb 22, 2005 page 1462 of 1484 REJ09B0103-0600 Internal address bus Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D PA1PCR C WPCRA RPCRA Smart card mode signal TxD output TxD output enable Reset R Q D PA1DDR C WDDRA Reset R Q D PA1DR C WDRA Reset R Q D PA1ODR C WODRA RODRA *1 PA1 Modes 4/5/6 Address enable *2 RDRA RPORA Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Notes: 1. Output enable signal 2. Open drain control signal Figure C-5 (b) Port A Block Diagram (Pin PA1) Rev. 6.00 Feb 22, 2005 page 1463 of 1484 REJ09B0103-0600 Internal address bus Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D PA2PCR C Internal address bus WPCRA RPCRA Internal data bus RxD input enable Reset R Q D PA2DDR C *1 WDDRA Reset R Q D PA2DR C WDRA Reset R Q D PA2ODR C WODRA RODRA PA2 Modes 4/5/6 Address enable *2 RDRA RxD input RPORA Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Notes: 1. Output enable signal 2. Open drain control signal Figure C-5 (c) Port A Block Diagram (Pin PA2) Rev. 6.00 Feb 22, 2005 page 1464 of 1484 REJ09B0103-0600 Appendix C I/O Port Block Diagrams Reset R Q D PA3PCR C WPCRA RPCRA SCK input enable SCK output SCK output enable Reset R Q D PA3DDR C WDDRA Reset R Q D PA3DR C WDRA Reset R Q D PA3ODR C WODRA RODRA *1 PA3 Modes 4/5/6 Address enable *2 RDRA SCK input RPORA Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Notes: 1. Output enable signal 2. Open drain control signal Figure C-5 (d) Port A Block Diagram (Pin PA3) Rev. 6.00 Feb 22, 2005 page 1465 of 1484 REJ09B0103-0600 Internal address bus Internal data bus Appendix C I/O Port Block Diagrams C.6 Port B Block Diagram Reset R Q D PBnPCR C WPCRB RPCRB (Output compare) TPU output TPU output enable Reset R Q D PBnDDR C WDDRB Reset R Q D PBnDR C WDRB Reset R Q D PBnODR C WODRB RODRB *1 PBn Modes 4/5/6 Address enable *2 RDRB TPU input (Input capture) RPORB Legend: Notes: 1. Output enable signal 2. Open drain control signal WDDRB: Write to PBDDR WDRB: Write to PBDR WODRB: Write to PBODR WPCRB: Write to PBPCR RDRB: Read PBDR RPORB: Read port B RODRB: Read PBODR RPCRB: Read PBPCR n = 0 to 7 Figure C-6 Port B Block Diagram (Pins PB0 to PB7) Rev. 6.00 Feb 22, 2005 page 1466 of 1484 REJ09B0103-0600 Internal address bus Internal data bus Appendix C I/O Port Block Diagrams C.7 Port C Block Diagram Reset R Q D PCnPCR C WPCRC RPCRC Reset R Q D PCnDDR C *1 WDDRA Reset R Q D PCnDR C WDRA *2 Reset R Q D PCnODR C WODRC RODRC PCn Modes 4/5 Mode 6 RDRC RPORC Legend: Notes: 1. Output enable signal 2. Open drain control signal WDDRA: Write to PCDDR WDRA: Write to PCDR WODRA: Write to PCODR WPCRA: Write to PCPCR RDRA: Read PCDR RPORA: Read port A RODRA: Read PCODR RPCRA: Read PCPCR n = 0 to 7 Figure C-7 Port C Block Diagram (Pins PC0 to PC7) Rev. 6.00 Feb 22, 2005 page 1467 of 1484 REJ09B0103-0600 Internal address bus Internal data bus Appendix C I/O Port Block Diagrams C.8 Port D Block Diagram Reset Internal upper data bus R Q D PDnPCR C WPCRD RPCRD Reset R Q D PDnDDR C WDDRD Reset R Q D PDnDR C WDRD External address write PDn Mode 7 Modes 4/5/6 External address upper write RDRD RPORD External address upper read Legend: WDDRD: WDRD: WPCRD: RDRD: RPORD: RPCRD: n = 0 to 7 Write to PDDDR Write to PDDR Write to PDPCR Read PDDR Read port D Read PDPCR Figure C-8 Port D Block Diagram (Pins PD0 to PD7) Rev. 6.00 Feb 22, 2005 page 1468 of 1484 REJ09B0103-0600 Appendix C I/O Port Block Diagrams C.9 Port E Block Diagram Reset Internal upper data bus WPCRE RPCRE Reset R Q D PEnDDR C WDDRE Reset R Q D PEnDR C WDRE External address write PEn Mode 7 Modes 4/5/6 RDRE RPORE External addres lower read Legend: WDDRE: WDRE: WPCRE: RDRE: RPORE: RPCRE: n = 0 to 7 Write to PEDDR Write to PEDR Write to PEPCR Read PEDR Read port E Read PEPCR Figure C-9 Port E Block Diagram (Pins PE0 to PE7) Rev. 6.00 Feb 22, 2005 page 1469 of 1484 REJ09B0103-0600 Internal lower data bus R Q D PEnPCR C Appendix C I/O Port Block Diagrams C.10 Port F Block Diagrams R Q D PF0DDR C WDDRF Reset PF0 R Q D PF0DR C WDRF RDRF RPORF Internal data bus IRQ interrupt input Reset Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C-10 (a) Port F Block Diagram (Pin PF0) Rev. 6.00 Feb 22, 2005 page 1470 of 1484 REJ09B0103-0600 Appendix C I/O Port Block Diagrams Reset R Q D PF3DDR C WDDRF Reset R Q D PF3DR C WDRF PF3 Modes 4/5/6 Internal data bus Bus controller LWR output RDRF RPORF ADTRG input IRQ3 interrupt input Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C-10 (b) Port F Block Diagram (Pin PF3) Rev. 6.00 Feb 22, 2005 page 1471 of 1484 REJ09B0103-0600 Appendix C I/O Port Block Diagrams Reset R Q D PF4DDR C WDDRF Reset R Q D PF4DR C WDRF PF4 Modes 4/5/6 Internal data bus Bus controller HWR output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C-10 (c) Port F Block Diagram (Pin PF4) Rev. 6.00 Feb 22, 2005 page 1472 of 1484 REJ09B0103-0600 Appendix C I/O Port Block Diagrams Reset R Q D PF5DDR C WDDRF Reset R Q D PF5DR C WDRF PF5 Modes 4/5/6 Internal data bus Bus controller RD output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C-10 (d) Port F Block Diagram (Pin PF5) Rev. 6.00 Feb 22, 2005 page 1473 of 1484 REJ09B0103-0600 Appendix C I/O Port Block Diagrams Reset R Q D PF6DDR C WDDRF Reset R Q D PF6DR C WDRF PF6 Modes 4/5/6 Internal data bus Bus controller AS output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C-10 (e) Port F Block Diagram (Pin PF6) Rev. 6.00 Feb 22, 2005 page 1474 of 1484 REJ09B0103-0600 Appendix C I/O Port Block Diagrams Modes 4/5/6 Reset S* R Q D D PF7DDR C WDDRF Reset R Q D PF7DR C WDRF PF7 Internal data bus RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Note: * Set priority Write to PFDDR Write to PFDR Read PFDR Read port F Figure C-10 (f) Port F Block Diagram (Pin PF7) Rev. 6.00 Feb 22, 2005 page 1475 of 1484 REJ09B0103-0600 Appendix C I/O Port Block Diagrams C.11 Port H Block Diagram Reset R Q D PHnDDR C WDDRH Reset R Q D PHnDR C WDRH PHn Internal data bus PWM module PWM output enable PWM output RDRH RPORH Legend: WDDRH: WDRH: RDRH: RPORH: n = 0 to 7 Write to PHDDR Write to PHDR Read PHDR Read port H Figure C-11 Port H Block Diagram (Pins PH0 to PH7) Rev. 6.00 Feb 22, 2005 page 1476 of 1484 REJ09B0103-0600 Appendix C I/O Port Block Diagrams C.12 Port J Block Diagram Reset R Q D PJnDDR C WDDRJ Reset R Q D PJnDR C WDRJ PJn Internal data bus PWM module PWM output enable PWM output RDRJ RPORJ Legend: WDDRJ: Write to PJDDR WDRJ: Write to PJDR RDRJ: Read PJDR RPORJ: Read port J n = 0 to 7 Figure C-12 Port J Block Diagram (Pins PJ0 to PJ7) Rev. 6.00 Feb 22, 2005 page 1477 of 1484 REJ09B0103-0600 Appendix D Pin States Appendix D Pin States D.1 Port States in Each Mode Table D-1 I/O Port States in Each Processing State MCU Port Name Operating Pin Name Mode Port 1 4, 5 6 Hardware Standby Mode T Program Execution State Sleep Mode P10 to P13 [Address output] A20 to A23 [Otherwise] I/O port Reset T Software Standby Mode P10 to P13 [Address output, OPE = 0] T [Address output, OPE = 1] kept [Otherwise] kept P14 to P17 kept P14 to P17 I/O port P10 to P17 I/O port I/O port Input port Input port [Address output] A19 to A17 [Otherwise] I/O port 7 Port 3 Port 4 Port 9 Port A 4 to 7 4 to 7 4 to 7 4, 5 6 T T T L T T T T T T kept kept T T [Address output, OPE = 0] T [Address output, OPE = 1] kept [Otherwise] kept kept [Address output, OPE = 0] T [Address output, OPE = 1] kept [Otherwise] kept kept 7 Port B 4, 5 6 T L T T T T I/O port [Address output] A15 to A8 [Otherwise] I/O port 7 T T I/O port Rev. 6.00 Feb 22, 2005 page 1478 of 1484 REJ09B0103-0600 Appendix D Pin States MCU Port Name Operating Pin Name Mode Port C 4, 5 Hardware Standby Mode T Reset L Software Standby Mode [OPE = 0] T [OPE = 1] kept [DDR = 1, OPE = 0] T [DDR = 1, OPE = 1] kept [DDR = 0] kept kept T kept kept T kept [DDR = 0] T [DDR = 1] H [DDR = 0] T [DDR = 1] H [OPE = 0] T [OPE = 1] H kept [OPE = 0] T [OPE = 1] H kept Program Execution State Sleep Mode A7 to A0 6 T T [DDR = 1] A7 to A0 [DDR = 0] I/O port 7 Port D 4 to 6 7 Port E 4 to 6 8 bit bus T T T T T T T T T T T I/O port Data bus I/O port I/O port Data bus I/O port [DDR = 0] T [DDR = 1] Clock output [DDR = 0] T [DDR = 1] Clock output AS 16 bit T bus 7 PF7/ 4 to 6 T Clock output 7 T T PF6/AS 4 to 6 H T 7 PF5/RD PF4/HWR 4 to 6 T H T T I/O port RD, HWR 7 T T I/O port Rev. 6.00 Feb 22, 2005 page 1479 of 1484 REJ09B0103-0600 Appendix D Pin States MCU Port Name Operating Pin Name Mode PF3/LWR 4 to 6 Hardware Standby Mode T Reset H Software Standby Mode [OPE = 0] T [OPE = 1] H kept kept kept kept H T Program Execution State Sleep Mode LWR 7 PF0 Port H Port J HTxD0, HTxD1 HRxD0, HRxD1 4 to 7 4 to 7 4 to 7 4 to 7 4 to 7 T T T T H Input T T T T T T I/O port I/O port I/O port I/O port Tx output Rx output Legend: H: High level L: Low level T: High impedance kept: Input port becomes high-impedance, output port retains state DDR: Data direction register OPE: Output port enable Rev. 6.00 Feb 22, 2005 page 1480 of 1484 REJ09B0103-0600 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the signal low at least 10 states before the signal goes low, as shown below. must remain low until signal goes low (delay from low to high: 0 ns or more). STBY t1 10 tcyc RES t2 0 ns Figure E-1 Timing of Transition to Hardware Standby Mode (2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents does not have to be driven low as in (1). do not need to be retained, Timing of Recovery from Hardware Standby Mode STBY t 100 ns RES tOSC tNMIRH NMI Figure E-2 Timing of Recovery from Hardware Standby Mode Rev. 6.00 Feb 22, 2005 page 1481 of 1484 REJ09B0103-0600 YBTS signal low and the NMI signal high approximately 100 ns or more before Drive the goes high to execute a reset. SER SER SER YBTS SER YBTS SER YBTS Appendix F Product Code Lineup Appendix F Product Code Lineup Table F-1 H8S/2636, H8S/2638, H8S/2639, and H8S/2630 Product Code Lineup Product Code HD64F2636 Mark Code HD64F2636F HD64F2636UF Mask ROM HD6432636 version HD6432636F HD6432636UF H8S/2638 F-ZTAT version HD64F2638 HD64F2638F HD64F2638UF Functions No subclock function Subclock function No subclock function Subclock function No subclock function or I2C bus interface Subclock function, 2 no I C bus interface Packages 128-pin QFP (FP-128B) 128-pin QFP (FP-128B) 128-pin QFP (FP-128B) 128-pin QFP (FP-128B) 128-pin QFP (FP-128B) 128-pin QFP (FP-128B) Product Type H8S/2636 F-ZTAT version HD64F2638WF Subclock function and 128-pin QFP I2C bus interface (FP-128B) Mask ROM HD6432638 version HD6432638F HD6432638UF No subclock function or I2C bus interface Subclock function, 2 no I C bus interface 128-pin QFP (FP-128B) 128-pin QFP (FP-128B) HD6432638WF Subclock function and 128-pin QFP I2C bus interface (FP-128B) H8S/2639 F-ZTAT version HD64F2639 HD64F2639UF Subclock function, 2 no I C bus interface 128-pin QFP (FP-128B) HD64F2639WF Subclock function and 128-pin QFP 2 (FP-128B) I C bus interface Mask ROM HD6432639 version HD6432639UF Subclock function, no I2C bus interface 128-pin QFP (FP-128B) HD6432639WF Subclock function and 128-pin QFP I2C bus interface (FP-128B) Rev. 6.00 Feb 22, 2005 page 1482 of 1484 REJ09B0103-0600 Appendix F Product Code Lineup Product Type H8S/2630 F-ZTAT version Product Code HD64F2630 Mark Code HD64F2630F HD64F2630UF Functions No subclock function or I2C bus interface Subclock function, 2 no I C bus interface Packages 128-pin QFP (FP-128B) 128-pin QFP (FP-128B) HD64F2630WF Subclock function and 128-pin QFP 2 (FP-128B) I C bus interface Mask ROM HD6432630 version HD6432630F HD6432630UF No subclock function or I2C bus interface Subclock function, no I2C bus interface 128-pin QFP (FP-128B) 128-pin QFP (FP-128B) HD6432630WF Subclock function and 128-pin QFP I2C bus interface (FP-128B) H8S/2635 F-ZTAT version HD64F2635 HD64F2635F HD6432635F HD6432634F Subclock function, no I2C bus interface Subclock function, no I2C bus interface Subclock function, 2 no I C bus interface 128-pin QFP (FP-128B) 128-pin QFP (FP-128B) 128-pin QFP (FP-128B) Mask ROM HD6432635* version HD6432634* Note: * Under development Rev. 6.00 Feb 22, 2005 page 1483 of 1484 REJ09B0103-0600 Appendix G Package Dimensions Appendix G Package Dimensions Figure G-1 shows the package dimensions of the H8S/2636, H8S/2638, H8S/2639, H8S/2630, H8S/2635, and H8S/2634. JEITA Package Code P-QFP128-14x20-0.50 RENESAS Code PRQP0128KB-A Previous Code FP-128B/FP-128BV MASS[Typ.] 1.7g HD *1 D 65 64 102 103 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp HE E b1 Reference Symbol Dimension in Millimeters Min Nom 20 14 2.70 21.8 15.8 22.0 16.0 22.2 16.2 3.15 0.00 0.17 0.10 0.22 0.20 0.12 0.17 0.15 0 0.5 8 0.22 0.25 0.27 Max *2 c1 c D E A2 128 1 ZD Index mark 38 39 ZE Terminal cross section HD HE A A1 bp F b1 c A A2 c c1 A1 L L1 e *3 y bp x y ZD ZE L L1 0.3 0.75 0.75 0.5 1.0 0.10 0.10 M x Detail F 0.7 Figure G-1 FP-128B Package Dimensions Rev. 6.00 Feb 22, 2005 page 1484 of 1484 REJ09B0103-0600 Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Publication Date: 1st Edition, December 1999 Rev.6.00, February 22, 2005 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. (c) 2005. Renesas Technology Corp. All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 http://www.renesas.com Colophon 2.0 H8S/2639, H8S/2638, H8S/2636, H8S/2630, H8S/2635 Group Hardware Manual |
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